Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

: Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.


Introduction
The conventional metal oxide semiconductor (MOSFET) has a subthreshold swing limit of 60 mV/dec at room temperature, which limits the application of MOSFET devices in ultra-low power integrated circuits (ICs) [1,2]. In this context, the tunneling field effect transistor (TFET), which can break through the 60 mV/dec sub-threshold swing limit, is a competitive candidate to replace MOSFET in low power ICs [3][4][5].
Over the last decade, TFETs have gone through tremendous explorations, including SiGe source, spacer engineering, highly doped abrupt source profiles, double gate architectures, Band gap engineering using III-V materials [6][7][8] and vertical tunnel [9,10]. These explorations are mainly aimed at breaking through the subthreshold swing of 60 mV/dec and obtaining a higher open state current. However, in the IC industry, electrostatic discharge (ESD) impact phenomena may be generated from processing, packaging, transportation, system integration to use. With the decrease of the process size, advanced technologies such as thin gate oxide layer, short channel and shallow junction depth, while improving device performance, will also cause a significant decline in the anti-ESD impact capability for these devices [11]. According to the reliability analysis of the United States Center, 15% of electronic equipment hardware failures are caused by ESD impact, and in electrostatic highly sensitive integrated circuits, 60% of electronic equipment hardware failures are caused by ESD impact [12]. It shows that the electrostatic discharge phenomenon of TFET is a major reliability problem in the sub-10 nm node technology [13,14].
The analysis of ESD performance of TFET devices in the early stage can not only shorten the design time but also obtain devices with better ESD shock resistance, especially considering that TFET is expected to be a strong competitor to replace Fin FET in sub-10 nm node technology. But under ESD impact, the triggering voltage of TFET is higher than expected, which reduces its application in ESD protection. To enhanced TFET's ESD performance, SiGe Source/Drain TFET has been proposed, this new type of TFET's ESD characteristics has been improved compared with Conventional TFET [15]; N+ pocket TFET has also been proposed to obtain a better ESD design window [16]; the double current path phenomenon in ggTFETs has been proposed to explore ESD phenomenon [17,18].
Based on these works, this paper proposes a SiGe S/D PNN TFET. Sentaurus TCAD software(Mountain View, California, USA) is used to simulate the exhaustion of PNN TFET and Conventional TFET [19][20][21]. The simulation results show that the trigger voltage and failure current of PNN TFET are better than that of Conventional TFET. In addition, this paper makes a comprehensive analysis of SiGe PNN TFET. Different from the doublecurrent-path phenomenon of Conventional TFETs, the unique single current path phenomenon of PNN TFETs was found for the first time. The influence of various process and device parameters on ESD performance of PNN TFET is also given to obtain a better ESD design window.

Basic Concept of Electrostatic Discharge (ESD) Protection TFET
TFET is essentially a reverse biased gated p-i-n diode [22][23][24]. Under negative ESD stress, ESD current is injected into the source terminal of TFET with drain terminal grounded. TFET will operate in a positive diode conduction mode and has a high current discharge capability, as shown in Figure 1a [25,26]. Under the positive ESD stress, ESD current is injected into the drain terminal of TFET with the source terminal grounded. TFET will operate in avalanche breakdown mode to discharge the ESD current, as illustrated in Figure 1b. Since avalanche breakdown requires a relatively high electric field, the conduction voltage of TFET under positive ESD stress is high, making it unacceptable in advanced nanoscale technologies. Thus, the research on TFET under ESD stress mainly focuses on the positive discharge mode.  Figure 2a,b are schematic diagrams of SiGe S/D PNN TFET and Conventional TFET, both of which have SiGe Source/Drain. In order to facilitate heat dissipation, the device size is not set to a very small value [27,28]. The high K material of the gate medium is HfO2. The default device parameters are: gate oxide thickness = 4 nm, gate length LG = 100 nm, source, drain length = 100 nm, junction depth Xi = 10 nm, thickness= 1 μm, p+ source doping, p-channel doping and n+ doping of Conventional TFET are NS = 1 × 10 20 cm −3 , ND = 5 × 10 19 cm −3 , and NC = 1 × 10 17 cm −3 ; p+ source doping of SiGe S/D PNN is NS = 1 × 10 20 cm −3 , and the n+ drain and n+ channel doping are defined as ND, both of which are 5 × 10 19 cm −3 . In order to avoid possible high defect density at the SiGe/Si interface, we set the default Ge mole fraction to 0.5. Transmission line pulse(TLP) is a kind of non-destructive equivalent ESD impact test, which can accurately obtain the ESD characteristic parameters of the device. The drain terminal of the TFET was stressed with TLP pulses while keeping the gate and the source terminals grounded. The rise time and the pulse width were set as 10 ns and 100 ns. The voltage samples were obtained by averaging the transient data in the range of 60 ns to 90 ns [16].

Device Structure and Simulation Setup
All simulations of the above device structures are performed using Synopsys Sentaurus simulation software. In order to increase the accuracy of the simulation, the dynamic non-local path was used to analyze the band tunneling phenomenon of TFET devices under ESD impact. The probability of tunneling(TBTBT) depends on an electric field across the tunnel junction (E), carrier effective mass (m), the source band gap (Eg), as depicted in Equation (1).
The thermodynamic model was used to calculate the lattice temperature, and the Van overstraeten-de Man model was used to calculate the avalanche occurrence. In order to get more accurate simulation results, the bandgap narrowing model, the carrier mobility model, the high-field saturation model, and the doping associated carrier composite model were also used. The ESD characteristics of the device were evaluated by using the TLP simulation method. In the case of gate and source grounding, TLP current with 10 ns rise time and 100 ns pulse width was added to drain. The voltage samples are obtained by averaging the transient data in the range of 60 ns to 90 ns.

Simulation Results and Discussion
In order to verify the performance of PNN TFET, failure currents, trigger voltages, and electric fields of PNN TFET and Conventional TFET need to be simulated in this work. The source region tunneling junction of the Conventional TFET device was composed of a p+ SiGe doped source region and a low-doped p-Si substrate. Compared to PNN TFET, due to the wide tunnel junction and high trigger voltage, the failure current of Conventional TFET tends to be smaller. When the size of TFET device is reduced, the excessive trigger voltage may lead to the premature breakdown of the gate oxide layer, while the small failure current may lead to the premature damage of the device. In order to obtain better ESD design window, it is necessary to reduce the trigger voltage and increase the failure current. The TLP I-V curves of PNN TFET and Conventional TFET are shown in Figure 3. Under the same pulse current, the trigger voltage of PNN TFET was 1.3 V, and failure current was 3.0 mA/μm. Compared with Conventional TFET, the trigger voltage reduced by 66.3%, and the failure current increased by 20%. These key parameters will make it easier for TFET to adapt to modern ESD design Windows and improve the ESD performance of TFET devices.  Figure 4 shows the distribution of the tunneling probability of PNN TFET and Conventional TFET under 1 mA current pulse. The difference is that PNN TFET tunneling mainly occurred at the source/channel junction, while Conventional TFET mainly occurred at the drain/channel junction. According to the simulation results, near the channel surface (within 2 nm), both PNN TFET and Conventional TFET had high band-to-bandtunneling (BTBT) Gen Rate (GBTBT)( > 1 × 10 30 cm −3 s −1 ). However, from the middle of the channel (5 nm), the tunneling probability of the Conventional TFET decreased significantly while that of the PNN TFET remained at 1 × 10 30 cm −3 s −1 . Therefore, the tunneling probability distribution of PNN TFET is more uniform, and the tunneling area is effectively improved.  In order to study the improvement of the tunneling uniformity of the PNN TFET band, the electric field intensity distribution in the junction of drain and channel was extracted. When the band curvature was greater than the band gap of SiGe material; obvious band tunneling occurs. In other words, when the band bend exceeded the band gap of SiGe, the tunneling path obtained a large GBTBT. Because the band bending from drain to channel depends on the electric field. For SiGe PNN TFET, obvious tunneling occurred when the electric field at the tunneling junction was higher than 3.7 MV/cm −1 . As shown in Figure 5, the strength of the PNN TFET's entire electric field under 1 mA/μm TLP current was higher than 3.7 MV/cm −1 , indicating that the tunneling area was greatly increased. For PNN TFET, the doping concentration in the N+ channel region was 5 × 10 19 cm −3 ; for Conventional TFET, the channel was close to the eigenvalue, and the doping concentration was 1 × 10 17 cm −3 . When a TLP current pulse was applied, electrons accumulated in the channel. But the electron density in the middle and below of the channel was much lower than that on the channel surface. Since the channel region of PNN TFET was heavily doped, the electron density in and below the channel will be much higher than that of Conventional TFET when receiving the current pulse. When the TLP current increased, the double-current path of Conventional TFET was more obvious. The device could be observed to have two distinct current paths. The upper path was the hole current path, and the lower path was the electron current path. Different from the Conventional TFET's double-current path, the total current, electron current, and hole current of PNN TFET were all in one path; that is, there was only a single-current path, as shown in Figure 6. In the junction of channel/source, there existed a blocky current.
This phenomenon can be explained as follows: for the Conventional TFET with both gate and source grounded, the potential of drain level increases under the circumstance of ESD current injection. Figure 7 shows the electric potential contour of the SiGe S/D PNN TFET and Conventional TFET. The closely-spaced contour near the drain/channel interface indicates that the region has a high potential and is the first region where BTBT occurs, and BTBT generates a large number of hole electron pairs. The holes are swept to the oxide interface by a vertical electric field in Conventional TFET [18]. For PNN TFET, while the channel and the drain are n+ doping, the substrate is p-doping, it is equivalent to a reverse-biased PN(P-N+) junction, the electric field in the channel and the drain is basically the same. The difference of vertical electric field basically only exists at the junction of channel and source. This is the reason why the block current is generated here.

Optimization of SiGe S/D PNN TFET Device Parameters
Under an ESD event, the Joule heat is the main heat component in the device, and it can be expressed as in reference [29].
Where H is heat, J is current density, μ is mobility, and the subindices n and p are electrons and holes, respectively. The joule heat of the hole is higher than the joule heat of the electron because the hole generated by the impact moves from the drain interface to the source through the channel region, and the electron is collected by the drain and channel without any movement. These, in turn, cause a large amount of hole Joule heat generated at the interface regions, as shown in Figure 8. The hole mobility in SiGe S/D TFET is higher than that in Si TFET because the hole Joule heat is the dominant heat source and hole mobility in SiGe is higher than that in Si [30]. As shown in Figure 9, The hole mobility in the SiGe S/D PNN TFET is higher than that in the conventional TFET.    In SiGe PNN TFET, as shown in Figure 11, it can be seen that the increase of the mole fraction of Ge led to a decrease in the triggering voltage. It resulted in a slight reduction in the failure current. This trend can be easily understood from the preceding discussion. Because the hole Joule heat is the dominant heat source and hole mobility in SiGe is higher than that in Si, so the increase of the mole fraction of Ge will lead to the decrease of the triggering voltage.

Conclusions
In this paper, a new SiGe Source/Drain PNN field effect transistor was presented, and its ESD characteristics were studied by TCAD simulation. Compared with the Conventional TFET, the trigger voltage of the SiGe Source/Drain PNN TFET is reduced because the tunneling region has a high BTBT probability and a higher impact ionization coefficient. The failure current of the SiGe Source/Drain PNN TFET is also increased by the lower trigger voltage and a smaller Joule heat resulting from higher hole mobility in SiGe. The unique single current path phenomenon in PNN TFET has been discovered in this work. The results have demonstrated that the single current path is formed by the same electric field in the channel and the drain. SiGe S/D PNN TFET device parameters are optimized in this work; an increase of drain doping level and mole fraction of Ge can improve ESD performance. This enhanced ESD performance will be beneficial for constructing robust TFET-based ESD protection devices in the future.