Bridgeless Boost Converter with an Interleaving Manner for PFC Applications

: Power quality is a critical issue in power systems. This paper proposes a bridgeless boost converter to increase the power factor of power systems using a utility line source for raising power quality. To reduce input and output current ripple, an interleaving manner is adopted in the proposed power system. When the interleaving bridgeless boost converter is used to implement power factor correction (PFC), it needs two bridgeless boost converters to process power during one switching cycle. In order to simplify the proposed bridgeless boost converter, two sets of switches in the conventional bridgeless boost one are integrated to reduce component counts. With this approach, the proposed bridgeless boost converter uses four switches to implement PFC features. Therefore, the proposed boost converter can increase conversion efﬁciency and decrease component counts, resulting in a higher conversion efﬁciency, lower cost and more simplicity for driving circuits. Finally, a prototype with a universal input voltage source (AC 90 V~265 V) under an output voltage of 400 V and a maximum output power of 1 kW has been implemented to verify the feasibility of the proposed bridgeless boost converter.


Introduction
The Internet of Things (IoT) is now widely applied to industrial, commercial and residential situations. Many sensors are adopted to construct the IoT. When a power supply generates a high-frequency noise, it will cause an abnormal signal of the sensor, leading to an error for IoT operations. Therefore, it needs a precision power supply and good power quality to supply a precision voltage level to control the system and avoid noise that affects its control functions. In addition, the power supply for IoT applications is required to have lighter, thinner, shorter and smaller features. As a result, a switching-mode converter is widely applied to these applications [1][2][3][4][5][6][7][8][9][10][11]. When a switching-mode converter adopts a utility line source as its power source, it will generate a seriously harmonic current pollution in the line source. In order to protect the line source from harmonic current pollution, a power factor corrector (PFC) is used in AC/DC power systems. It has to meet the various international power quality standards, such as International Electro-technical Commission (IEC) 61000-3-2 [12]. Thus, when an AC/DC converter uses PFC techniques to increase the power factor (PF), its input voltage can be made to be completely in phase with the input current one, implying an approximately unity power factor.
When an AC/DC power supply adopts active PFC to increase the PF, a boost converter is the most popular topology among the AC/DC converters. Since a boost converter is combined with a diode bridge rectifier to form the active PFC, losses from the diode bridge rectifier are significant, as shown in Figure 1. In particular, when the line source is at a lower input voltage and high output power, the conversion efficiency of the AC/DC converteris reduced. To improve the efficiency of the diode bridge rectifier, a bridgeless boost converter is adopted to reduce losses of diodes, as shown in Figure 2. Due to larger common-mode (CM) noise interference in the bridgeless boost converter shown in Figure 2, two diodes    When a switching-mode converter is used in high-power applications, it will induce larger current ripples in input and output ports, resulting in a requirement for a larger passive filter. In order to reduce the passive component size, increase the output power level and decrease the current ripple, an interleaving circuit is usually adopted as an alternative solution in high-power applications. Many interleaving converters have been proposed, such as in [13][14][15][16][17][18][19]. When the AC/DC converter uses the conventional bridgeless boost converter for PFC applications, it can adopt its interleaving circuit to increase power processing capability, as shown in Figure 5. From Figure 5, it can be seen that the interleaving bridgeless boost converter can achieve a higher power factor, smaller current ripple and higher conversion efficiency. It is suitable for PFC applications. When PFC adopts the interleaving bridgeless boost converter illustrated in Figure 5, it needs a more complex driving circuit. In order to further simplify the circuit, switches M 1~M4 shown in Figure 5 can be merged and replaced by switches M 1 and M 2 , illustrated in Figure 6. According to performances of circuits shown in Figures 2-6, each PFC circuit can be used in different situations. Table 1 shows the performance comparisons among different PFCs with power flow through component paths. When power flows through each component, it will generate power loss in the component, resulting in lower conversion efficiency. The circuits, shown in Figures 2-4 are the single-phase topology. Their power level processing capability belongs in low-or medium-power applications. The circuits in Figures 5 and 6 are the two-phase topology. Their power level processing capacities are suitable for medium-or high-power applications. In Table 1, it can be seen that the converter in Figure 4 possesses the highest conversion efficiency, while the one in Figure 3 has lower conversion efficiency. When the converter topology adopts a two-phase manner, the proposed boost converter can reduce component counts, resulting in lower conversion efficiency compared with the modified bridgeless boost converter with low CM noise shown in Figure 5. Their conversion efficiency difference is about 1%. Therefore, the proposed boost converter possesses superiority in PFC applications. In Figure 6, the proposed interleaving bridgeless boost converter can implement PFC functions and reduce current ripple and increase conversion efficiency and power processing capability.
inductor in the released energy state The negative half period inductor in the stored energy state inductor in the released energy state Power level processing capability small small small large large Input and output current ripple large large large small small Efficiency higher low highest highest higher Figure 5 shows a schematic diagram of the conventional interleaving bridgeless boost converter for PFC applications. Since the utility line source is divided into the positive half period and the negative half one, its power flow is different during each half period operation. When the conventional bridgeless boost converter is operated in the positive half period, switch Ms 2 is turned on, and switches M 1 and M 2 are operated in an interleaving mode. If switches M 1 and M 2 are separately turned on, inductors L 1 and L 2 , respectively, operate in the stored energy state. When switches M 1 and M 2 are separately operated in the turned-off state, inductors L 1 and L 2 , respectively, operate in the released energy state through diodes D 1 and D 2 . When the conventional bridgeless boost converter is operated in the negative half period, switch M s1 is turned on, and switches M 3 and M 4 operate in the interleaving mode. Inductors L 3 and L 4 can be worked in the stored and released energy states, respectively, through switches M 3 and M 4 or diodes D 3 and D 4 . According to the operations mentioned above, the conventional bridgeless boost converter can achieve PFC function.

Derivation of the Proposed Converter
In order to simplify the circuit shown in Figure 5, switches M 2 and M 4 are replaced by one switch, M 2 , and two diodes, D 6 and D 8 , as shown in Figure 6. The switch M 2 plays a switching role and is the same as that of switches M 2 and M 4 shown in Figure 5. Diodes D 6 and D 8 are used to avoid a reverse current from inductors L 2 and L 4 , respectively. Moreover, switches M 1 and M 3 can be replaced by switch M 1 and diodes D 5 and D 7 , as shown in Figure 6. In Figure 6, it can be seen that switch M 1 can be, respectively, operated in the positive half and the negative half periods to replace switches M 1 and M 3 , shown in Figure 5, when inductors L 1 and L 3 are worked in the stored energy state. Diodes D 5 and D 7 are adopted to avoid the reverse currents of inductors L 1 and L 3 , respectively. In addition, diodes D 1 and D 3 are, respectively, operated in the released energy states of inductors L 1 and L 3 when switch M 1 is turned off.

Operational Principle of the Proposed Boost Converter
The proposed interleaving bridgeless boost converter is operated in a PFC manner. Its conceptual waveform is plotted in Figure 7 during a complete line period. When the proposed converter is operated during a complete line period, it can be divided into two operational periods: the positive and negative half periods. In the positive half period, switch M 4 is turned on and switch M 3 is turned off. In addition, switches M 1 and M 2 are operated in the interleaving manner. That is, their operation is out of phase by 180 • for each switch. When the proposed converter operates in the negative half period, switch M 3 is turned on and M 4 is turned off. In the operational interval, switches M 1 and M 2 also operate in the interleaving manner. Since the operational principles of the proposed converter in the positive half period are the same as those in the negative half period, except that switch M 4 turned on in the positive half periods changed to M 3 turned on in the negative one, its operational principles are only described in this paper for the positive half period situation.  When the proposed interleaving boost converter is operated in the positive half period, input voltage varies from 0 V to a maximum value and then from the maximum value to 0 V with a sine wave variation. The duty ratio of the switch in the proposed converter slowly decreases its value, which depends on the level of increase in the input voltage. When the input voltage is high enough, the duty ratio is less than 0.5 and inductor currents i L1 and i L2 operate in continuous conduction mode (CCM). Its conceptual waveform is shown in Figure 7. According to the operational principle of the proposed converter, its operational mode is divided into four modes. The equivalent circuit of each operational mode is illustrated in Figure 8. Each operational mode of the proposed converter is briefly described in the following section.
Mode 1 (Figure 8a: t 0 ≤ t < t 1 ): Before t 0 , inductors L 1 and L 2 simultaneously work in the released energy states. Diodes D 1 and D 2 are forwardly biased. Currents i L1 and i L2 linearly decrease through D 1 , load R 0 and switch M 4 , and D 3 , load R 0 and switch M 4 , respectively. When t = t 0 , switch M 1 is turned on and M 4 is kept in a turned-on condition. Diode D 1 is reversely biased and D 2 is forwardly biased, and inductor L 1 enters the stored energy state. In addition, inductor L 2 works in the released energy state through diode D 3 . During this interval, inductor current i L1 linearly increases and current i L2 linearly decreases.
Mode 2 ( Figure 8b: t 1 ≤ t < t 2 ): At t 1 , switch M 1 is turned off and M 2 is still in a turned-off state. Inductors L 1 and L 3 are in the released energy state through diodes D 1 , D 3 and switch M 4 , simultaneously. In this mode, currents i L1 and i L2 linearly decrease. Mode 3 ( Figure 8c: t 2 ≤ t < t 3 ): When t = t 2 , switch M 2 is turned on and M 4 is kept in the turned-on state. Inductor L 2 operates in the stored energy state through diode D 4 and switch M 4 . Therefore, inductor current i L1 linearly decreases and i L2 linearly increases.
Mode 4 ( Figure 8d: t 3 ≤ t < t 4 ): At t = t 3 , switch M 2 is turned off. Inductor L 2 changes the operation state from the stored energy state to the released energy state. Diodes D 1 and D 3 help inductors L 1 and L 2 turn to the released energy state, respectively. During this interval, currents i L1 and i L2 linearly decrease. When t = t 4 , switch M 1 is turned on again. The new switching cycle starts.

Design of the Proposed Interleaving Bridgeless Boost Converter
The proposed interleaving bridgeless boost converter adopts the interleaving circuit to reduce input and output ripple currents. Its inductor ripple cancellation k(D) is derived in this paper. For the design of the proposed converter, the determination of duty ratio D, inductors L 1~L4 and output capacitor C 0 is important. In addition, the selection of components D 1~D8 , M 1~M4 is also described in this paper. Their design is briefly derived as follows.
(a) Ripple current cancellation K(D) The proposed interleaving boost converter can reduce the ripple currents of inductors L 1~L4 . The ratio K(D) of input ripple current ∆i in to individual inductor ripple current ∆i L1 in the interleaving boost converter is plotted in Figure 9. When duty ratio D is equal to or less than 0.5, K(D) can determined by If D is greater than 0.5, K(D) can be derived by According to (1) and (2) The input voltage range of the proposed boost converter is from AC 90 V to AC 265 V. When the input voltage is at low line, the duty ratio can be obtained by where V in-min represents AC 90 V. If the input voltage is at high line, duty ratio D PHL can determined as where V in-max is equal to AC 265 V. Duty ratio D can be varied from D PHL to D PLL .
(c) Inductors L 1~L4 Since the maximum inductor current i L(max) is at low line of the input voltage, inductors L 1~L4 can be determined for control within a desired range. In order to determine the values of inductors L 1~L4 , the ripple current ∆i L must be specified. When the proposed boost converter is operated at low line, ∆i L(max) can be obtained by where 0.3 means that the maximum input ripple current was set to 30% of the peak input current at low line, η represents the conversion efficiency under a full-load condition and K(D PLL ) is the ratio of input current to inductor ripple current at the peak of low line operation. When ∆i L(max) is determined, inductor L 1 ( = L 2 = L 3 = L 4 ) can be obtained as where T s is the switching period.

(d) Output capacitor C o
When the proposed boost converter is applied to PFC applications, output capacitor C o must sustain the output voltage V o at a desired value during loss of the line source under one line cycle. In general, when the line source faulty is during a line cycle, output voltage V o can be kept at and be greater than 0.75V o . According to the above requirement, output capacitor C o can be derived as where f l is the line frequency of the line source, and when output capacitor C o is determined, output ripple voltage ∆V o can be expressed by where ω l is equal to 2πf l .
(e) Selection of switches and diodes Figure 6 shows the schematic diagram of the proposed interleaving bridgeless boost converter. In order to determine the voltage and current ratings of components, the input voltage is in different situations. When the input voltage is in a high line situation, the voltage ratings of components in the proposed converter can be determined. The maximum voltage stresses of switches M 1 and M 2 can be determined by In addition, that of diodes D 1~D8 can be expressed by In a high line situation, the voltage stresses of switches M 3 and M 4 can be obtained: as where V in(max) represents the input voltage level in a high line situation. When the input voltage is in a low line condition, rms currents I M1(rms) (=I M2(rms) ) of switch M 1 can be derived as where P o is the maximum output power, V in-min represents the rms value of input line voltage in a low line condition, η is the conversion efficiency of the proposed converter and V o is the output voltage. Switch rms currents I M3(rms) (= I M4(rms) ) can be expressed by Additionally, the diode rms current i D1(rms) ( = i D2(rms) = i D3(rms) = i D4(rms) ) is derived as The diode rms current i D5(rms) ( = i D6(rms) = i D7(rms) = i D8(rms) ) is derived by Furthermore, the output capacitor rms current I Co(rms) is shown by

Experimental Results
The proposed interleaving bridgeless boost converter is shown in Figure 6. In order to verify the performance of the proposed converter, a prototype with the following specifications was implemented.    The proposed interleaving bridgeless boost converter is proposed to achieve a higher PF and a lower input ripple current. Figure 10 shows the measured currents i L1 , i L2 and i in waveforms of the proposed interleaving bridgeless converter under AC 90 V of input voltage. Figure 10a shows those waveforms with 10% of the full-load condition, while Figure 10b illustrates those waveforms with 100% of the full-load condition. In Figure 10, it can be seen that the proposed converter operates in discontinuous conduction mode (DCM) under 10% of the full-load condition, and operates in CCM under 100% of the full-load condition. Furthermore, the input ripple current can be reduced from a light load to a heavy load. Measured output voltage V o and current I o waveforms of step-load changes between 10% and 100% of the full-load condition with a duty ratio of 50% and a repetitive period of 1s are illustrated in Figure 11. Figure 11a depicts those waveforms under AC 220 V of the input voltage. From Figure 11, output voltage V o is regulated within a desired voltage range. Its value is limited within 1%.
The conversion efficiency of the proposed boost converter from a light load to a heavy load under the different input voltage is plotted in Figure 12. In Figure 12, when the input voltage is at a higher level, its conversion efficiency is higher than that of a lower input voltage from a light load to a heavy load. The maximum conversion efficiency is 96% under 80% of the full-load condition at AC 230 V of input voltage. From Figure 12, it can be seen that the conversion efficiency of the proposed boost converter is higher than 88% under different input voltages. Since the input voltage V in varies with the sine wave, it is difficult to evaluate the power loss of each component with an accurate method. In general, power loss analysis of PFC is usually adopted by simulation tools to obtain approximate power losses for the converter. Table 3 lists the parameters of selection components in the proposed boost converter. According to Equations (12)- (16), the rms currents of switches and diodes can be obtained from a light load to a heavy load at input voltage V in of AC 110 V. Table 4 shows the power loss of each semiconductor. In Table 4, power losses of switches include switching loss and conduction loss. Figure 13 shows the conceptual waveforms of switching loss during switch turn-on and turn-off transitions. In addition, the conduction loss of switches can be determined by I 2 M(rms) R ds(on) , where I M(rms) is the average rms current of a switch and R ds(on) expresses the resistance of a switch in the conduction state. Power loss analysis of diodes is evaluated by I D(rms) V F , where I D(rms) is the average rms current of a diode and V F is its forward drop voltage. Switches M 3 and M 4 are turned on or turned off at the zero-crossing point. Therefore, their switching losses are equal to 0. Their power losses only consider conduction loss.
higher PF and a lower input ripple current. Figure 10 shows the measured currents iL1, iL2 and iin waveforms of the proposed interleaving bridgeless converter under AC 90 V of input voltage. Figure 10a shows those waveforms with 10% of the full-load condition, while Figure 10b illustrates those waveforms with 100% of the full-load condition. In Figure 10, it can be seen that the proposed converter operates in discontinuous conduction mode (DCM) under 10% of the full-load condition, and operates in CCM under 100% of the full-load condition. Furthermore, the input ripple current can be reduced from a light load to a heavy load. Measured output voltage Vo and current Io waveforms of step-load changes between 10% and 100% of the full-load condition with a duty ratio of 50% and a repetitive period of 1s are illustrated in Figure 11. Figure 11a depicts those waveforms under AC 220 V of the input voltage. From Figure 11, output voltage Vo is regulated within a desired voltage range. Its value is limited within 1%. The conversion efficiency of the proposed boost converter from a light load to a heavy load under the different input voltage is plotted in Figure 12. In Figure 12, when the input voltage is at a higher level, its conversion efficiency is higher than that of a lower input voltage from a light load to a heavy load. The maximum conversion efficiency is 96% under 80% of the full-load condition at AC 230 V of input voltage. From Figure 12, it can be seen that the conversion efficiency of the proposed boost converter is higher than 88% under different input voltages. Since the input voltage Vin varies with the sine wave, it is difficult to evaluate the power loss of each component with an accurate method. In general, power loss analysis of PFC is usually adopted by simulation tools to obtain approximate power losses for the converter. Table 3 lists the parameters of       In the proposed boost converter, a major power loss is core loss P c and copper loss P cp in the inductors. Table 5 illustrates core loss P c and copper loss P cp of inductors L 1~L4 of the proposed boost converter. Since inductors L 1~L4 in the proposed boost converter are selected with super-MSS powder core manufactured by Arnold Magnetics LTD, its core loss curves are shown in Figure 14. The core loss must first obtain maximum flux density B m , and then the core loss coefficient is determined, which is specified by Figure 14. Moreover, copper loss can be determined by i 2 L(rms) R dc , in which R dc is the resistance of wire gauge. Table 6 illustrates the power loss analysis of the proposed boost converter under input voltage V in of AC110V. According to Table 6, it can be seen that when output power P o is less than 40% of the maximum output power P o(max) , the calculation efficiency η c is higher than practical efficiency η p . The reason for is that the stray losses do not include in the total power losses of the proposed converter, resulting in a lower practical efficiency. When output power Po is greater than 40% of the full-load condition, the proposed converter operates in CCM. Its practical peak currents of switches and inductors are less than those with the calculation method. Therefore, core losses of inductors and switching losses of switches with the calculation method are greater than the practical losses, meaning that the calculation efficiency η c is less than that of the practical efficiency η p . Their difference is 2-3%. The calculation efficiency can be regarded as the reference efficiency.     Figure 15 shows plots of the harmonic current of the proposed boost converter from a light load to a heavy load at different input voltages. From Figure 15, it can be seen that the harmonic current of the proposed converter from a light load to a heavy load under different input voltages can meet the requirements of IEC-6100-3-2 class A. In addition, plots of the power factor of the proposed converter from a light load to a heavy load under different input voltages are illustrated in Figure 16. With different input voltages, the power factor of the proposed converter from a light load to a heavy load is higher than 0.8. As mentioned above, the proposed interleaving bridgeless boost converter can implement a lower input ripple current, a higher conversion efficiency and a higher power factor. It is suitable for PFC applications.  Figure 15 shows plots of the harmonic current of the proposed boost converter from a light load to a heavy load at different input voltages. From Figure 15, it can be seen that the harmonic current of the proposed converter from a light load to a heavy load under different input voltages can meet the requirements of IEC-6100-3-2 class A. In addition, plots of the power factor of the proposed converter from a light load to a heavy load under different input voltages are illustrated in Figure 16. With different input voltages, the power factor of the proposed converter from a light load to a heavy load is higher than 0.8. As mentioned above, the proposed interleaving bridgeless boost converter can implement a lower input ripple current, a higher conversion efficiency and a higher power factor. It is suitable for PFC applications.

Conclusions
The proposed interleaving bridgeless boost converter is presented for PFC applications. The proposed converter adopts interleaving and bridgeless circuits to increase the power process capability and increase conversion efficiency, simultaneously. In this paper, the operational principle and design of the proposed converter have been described in detail. According to the experimental results of the proposed converter, input ripple current can be reduced and power factor can be increased. Furthermore, the proposed converter can also achieve a lower harmonic current and a higher conversion efficiency. Its harmonic current from a light load to a heavy load under different input voltages can meet the requirements of IEC-6100-3-2 class A. The maximum conversion efficiency is about 96.4% under 80% of the full-load condition at AC 265 V of input voltage. In addition, the power factor from a light load to a heavy load under different input voltages is higher than 0.8. From the experimental results of the proposed interleaving bridgeless boost converter mentioned above, the proposed converter was

Conclusions
The proposed interleaving bridgeless boost converter is presented for PFC applications. The proposed converter adopts interleaving and bridgeless circuits to increase the power process capability and increase conversion efficiency, simultaneously. In this paper, the operational principle and design of the proposed converter have been described in detail. According to the experimental results of the proposed converter, input ripple current can be reduced and power factor can be increased. Furthermore, the proposed converter can also achieve a lower harmonic current and a higher conversion efficiency. Its harmonic current from a light load to a heavy load under different input voltages can meet the requirements of IEC-6100-3-2 class A. The maximum conversion efficiency is about 96.4% under 80% of the full-load condition at AC 265 V of input voltage. In addition, the power factor from a light load to a heavy load under different input voltages is higher than 0.8. From the experimental results of the proposed interleaving bridgeless boost converter mentioned above, the proposed converter was implemented to verify its feasibility. It is suitable for PFC applications.

Conflicts of Interest:
The authors declare no conflict of interest.