Improvement of Small Signal Equivalent Simulations for Power and Efficiency Matching of GaN HEMTs

In high-frequency power-amplifier design, it is common practice to approach the design of reactive matching networks using linear simulators and targeting a reflection loss limit (referenced to the target impedance). It is well known that this is only a first-pass design technique, since output power or efficiency contours do not correspond to mismatch circles. This paper presents a method to improve the accuracy of this approach in the case of matching network design for power amplifiers based on gallium nitride (GaN) technology. Equivalent mismatch circles, which lay within the power or efficiency contours targeted by the design, are analytically obtained thanks to geometrical considerations. A summary table providing the parameters to use for typical contours is provided. The technique is demonstrated on two examples of power-amplifier design on the 6–12 GHz band using the non-linear large-signal model of a GaN High Electron Mobility Transistor (HEMT).


Introduction
High-frequency power amplifiers (PAs) are crucial components in wireless transmitters. To meet the signal output power requirements, they normally consume most of the energy in the system. Therefore, their design normally targets high efficiency to minimize not only consumption, but also power dissipation and, consequently, lower the requirements on cooling [1]. As a result, improving the PA efficiency can lead to significant savings in terms of direct and operation costs of a wireless system. However, efficiency improvement is often in contrast with other equally important design requirements, such as output power and bandwidth. Using GaN HEMTs can help the design of PAs in this respect [2]. In fact, among the transistor technologies able to operate at high frequency, they offer the best power density, meaning that higher power can be achieved with simpler power combining networks, making it easier to achieve broadband designs with low losses and, consequently, high efficiency.
It is common practice among PA designers to identify the target impedance Z opt to be presented at the device drain of the transistor by either measurement of the device or simulations of a non-linear model of the device. Then, to initiate the design of the matching networks by using a linear simulator that targets zero reflection when normalizing the simulating impedance to Z opt . This is done because linear simulation is faster and allows the optimization of more parameters with a reasonable simulation time [3]. This approach is formally correct in a single-frequency design. However, when designing for a frequency band, it is normally impossible to achieve a perfect match at all frequencies, therefore contours are used instead of single-point impedance targets [4]. The problem is that it is not straightforward to set a linear simulator to target a contour that resembles the shape of power or efficiency contours of real transistors. Therefore, most designers set as target a maximum reflection loss Γ MAX , effectively a mismatch circle, whose relationship with the power of efficiency contours of the device is not immediate. Then, the matching network is readjusted using simulations with the large-signal model. This paper proposes, for GaN HEMTs, a simple way of modifying the linear simulation settings by providing the relation between the power and efficiency contours and the mismatch circle, so that a linear simulator can be used to target immediately a load within the power and efficiency contours. The motivation of the work is to provide PA designers with a simple, yet effective, tool to improve the design of matching networks while still using the technique with which they are most familiar.
The power and efficiency contours are estimated by using the simplified method proposed in [5], with demonstrated effectiveness in modeling different GaN HFETs contours. This enables the analysis in a closed form, because the approximated contours in [5] are expressed in terms of circles and ellipses, therefore with clearly identifiable geometrical properties. On the other hand, the method proposed in this paper does not require the repetition of the modeling procedure proposed in [5], and can be extended to any target contour for which we can identify key geometrical properties on the Smith Chart. Two examples of design using a GaN HFET die large-signal model are used to prove the validity of the approach. The validation is done at simulation level, by checking that the networks designed using the simplified method led to the expected results in terms of large-signal performance when tested with the non-linear model.

Theoretical Analysis
PA designers, especially when using integrated or die level devices, tend to prefer operating at the intrinsic generator plane, where the optimum impedance targets for maximum output power or efficiency are real valued. This means including the reactive effects and parasitics in the linear simulation as a network that lies between the test port and the matching network. This is an approximation, since reactive intrinsic elements of the transistor are voltage-dependent and hence linearized. Such an approximation is acceptable for a first-pass design approach. To achieve high levels of accuracy, the non-linear capacitance elements must be embedded too [6].
At the intrinsic generator plane, the power contours of an ideal transistor were described by Cripps in [7] (Cripps contours) and showed very good agreement with measurements of gallium arsenide (GaAs) devices whose output IV characteristics presented a very sharp knee. GaN HEMTs present smoother output characteristics, making the Cripps contours less accurate. A recent paper [5] has proposed to use a parameter N to describe the sharpness of the IV knee profile, providing an effective method to predict both output power and efficiency contours of GaN HEMTs. Figure 1 shows an example of GaN HEMT output characteristics shown in terms of "fan-diagrams" [8] (Pulsed IV curves can also be used), with N-model profiles superimposed. The simulated fan diagram is obtained, at 100 MHz, with the non-linear model of the PB1001 GaN HEMT from ICONIC RF Ltd., Belfast, UK. The quiescent bias point is 28 V, 45 mA, and the dynamic load lines are obtained by loading the transistor with a tuned real load varying from 5 Ω to 130 Ω. By selecting the I MAX and V DD parameters from this plot, as well as the N that best fits the profile, the contours of Figure 2 can be obtained. Please note that they are represented on a Smith Chart normalized to R opt = 2V DD /I MAX , hence the need to identify these parameters. It is important to note that this parameter does not correspond to the effective optimum load, as already discussed in [5].
N values of 4, 6, and 8 have been found to fit most of the current GaN transistors IV profiles [5]. It is important to point out that pulsed or dynamic IV characteristics must be used to fit the N profile, because DC characteristics are not an accurate representation of the real response of the HEMT at high frequency. On the other hand, the variation between contours when moving from N = 4 to N = 8 is not very large. Consequently, the inaccuracy of the fitting of the N model over the IV curves has a relatively low impact on the effectiveness of the method.

Power and Efficiency Contours vs. Mismatch Circles
A simple simulation for designing the PA matching network can be set using a linear simulation of the cascade of device reactive effects and the matching network topology, terminated on the system impedance, typically 50 Ω (see Figure 3). An optimizer or manual tuner can be used to target a given maximum |S 11 | = Γ MAX which is referenced to the port 1 impedance Z u , normally set to R opt .
Elements to be optimised The Γ MAX circle is a mismatch circle that corresponds to a gain reduction contour of value G red (in a power transfer, conjugate matching sense) of that in turn means: So for example, a gain reduction contour of 0.5 dB means Γ MAX = 0.33. If we superimpose the 0.5 dB mismatch circle to the 0.5 dB output power contour for N = 8 as in Figure 4, it can be noted how the mismatch circle is not inscribed into the power contour.
It can be argued that the difference is quite small, and it can be accepted as a firstpass design approach. However, the same argument would not hold for the efficiency contours, which are clearly offset from the center and different from the mismatch circles. Therefore, it makes sense to obtain mismatch circles which fit better with the power and efficiency contours.

Equivalent Mismatch Circles
The idea proposed here is to correct the target Γ MAX and port impedance Z u in the linear simulation so that they provide a more accurate result when used in the PA design. To do so, these key assumptions and observations are made:

•
To guarantee the power level, the circle inscribed in the power contour ellipse is used as an approximation; this is a conservative choice which might lead to bandwidth reduction compared to a complete analysis. • The efficiency levels are already well approximated by circles. • If interpreted as mismatch circles, it is important to note that their geometrical center does not correspond to the normalized impedance of the corresponding mismatch circle, and their radius does not correspond to the mismatch level.
Therefore, to determine the reference impedance and mismatch of the equivalent mismatch circles some other observations are needed: • Being at the intrinsic generator plane, the power contour ellipses and the efficiency circles are symmetric with respect to the real-impedance axis of the Smith Chart. • This means that the intersections between the contours and the real axis are separated by the diameter of the circle. • Therefore, the intersections with the real axis correspond to points of maximum mismatch with opposite phase.
Graphically, this is explained in Figure 5. Figure 5. Graphical explanation of the method used to achieve the equivalent mismatch circles.
Mathematically, we can solve this by noting that the impedance of the intersection points, which we call Z 1 and Z 2 , cannot depend on the normalized impedance chosen. Therefore, both: and are verified. Also, we know the coordinates of the intersections on both Smith Charts: By substituting (3) and (4) in (5), we obtain: where z u is Z u /R OPT . It is now possible to solve the system to find Z u as a function of c and r by equating the two equations, which leads to: that can be rewritten as: Finally, Γ MAX can be solved using either of the equations of (6). For convenience, Tables 1 and 2 report the setting for equivalent mismatch simulation for contours of output power and efficiency, respectively. In particular, a few levels of power and efficiency reduction are reported, with three different cases of N (4, 6, and 8).

Use in Design: Case Study
These steps can be followed to adopt this method in PA design: 1.
Determine the R OPT = V DD /I DD of the device.

2.
Determine the best N that approximates the DCIV of the device.

3.
Decide the maximum power or efficiency reduction α to be targeted by the design. 4.
Use either Table 1 or Table 2 to find Z u and Γ MAX 5.
Design the matching network in a linear scattering simulations, by setting Z u as port impedance on the device side, and Γ MAX as target for design, including the reactive and parasitic elements. The design can be carried out using an optimizer, manual tuner, or even closed-form formulas where possible.
After these steps, depending on the availability of a large-signal model, the design can be refined using large-signal simulations.
If load-pull contours are already available, or if the device technology used does not obey the listed N approximation in the table, it is still possible to use this method. As long as the experimental or simulated contours can de-embedded to be placed on the real axis, it is then possible to use them to inscribe a circle. The center c and radius r of the circle can be identified and used to calculate Z u and Γ MAX by applying (8) and (6).

Design Example
The device used for the design example is the PB1001 from ICONIC RF Ltd., Belfast, UK, a GaN HEMT die optimized for X-band operation. For the design example, the target is the 6-12 GHz band. Fundamental load-pull simulations in class AB, at 28 V drain bias, show that the device can deliver up to 39.8 dBm at 5.5 dB compression on the optimum for power, and present an efficiency up to 70% at 5.5 dB compression on the optimum for efficiency. For our demonstration, the load-pull results are not used directly in the design, but just as a benchmark to check the results.
Two examples of matching network design are shown, the first targeting a 0.5 dB output power contour on the 6-12 GHz band (meaning higher than 39.3 dBm), and the second targeting a 0.5 dB efficiency contour on the same band (meaning an efficiency higher than 62.4%).
To obtain the values for N, I MAX and V DD we analyze the low-frequency fan diagram, which is reported in Figure 1. A value of N = 8 provides a good fitting for the IV curves. The maximum current is I MAX = 1.36 A, and the drain bias voltage is set at V DD = 28 V. This means that the value for R opt is 41 Ω. The reactive/parasitic effects can be estimated with a small signal simulation in pinch-off, and modeled quite accurately as a 0.5 pF shunt output capacitance followed by a series 80 pH inductance.

Example Targeting Power Contour
For the first design, Table 1 is used to find z u = 0.96 and Γ MAX = 0.17. ADS is used as a simulator, using the optimization shown in Figure 6. The port at which the mismatch is measured is set at the reference impedance Z u , while the optimization goal targets a maximum S 11 with value Γ MAX .
The matching network, which uses ideal elements for this demonstration, already considers the final realization. The series inductance can be implemented with the bond wires used to connect the die to the board. The short-circuit stub can be used to provide the bias supply, while the series capacitance serves as DC-block. The values shown in Figure 6 lead to the result reported in Figure 7, where the simulated S 11 is within the 0.17 circle on the whole band. Figure 8 shows the output power vs. frequency obtained with a large-signal simulation of the PA using the designed matching network, at 5.5 dB compression. The output power is always above 39.3 dBm in the 6-12 GHz band, as expected from targeting the 0.5 dB output power contour. It can be noted how, at some frequencies, the output power exceeds the optimum simulated with load-pull. However, the load-pull was fundamental only, so the higher output power at same compression can be ascribed to a more favorable harmonic loading.

Example Targeting Efficiency Contour
In this case, Table 2 is used to find z u = 1.6 and Γ MAX = 0.3. The ADS simulation with optimization and the obtained values is shown in Figure 9. The same topology of the previous example is used, but the values are different. The reflection coefficient lying in the 0.3 circle is shown in Figure 10, while the largesignal PA simulation with this matching network is reported in Figure 11. The efficiency at 5.5 dB compression is shown vs. frequency, and results always higher than 62.4% as expected when targeting the 0.5 dB efficiency contour. Also, in this case, the efficiency is higher than expected from load-pull, and again it can be ascribed to different harmonic terminations.

Discussion
The performance simulated using the large-signal model shows that the proposed method, relying on the linear simulator only for matching network design, is effective in guaranteeing a minimum in-band performance, related to the load laying within the contours. On the other hand, the method proposed is a first-order approximation. Therefore, an increase or decrease of performance due to detrimental or favorable harmonic terminations cannot be predicted. This can be seen as the main limitation of the proposed approach. In fact, it is not suggested to use this method to substitute simulations with a full non-linear model, but as a way of initiating the design within a linear simulation environment, for example in the phase of defining the matching network topology. Also, if information is provided on detrimental harmonic loads, the linear simulation can also include a target of avoiding these loads. This will still maintain a simulation environment that is faster than initiating the design in the harmonic balance simulator with the non-linear model.
Funding: This research received no external funding. Data Availability Statement: All data used is reported in the paper.