Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).


Introduction
Buffer-based analogue filters are in fact unity-gain amplifiers (i.e., buffers, followers) characterized by a bandwidth that is limited to the required frequency. For example, a simple two-stage Miller operational amplifier can be converted to a filter when it is configured as a unity-gain amplifier by closing a negative feedback loop. In this case, the limited bandwidth is due to Miller compensation, which results in a low-pass transmittance with one dominant pole, i.e., a first-order low-pass filter. Synthesis of a second-order response is also possible, however, only for certain classes of buffers-for instance a few variants of source followers including undamped [1,2], super [3], flipped [4][5][6], and ones that belong to other classes [7][8][9][10]. The advantage of the buffer-based filter realizations is a substantially lower number of transistors compared to traditional Operational Transconductance Amplifier Capacitor (OTA-C) structures [11][12][13][14] since a single transistor or a differential pair replaces the entire OTA. Consequently, the buffer-based filters are referred to as "transistorized" filters [6,15]. The reduced number of transistors decreases power and noise, whereas a simplified circuitry allows for an operation with supply voltage being as low as 0.3 V [9]. The buffer-based, transistorized filters are used for low power and low voltage applications in high frequency range [2][3][4][5]15], as well as for low-frequency, ultra-low power bioelectrical sensors [1,[6][7][8][9][10].
Realizations of buffer-based filters reported in the literature tend to be "individual" and down-to-top, as they start from a transistor-level circuit and end at Laplace transmittance. A typical design of a biquadratic structure is as follows. First, a potential candidate (i.e., a buffer) for filter realization is selected. Next, two capacitors are connected to internal nodes of a buffer's transistor-level circuit. Then, an equivalent OTA-C (Gm-C) schematic is extracted, and the Laplace transmittance is derived. Finally, if the transmittance is found to be desirable, the buffer circuit parameters (transistor transconductances, node capacitances, etc.) are selected to meet the required filter parameters. Assuming higher-order filter is needed, it is constructed as a cascade of biquadratic cells.
In this paper, a systematic approach to the synthesis of buffer-based filters is proposed. It originates from the traditional and well-developed top-to-down method that exploits RLC ladder to prototype an OTA-C (G m -C) filter structure [11,16]. In the final stage of the synthesis, the G m -C schematic is converted onto the transistor-level circuit, which permits synthesis of "transistorized" filters of any order. In addition to the proposed synthesis method, new transistor-level designs of low-frequency filters operating at 0.4 V supply voltage are also introduced. Two examples of fourth-order, low-pass, 100-Hz filters based on using both the conventional cascade method and the proposed ladder-based approach are presented. The introduced design framework reduces the total filter capacitance, which is an important advantage when integrating low-frequency filters on a chip.

Synthesis Method
The foundation of the proposed synthesis of buffer-based filters is based on a certain analogy between a unity-gain buffer and an OTA-C filter obtained from a single-resistance terminated ladder prototype. The details are provided below. Figure 1a shows a second-order, low-pass ladder filter terminated by a single resistor. At low frequencies, in the ladder passband, the inductor L 2P and the capacitor C 1P represent a short and an open circuit, respectively. Consequently, the output voltage V out is equal to the input V in , and the passband voltage gain is 1 V/V. Electronics 2021, 10, x FOR PEER REVIEW 2 of 13 nal nodes of a buffer's transistor-level circuit. Then, an equivalent OTA-C (Gm-C) schematic is extracted, and the Laplace transmittance is derived. Finally, if the transmittance is found to be desirable, the buffer circuit parameters (transistor transconductances, node capacitances, etc.) are selected to meet the required filter parameters. Assuming higherorder filter is needed, it is constructed as a cascade of biquadratic cells.

The Analogy
In this paper, a systematic approach to the synthesis of buffer-based filters is proposed. It originates from the traditional and well-developed top-to-down method that exploits RLC ladder to prototype an OTA-C (Gm-C) filter structure [11,16]. In the final stage of the synthesis, the Gm-C schematic is converted onto the transistor-level circuit, which permits synthesis of "transistorized" filters of any order. In addition to the proposed synthesis method, new transistor-level designs of low-frequency filters operating at 0.4 V supply voltage are also introduced. Two examples of fourth-order, low-pass, 100-Hz filters based on using both the conventional cascade method and the proposed ladder-based approach are presented. The introduced design framework reduces the total filter capacitance, which is an important advantage when integrating low-frequency filters on a chip.

Synthesis Method
The foundation of the proposed synthesis of buffer-based filters is based on a certain analogy between a unity-gain buffer and an OTA-C filter obtained from a single-resistance terminated ladder prototype. The details are provided below. Figure 1a shows a second-order, low-pass ladder filter terminated by a single resistor. At low frequencies, in the ladder passband, the inductor L2P and the capacitor C1P represent a short and an open circuit, respectively. Consequently, the output voltage Vout is equal to the input Vin, and the passband voltage gain is 1 V/V. Figure 1b presents the OTA-C filter obtained from the ladder of Figure 1a using the conventional state variable method (inductor currents and capacitor voltages are expressed by the corresponding nodal voltages in the OTA-C filter [16]). At low frequencies, the capacitors C1 and C2 can be treated as open circuits. OTAs are characterized by a high open-loop voltage gain (due to Gm >> Go, Go is the output conductance), thus the use of negative feedback loops results in virtual short circuits between positive (+) and negative (−) inputs of OTAs. Consequently, at low frequencies, the output voltage of the OTA-C filters is equal to the input voltage (Vout = Vin) resulting in a passband gain of 1 V/V. The input resistance of the structure of Figure 1b increases to infinity and the output resistance decreases to zero at low frequencies. Therefore, the considered structure is in fact a unitygain amplifier/buffer with bandwidth limited by the capacitances C1 and C2. The Laplace transfer function of the filters depicted in Figure 1a,b is   Figure 1a using the conventional state variable method (inductor currents and capacitor voltages are expressed by the corresponding nodal voltages in the OTA-C filter [16]). At low frequencies, the capacitors C 1 and C 2 can be treated as open circuits. OTAs are characterized by a high open-loop voltage gain (due to G m >> G o , G o is the output conductance), thus the use of negative feedback loops results in virtual short circuits between positive (+) and negative (−) inputs of OTAs. Consequently, at low frequencies, the output voltage of the OTA-C filters is equal to the input voltage (V out = V in ) resulting in a passband gain of 1 V/V. The input resistance of the structure of Figure 1b increases to infinity and the output resistance decreases to zero at low frequencies. Therefore, the considered structure is in fact a unitygain amplifier/buffer with bandwidth limited by the capacitances C 1 and C 2 . The Laplace transfer function of the filters depicted in Figure 1a,b is

The Analogy
where ω 0 = 2πf 0 is so-called a natural frequency, and Q denotes a quality factor. Note that the voltage amplifier characterized by the gain of 1 Ω/R (V/V) is usually not shown in schematic diagrams because R is typically 1 Ω. However, here this amplifier is used for analyses derived in subsequent sections of this work. OTA-C filters of higher orders also feature the analogy to unity-gain buffers when synthesized from RLC ladders terminated by single resistance. An example fourth-order filter is considered in Section 5.

Lossless and Lossy Integrator Circuits
Based on the example circuit of Figure 1b it can be observed that the OTA-C filter requires both lossless and lossy integrators. In general, a second-order filter requires at least one set of such components. In the filter of Figure 1b, the lossless circuit is represented using an open-loop OTA of G m2 , whereas the lossy circuit with the closed-loop OTA of G m1 . As mentioned earlier, a unity-gain buffer made of the Miller amplifier (Figure 2a, [17]) cannot be used for synthesis of a biquadratic filter, because its OTA-C equivalent schematic does not contain a lossy integrator. In fact, the circuit in Figure 2a features the second-order characteristic (1), but with Q increasing to infinity.
where ω0 = 2πf0 is so-called a natural frequency, and Q denotes a quality factor.
Note that the voltage amplifier characterized by the gain of 1 Ω/R (V/V) is usually not shown in schematic diagrams because R is typically 1 Ω. However, here this amplifier is used for analyses derived in subsequent sections of this work.
OTA-C filters of higher orders also feature the analogy to unity-gain buffers when synthesized from RLC ladders terminated by single resistance. An example fourth-order filter is considered in Section 5.

Lossless and Lossy Integrator Circuits
Based on the example circuit of Figure 1b it can be observed that the OTA-C filter requires both lossless and lossy integrators. In general, a second-order filter requires at least one set of such components. In the filter of Figure 1b, the lossless circuit is represented using an open-loop OTA of Gm2, whereas the lossy circuit with the closed-loop OTA of Gm1. As mentioned earlier, a unity-gain buffer made of the Miller amplifier (Figure 2a, [17]) cannot be used for synthesis of a biquadratic filter, because its OTA-C equivalent schematic does not contain a lossy integrator. In fact, the circuit in Figure 2a features the second-order characteristic (1), but with Q increasing to infinity. The buffer-based biquad realizations reported in the literature contain lossless and lossy integrators. One should emphasize that the equivalent OTA-C schematics of these biquads may differ from the circuit in Figure 1b. For example, a closed-loop OTA (i.e., a lossy circuit) can be placed at the filter input [6,8,9]. Such reverse OTA-C topologies can also be obtained from ladders with single-resistance termination. The first method exploits the bilateral nature of ladders, i.e., the ladder of Figure 1a can be driven in a current mode from its output (Vout) side leading to the reciprocal OTA-C structures [18]. Alternatively, a different type of single-resistance terminated ladder that has a resistor on its input can be used [19]. To make the work concise, the synthesis examples are limited to conventional ladder configurations that are terminated with an output resistor, as shown in Figure 1a.
The transistorized solutions for lossless and lossy integrators are presented in the next section. The buffer-based biquad realizations reported in the literature contain lossless and lossy integrators. One should emphasize that the equivalent OTA-C schematics of these biquads may differ from the circuit in Figure 1b. For example, a closed-loop OTA (i.e., a lossy circuit) can be placed at the filter input [6,8,9]. Such reverse OTA-C topologies can also be obtained from ladders with single-resistance termination. The first method exploits the bilateral nature of ladders, i.e., the ladder of Figure 1a can be driven in a current mode from its output (V out ) side leading to the reciprocal OTA-C structures [18]. Alternatively, a different type of single-resistance terminated ladder that has a resistor on its input can be used [19]. To make the work concise, the synthesis examples are limited to conventional ladder configurations that are terminated with an output resistor, as shown in Figure 1a.
The transistorized solutions for lossless and lossy integrators are presented in the next section.

Proposed Lossless Integrator
The proposed lossless integrator is depicted in Figure 3a. It comprises a standard differential amplifier (transistors M 1 -M 4 ), and a floating integrating capacitor (C). C par1 and C par2 are the main parasitic capacitances.

Proposed Lossless Integrator
The proposed lossless integrator is depicted in Figure 3a. It comprises a standard differential amplifier (transistors M1-M4), and a floating integrating capacitor (C). Cpar1 and Cpar2 are the main parasitic capacitances. The transfer function of the integrator in Figure3a is given as It can be shown that under proper conditions Cpar1 does not significantly affect the AC response of the integrator. For example, if Cpar1 is large (Cpar1 >> C) then the drain of M1 is "strongly" shorted to GND and, as a consequence, C is connected in parallel to Cpar2. The transmittance (2) reduces to the simple form 0.5gm1,2/(s(C + Cpar2)) which represents a closeto-ideal integrator. Nevertheless, for low-frequency filters C is tens of pF, thus applying Cpar1 >> C is impractical. Note that Cpar1, as well as Cpar2 result from parasitic capacitances of transistors, and they are tens to hundreds of fF. Therefore, in a practical low-frequency circuit, the inequalities Cpar1 << C and Cpar2 << C are fulfilled resulting in reduction of the integrator transmittance (2) to the form The last fractional term in (3) represents a transmittance of an allpass filter. Thus, to improve the integrator response (3) one can slightly increase Cpar1. Even small Cpar1 comparable to Cpar2 provides acceptable results. Figure 3b presents the flow of currents assuming Cpar1 ≥ Cpar2, Cpar1 << C, and Cpar2 << C. Under these conditions the integrating capacitor C intercepts most of the AC current (iac) and the transistors M3 and M4 conduct only DC currents of IB (the current mirrors M3-M4 operate rather like an auto bias circuit). In consequence, the proposed integrator configuration with a floating capacitor has three major advantages over the conventional grounded-capacitor configuration. First, the parasitic The transfer function of the integrator in Figure 3a is given as where g m1,2 = 2g m1 g m2 /(g m1 + g m2 ). If g m1 is equal to g m2 then g m1,2 = g m1 = g m2 . It can be shown that under proper conditions C par1 does not significantly affect the AC response of the integrator. For example, if C par1 is large (C par1 >> C) then the drain of M 1 is "strongly" shorted to GND and, as a consequence, C is connected in parallel to C par2 . The transmittance (2) reduces to the simple form 0.5g m1,2 /(s(C + C par2 )) which represents a close-to-ideal integrator. Nevertheless, for low-frequency filters C is tens of pF, thus applying C par1 >> C is impractical. Note that C par1 , as well as C par2 result from parasitic capacitances of transistors, and they are tens to hundreds of fF. Therefore, in a practical low-frequency circuit, the inequalities C par1 << C and C par2 << C are fulfilled resulting in reduction of the integrator transmittance (2) to the form The last fractional term in (3) represents a transmittance of an allpass filter. Thus, to improve the integrator response (3) one can slightly increase C par1 . Even small C par1 comparable to C par2 provides acceptable results. Figure 3b presents the flow of currents assuming C par1 ≥ C par2 , C par1 << C, and C par2 << C. Under these conditions the integrating capacitor C intercepts most of the AC current (i ac ) and the transistors M 3 and M 4 conduct only DC currents of I B (the current mirrors M 3 -M 4 operate rather like an auto bias circuit). In consequence, the proposed integrator configuration with a floating capacitor has three major advantages over the conventional grounded-capacitor configuration. First, the parasitic capacitance C par1 helps to stabilize the currents in M 3 and M 4 . Second, the mismatch between g m3 and g m4 does not affect AC response of the integrator. Third, due to i ac = 0.5·g m1,2 ·(V + − V − ), an integration time constant is doubled, that is advantageous for low-frequency filter realizations. In a filter synthesis process, the floating-capacitor integrator of Figure 3a can be represented by the Gm-C integrator composed of a grounded capacitor of C and a transconductor of G m = 0.5g m1,2 , as shown in Figure 3c.
In the analysis presented here, the output conductances (g ds ) of the transistors are neglected because otherwise the integrator transfer function becomes too complicated to interpret. The body effect in the differential pair M 1 -M 2 is also neglected in the analysis because it does not affect the transfer function (2).

Lossy Integrator
A lossy integrator can be implemented using the proposed differential integrator in Figure 3a through introduction of a feedback loop that connects the output V out to the inverting input V − . However, one can derive a much simpler implementation using a conventional MOS source follower shown in Figure 4a. Its transmittance is as follows where g mb denotes the bulk (body) transconductance of the MOS transistor, and C gs is its gate-source capacitance.
capacitance Cpar1 helps to stabilize the currents in M3 and M4. Second, the mismatch between gm3 and gm4 does not affect AC response of the integrator. Third, due to iac = 0.5•gm1,2•(V+ − V−), an integration time constant is doubled, that is advantageous for lowfrequency filter realizations. In a filter synthesis process, the floating-capacitor integrator of Figure 3a can be represented by the Gm-C integrator composed of a grounded capacitor of C and a transconductor of Gm = 0.5gm1,2, as shown in Figure 3c.
In the analysis presented here, the output conductances (gds) of the transistors are neglected because otherwise the integrator transfer function becomes too complicated to interpret. The body effect in the differential pair M1-M2 is also neglected in the analysis because it does not affect the transfer function (2).

Lossy Integrator
A lossy integrator can be implemented using the proposed differential integrator in Figure 3a through introduction of a feedback loop that connects the output Vout to the inverting input V−. However, one can derive a much simpler implementation using a conventional MOS source follower shown in Figure 4a. Its transmittance is as follows where gmb denotes the bulk (body) transconductance of the MOS transistor, and Cgs is its gate-source capacitance. The integrator transmittance (4) has a pole associated with C + Cgs and a parasitic zero associated with Cgs. However, this zero is located 2 to 3 decades away from the pole because in low-frequency realizations the integrating capacitance C is of the order of pF and is much higher than the parasitic Cgs (fF). Thereby, Cgs can be neglected in (4). On the other hand, the parasitic body transconductance gmb cannot be neglected in (4) because it is comparable to the main integrating transconductance gm (gmb ≈ 0.2 gm). Therefore, when the transistor body terminal Vb is not connected to Vout (see Figure 4a), the body effect results in an additional OTA of gmb, as shown in Figure 4b, or in an additional voltage amplifier of gain of 1 Ω/R' = 1 + gmb/gm (V/V), as depicted in Figure 4c. Fortunately, these extra amplifiers do not need to be implemented because the body effect can be accounted for in the course of filter synthesis by pre-modifying the component values in a ladder prototype. The body effect alters the termination resistor value to R', as explained in Figure 4d  The integrator transmittance (4) has a pole associated with C + C gs and a parasitic zero associated with C gs . However, this zero is located 2 to 3 decades away from the pole because in low-frequency realizations the integrating capacitance C is of the order of pF and is much higher than the parasitic C gs (fF). Thereby, C gs can be neglected in (4). On the other hand, the parasitic body transconductance g mb cannot be neglected in (4) because it is comparable to the main integrating transconductance g m (g mb ≈ 0.2 g m ). Therefore, when the transistor body terminal V b is not connected to V out (see Figure 4a), the body effect results in an additional OTA of g mb , as shown in Figure 4b, or in an additional voltage amplifier of gain of 1 Ω/R' = 1 + g mb /g m (V/V), as depicted in Figure 4c. Fortunately, these extra amplifiers do not need to be implemented because the body effect can be accounted for in the course of filter synthesis by pre-modifying the component values in a ladder prototype. The body effect alters the termination resistor value to R', as explained in Figure 4d. The new value of R' involves updating the rest of the ladder components resulting from denormalization of impedance. For example, the component values in the ladder of Figure 1a, pre-modified due to the body effect, would be: R' = 1 Ω/(1 + g mb /g m ), C 1P ' = C 1P ·R/R', and L 2P ' = L 2P ·R'/R.

Proposed Biquadratic Filter
Using the integrators of Figures 3a and 4a, the biquadratic filter can be synthesized according to the schematic of Figure 1b. Assuming no-body-effect in the integrator of Figure 4a (V b connected with V out ), the transistor-level realization of the filter can be represented as the transistor-level circuit shown in Figure 5. Note that the synthesis has resulted in the filter based on the unity-gain buffer of ref. [20], but in opposite-transistortype configuration. ure 4a (Vb connected with Vout), the transistor-level realizatio sented as the transistor-level circuit shown in Figure 5. Note th in the filter based on the unity-gain buffer of ref. [20], but in o figuration. The example 100-Hz filter has been designed for biomedi ply voltage of 0.4 V and power consumption in the range of 1 ment for such a low supply voltage, the X-FAB transistors w (nominal VTHP = −0.35 V, VTHN = 0.4 V) are selected. Furthermo transistors are connected to GND to reduce their threshold vo bulk and source of M5 are connected in order to reduce the th to avoid a correction of filter parameters due to the body eff 3.2). The bias current IB is set to 250 pA in order to limit the tr to the level of a few nS and allow use of filter capacitors with than a few tens of pF. The detailed parameters of the transisto  The bulk and source of M5 are connected in order to reduce the threshold voltage, as well as to avoid a correction of filter parameters due to the body effect (as described in Section 3.2). The bias current I B is set to 250 pA in order to limit the transistors' transconductance to the level of a few nS and allow use of filter capacitors with practical values no greater than a few tens of pF. The detailed parameters of the transistors are given in Table 1.  Note that the dimensions of the "mirroring" transistors, M 3 and M 4 , are large to increase their parasitic capacitances (C par1 in Figure 3a) and improve an integrator response, as explained earlier in Section 3.1. The "integrating" transistors, M 1 , M 2 , and M 5 , have transconductances of g m1 ∼ = g m2 = g m1,2 = 7.9 ns and g m5 = 8.3 nS. Thus, the transconductances of the equivalent OTAs in Figure 1b are: G m1 = g m5 = 8.3 nS, G m2 = g m1,2 /2 = 7.9/2 nS.
With the supply voltage V DD of 0.4 V the drain-source voltage (V DS ) of the transistors approaches the triode region limit i.e., 100-200 mV (see Table 1). Under these conditions, the transistors' output conductances (g ds ) increase, which affects f 0 and Q. However, the deviation in the filter characteristics, caused by the increased g ds , is relatively small and can therefore be compensated by a small (up to a few percent) adjustment of the filter capacitances [19]. The corrected values of the capacitances in the biquad of Figure 5 are C 1 = 9.2 pF and C 2 = 8.7 pF.
The simulated amplitude characteristic of the proposed biquad follows the ideal (RLC prototype) response down to −80 dB, as shown in Figure 6a. The detailed values of passband gain and −3-dB frequency are 0.99 V/V and 100 Hz.  Table 1). Under these conditions, the transistors' output conductances (gds) increase, which affects f0 and Q. However, the deviation in the filter characteristics, caused by the increased gds, is relatively small and can therefore be compensated by a small (up to a few percent) adjustment of the filter capacitances [19]. The corrected values of the capacitances in the biquad of Figure 5 are C1 = 9.2 pF and C2 = 8.7 pF.
The simulated amplitude characteristic of the proposed biquad follows the ideal (RLC prototype) response down to −80 dB, as shown in Figure 6a. The detailed values of passband gain and −3-dB frequency are 0.99 V/V and 100 Hz. The −3-dB frequency can be tuned from 50 Hz to 377 Hz by means of changing the bias current IB from 125 pA to 1 nA (Figure 6b). In the presence of the process deviation as well as transistor and capacitor mismatch (Figure 6c  The −3-dB frequency can be tuned from 50 Hz to 377 Hz by means of changing the bias current I B from 125 pA to 1 nA (Figure 6b). In the presence of the process deviation as well as transistor and capacitor mismatch (Figure 6c), the biquad keeps its passband gain of near 0.98-0.99 V/V and stopband attenuation of over 80 dB, whereas spread in the −3-dB frequency is only 4.5 Hz (1 sigma). The filter features a maximum input sine amplitude of 103.4 mV peak (conditions: output THD = 1%, fundamental frequency = 20 Hz, optimal DC input level = 260 mV). The input-referred noise integrated from 1 Hz to 100 Hz is 29 µV RMS , which results in a biquad dynamic range of 68 dB.

Fourth Order Filters
In this section, two designs of fourth-order low-pass filters are presented and compared. One design is obtained using a ladder-based synthesis. Another one is generated by cascading the two biquads of Figure 5. The parameters of the obtained filters have been compared with each other and with the reference ladder prototype. Figure 7a,b shows, respectively, the 4th-order ladder prototype with single-resistance termination and the corresponding OTA-C schematic obtained by the state variable method. Assuming the ideal OTAs (i.e., G m >> G o ), the filter in Figure 7b behaves as a unity-gain buffer because its input resistance is infinity, output resistance decreases to zero, and its gain is 1 V/V in the passband-regardless of the capacitance and the OTA transconductance values. optimal DC input level = 260 mV). The input-referred noise integrated from 1 Hz to 100 Hz is 29 µ VRMS, which results in a biquad dynamic range of 68 dB.

Fourth Order Filters
In this section, two designs of fourth-order low-pass filters are presented and compared. One design is obtained using a ladder-based synthesis. Another one is generated by cascading the two biquads of Figure 5. The parameters of the obtained filters have been compared with each other and with the reference ladder prototype. Figure 7a,b shows, respectively, the 4th-order ladder prototype with single-resistance termination and the corresponding OTA-C schematic obtained by the state variable method. Assuming the ideal OTAs (i.e., Gm >> Go), the filter in Figure 7b behaves as a unitygain buffer because its input resistance is infinity, output resistance decreases to zero, and its gain is 1 V/V in the passband-regardless of the capacitance and the OTA transconductance values.  Table 1). Notice that three additional voltage shifters (MSH) are used in the circuit. They increase the source-drain voltages of the M2 transistors to 100-120 mV, allowing them to operate in the saturation region. Without the shifters, the M2 source-drain voltages would be around 30 mV, that is below the triode region boundary. Using the integrators shown in Figures 3a and 4a and following the schematic in Figure 7b (for R = 1) the transistorized filter shown in Figure 7c is obtained. The transistor parameters are the same as in the biquad of Figure 5 (see Table 1). Notice that three additional voltage shifters (M SH ) are used in the circuit. They increase the source-drain voltages of the M 2 transistors to 100-120 mV, allowing them to operate in the saturation region. Without the shifters, the M 2 source-drain voltages would be around 30 mV, that is below the triode region boundary. Figure 7b correspond to transconductances of transistors in Figure 7c as follows: G m1 = g m5 , G m2 = G m3 = G m4 = g m1,2 /2. The components in the normalized Butterworth ladder of Figure 6a are as follows: R = 1 Ω, C 1P = 0.3827 F, C 3P = 1.5772 F, L 2P = 1.0824 H, and L 4P = 1.5307 H [21]. Therefore, assuming f −3dB = f 0 = 100 Hz, the capacitances calculated for the filter in Figure 7c are as follows: C 1 = g m5 ·C 1P /(2πf 0 ) = 5.05 pF, C 2 = g m1,2 ·L 2P /(2πf 0 ) = 6.80 pF, C 3 = g m1,2 ·C 3P /(2πf 0 ) = 9.91 pF, and C 4 = g m1,2 ·L 4P /(2πf 0 ) = 9.62 pF. After applying correction to these capacitances due to low V DD and increased g ds (as mentioned earlier in Section 4 [19]), their final values are as follows: C 1 = 4.98 pF, C 2 = 6.73 pF, C 3 = 9.80 pF, and C 4 = 9.50 pF.

Cascade Filter
Cascading the two biquads from Figure 5 results in the fourth-order filte Figure 8. To obtain the Butterworth approximation and 100-Hz bandwidth, frequencies and quality factors of the consecutive biquads should be: ω0A = 2π QA = 0.541, ω0B = 2π•100 rad/s, and QB = 1.307. Assuming the transistor transco given in Table 1

Simulations and Comparison
The nominal amplitude responses (for IB = 250 pA) of the designed fourthtures are shown in Figure 9a. In the passband, the circuits have the same gain V/V (−264 mdB to −175 mdB). In the stopband, the gain of the ladder-based filte to −120 dB, which is a worse result compared to the cascade filter (−160 dB) frequency in both realizations is the same (100.1 Hz) and can be tuned from 5 Hz (Figure 9b).

Simulations and Comparison
The nominal amplitude responses (for I B = 250 pA) of the designed fourth-order structures are shown in Figure 9a. In the passband, the circuits have the same gain of 0.97-0.98 V/V (−264 mdB to −175 mdB). In the stopband, the gain of the ladder-based filter decreases to −120 dB, which is a worse result compared to the cascade filter (−160 dB). The −3-dB frequency in both realizations is the same (100.1 Hz) and can be tuned from 51 Hz to 377 Hz (Figure 9b). The influence of fabrication process spread and the mismatch of the filter components is illustrated in Figure 9c. As can be seen both filters behave similarly. The changes in the passband gain are insignificant, whereas a 1-sigma deviation in −3-dB frequency is only 4.5 Hz. Details of the filter performance under process-voltage-temperature (PVT) variations are provided in Appendix.
In conclusion, both the ladder-based and cascade filters feature a similar maximum input sine amplitude of about 70 mVpeak ( Figure 9d) and a noise of about 50 µ VRMS. As a result, a similar dynamic range of about 60 dB is obtained for both circuits. The ladderbased realization provides 8.9 pF smaller total capacitance, that translates to a reduction of 4050 µ m 2 on a chip assuming the use of typical MIM capacitors of 2.2 fF/µ m 2 . Since the area of the capacitors determines the total area of the filters, the latter parameter is easily scalable and predictable. In addition, the total current consumption can be easy predicted because it results simply from the total number of the bias sources IB, as given in Table 2. The influence of fabrication process spread and the mismatch of the filter components is illustrated in Figure 9c. As can be seen both filters behave similarly. The changes in the passband gain are insignificant, whereas a 1-sigma deviation in −3-dB frequency is only 4.5 Hz. Details of the filter performance under process-voltage-temperature (PVT) variations are provided in Appendix A.
In conclusion, both the ladder-based and cascade filters feature a similar maximum input sine amplitude of about 70 mV peak ( Figure 9d) and a noise of about 50 µV RMS . As a result, a similar dynamic range of about 60 dB is obtained for both circuits. The ladderbased realization provides 8.9 pF smaller total capacitance, that translates to a reduction of 4050 µm 2 on a chip assuming the use of typical MIM capacitors of 2.2 fF/µm 2 . Since the area of the capacitors determines the total area of the filters, the latter parameter is easily scalable and predictable. In addition, the total current consumption can be easy predicted because it results simply from the total number of the bias sources I B , as given in Table 2. Table 2. Scalable properties of the developed 0.4-V, 100-Hz filters.

Summary of Low-Frequency Filter Performance
The parameters of the proposed and other state-of-the-art transistorized filters are collated in Table 3. The filters from [6][7][8][9][10] are selected due to their reported low supply voltages. The examples of OTA-C realizations, [11,12,14] are also included in the comparison. These OTA-C filters feature much smaller total capacitance (6-9 pF) compared to the transistorized solutions (25-80 pF). This results from the fact that a linear OTA has smaller transconductance (compared to a transistor) because linearization techniques are involved in its reduction. Thus, OTAs in refs. [11,12,14] have been linearized by a source degeneration reducing the transconductance to the range of single nano siemens. However, linearization techniques also increase the complexity and noise of the circuit [13,21]. In consequence, the OTA-C filters [11,12,14] are characterized by a high noise of over 190 µV RMS . Note that OTA-C filters from refs. [11,12] feature a passband gain that is much lower than 1 V/V (−10.5 and −6 dB respectively), implying an increase of the input referred noise (IRN). However, one should emphasize that the low gain of these structures results from a synthesis based on double-resistance terminated ladders being characterized by 0.5-V/V gain. Thus, the noise performance of OTA-C filters [11,12] could be improved if ladders with single-resistance termination and gain of 1-V/V were used.
The transistorized solutions gathered in Table 3 provide only a slightly better dynamic range compared to OTA-C realizations. However, the power consumption of the transistorized filters (6-15 nW) is one to two orders lower compared to OTA-C filters (350-450 nW). In terms of power consumption, the proposed filters achieve best results of 0.6-1 nW (predicted by simulations). In addition, in terms of total capacitance and supply voltage, the proposed solutions outperform all other filters except the one from ref. [9].

Conclusions
Buffer-based "transistorized" filters are a promising alternative to OTA-C-based structures. The synthesis methodology of buffer-based filters, using the analogy to RLC ladder filters with single-resistance termination, was presented. Innovative transistor-level solutions operating at supply voltages of only 0.4 V were also proposed.
Author Contributions: All authors contributed equally in conceptualization, methodology, formal analysis, simulations, writing-original draft preparation, and writing-review and editing. All authors have read and agreed to the published version of the manuscript.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

Appendix A
This appendix provides in Tables A1 and A2 simulations results of −3-dB frequency and DC gain (passband gain) of the proposed fourth-order filters under PVT variation. Table A1. Process (CMOS 180 nm X-FAB) corner simulation results for the ladder-based filter in Figure 7c.  Table A2. Process (CMOS 180 nm X-FAB) corner simulation results for the cascade filter in Figure 8.