A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter

This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 μm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm2, of which the bootstrap area is 0.149 mm2 and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers.


Introduction
With the continuous development of modern electronic equipment power supplies, miniaturized and high-performance power drivers have become a current research hotspot [1][2][3][4][5][6]. Regarding traditional silicon complementary metal-oxide-semiconductor (CMOS) technology, NMOS (n-channel metal-oxide-semiconductor) is usually selected as the power device [7][8][9], which is mainly attributed to its high carrier mobility and desirable device area [10]. Additionally, third-generation semiconductor power devices with the characteristics of high speed and low on-resistance, such as GaN HEMTs (gallium nitride high-electron-mobility transistors) [11][12][13][14], are also dominated by N-type devices.
LDOs [15], dc-dc converters (such as charge pumps [16][17][18]) and pre-regulators [19] are mainly employed in a low-side N-Type power MOS structure with the power supply relative to ground. Regarding a high-side N-type power device, the floating source demonstrates the high-side driving problem of the device [20,21], which is usually solved by bootstrap charging circuits [22][23][24]. The principle of these circuits is to provide a voltage that is relative to the floating source, namely the switching node (V SW ), for driver and power MOS [25]. Although the traditional bootstrap charging circuit shown in Figure 1 has a simple structure, there are still a series of problems to be solved.
The traditional bootstrap charging circuit needs a fixed charging voltage V DD , which is generally set between 5 and 6 V, and it is generated by the on-chip power supply. In the case of a large driving capability and high switching frequency, the requirements for the load current, bandwidth, and stability of the on-chip regulator are relatively high, which increases the design difficulty of the LDO. On the other hand, the change in the V DD will cause a certain offset in the V boot voltage of the traditional bootstrap circuit. When the bootstrap voltage is too high, the gate of the power device, especially the GaN HEMT, easily breaks down. Conversely, a bootstrap voltage that is too low will affect the driving capability of the circuit, resulting in excessive on-resistance of the power device and increasing power loss. Li, S.T. et al., proposed the theory of active bootstrap control (ABC) [26], that is, the logic control of the high-side signal, low-side signal, and dead time ensures that the bootstrap capacitor is charged only when the low-side power device is turned on. Ke, X. et al., proposed an active BST balancing (ABB) method to achieve bootstrap voltage control [27]. The traditional bootstrap charging circuit needs a fixed charging voltage VDD, which is generally set between 5 and 6 V, and it is generated by the on-chip power supply. In the case of a large driving capability and high switching frequency, the requirements for the load current, bandwidth, and stability of the on-chip regulator are relatively high, which increases the design difficulty of the LDO. On the other hand, the change in the VDD will cause a certain offset in the Vboot voltage of the traditional bootstrap circuit. When the bootstrap voltage is too high, the gate of the power device, especially the GaN HEMT, easily breaks down. Conversely, a bootstrap voltage that is too low will affect the driving capability of the circuit, resulting in excessive on-resistance of the power device and increasing power loss. Li, S.T. et al. proposed the theory of active bootstrap control (ABC) [26], that is, the logic control of the high-side signal, low-side signal, and dead time ensures that the bootstrap capacitor is charged only when the low-side power device is turned on. Ke, X. et al. proposed an active BST balancing (ABB) method to achieve bootstrap voltage control [27].
Although a series of considerable research results have been achieved in bootstrap voltage control, there are still certain challenges in reducing the pressure on LDO design. Ming, X. et al. proposed an advanced bootstrap circuit structure that does not depend on the voltage of the on-chip low dropout linear regulator, which also ensures the stability of the high-side power rail by using the directly sensed bootstrap voltage (DSBV) [28]. A bootstrap structure is proposed by Liu, Y. et al., the bootstrap voltage of which is charged by input power and regulated by a feedback loop [29]. The conventional structure employs an analog feedback loop, the speed of which is influenced by the loop bandwidth, while high bandwidth and high stability are hard to achieve at the same time. Herein, based on the above-mentioned research, this paper presents a bootstrap circuit structure with the following advantages: a small area, high frequency, and good figure-of-merit (FOM). Without an analog loop, the speed of the structure is only determined by the threshold-based detection circuit, avoiding the trade-off between bandwidth and stability. The DCBV circuit is used to directly charge the bootstrap capacitor from the BUS voltage VIN, which greatly reduces the design difficulty of the low dropout linear regulator. The Although a series of considerable research results have been achieved in bootstrap voltage control, there are still certain challenges in reducing the pressure on LDO design. Ming, X. et al., proposed an advanced bootstrap circuit structure that does not depend on the voltage of the on-chip low dropout linear regulator, which also ensures the stability of the high-side power rail by using the directly sensed bootstrap voltage (DSBV) [28]. A bootstrap structure is proposed by Liu, Y. et al., the bootstrap voltage of which is charged by input power and regulated by a feedback loop [29]. The conventional structure employs an analog feedback loop, the speed of which is influenced by the loop bandwidth, while high bandwidth and high stability are hard to achieve at the same time. Herein, based on the above-mentioned research, this paper presents a bootstrap circuit structure with the following advantages: a small area, high frequency, and good figure-of-merit (FOM). Without an analog loop, the speed of the structure is only determined by the thresholdbased detection circuit, avoiding the trade-off between bandwidth and stability. The DCBV circuit is used to directly charge the bootstrap capacitor from the BUS voltage V IN , which greatly reduces the design difficulty of the low dropout linear regulator. The TBDC circuit is used to detect the voltage of the high-side bootstrap power rail, which can control the on-off of the PMOS switch in the DCBV circuit, thereby ensuring that the bootstrap voltage is within the required range.

Concept of the Proposed Bootstrap Architecture
As shown in Figure 2, the DCBV is directly used in the bootstrap charging of the proposed structure, which reduces the pressure on the bandwidth and load capacity of the on-chip LDO at high frequency. The TBDC circuit is used to detect the bootstrap voltage, which is mainly composed of isolated MOSFETs instead of high-voltage devices, and As shown in Figure 2, the DCBV is directly used in the bootstrap charging of the proposed structure, which reduces the pressure on the bandwidth and load capacity of the on-chip LDO at high frequency. The TBDC circuit is used to detect the bootstrap voltage, which is mainly composed of isolated MOSFETs instead of high-voltage devices, and controls the charging path of the bootstrap. Moreover, the logic control module is related to the detection result of the TBDC.
When the TBDC detects that the bootstrap voltage is lower than the under-voltage threshold VTHL, the under-voltage signal uv will pull down the driving signal in the control logic circuit to turn off the power device, thereby avoiding the efficiency loss caused by insufficient driving voltage. When the TBDC detects that the bootstrap voltage exceeds the over-voltage threshold VTHH, the non-over-voltage signal _ov is set to 0, and the gate of the PMOS switch (PM) is pulled up to VIN by the bias resistor Rb, resulting in the shutdown of PM and charging path. Moreover, the bootstrap voltage slowly decreases until the TBDC detects that the bootstrap is lower than the over-voltage threshold VTHH. Additionally, the _ov signal remains high. The high-voltage NMOS (NM) is turned on, and the bias current Ib causes a voltage drop on the bias resistor Rb. Next, the PM is turned on, and the BUS voltage VIN charges the bootstrap capacitor Cboot through the bootstrap diode Dboot. The charging path is shown as a red arrow, and the bootstrap voltage increases immediately. The above processes are repeated during normal operation. Due to a slight delay in the DCBV circuit, the bootstrap voltage is controlled within a voltage range with a small ripple (VTHH ± ∆V).
In the case of high-frequency operation, the traditional structure has relatively high requirements for the bandwidth and load regulation rate of the LDO. However, the structure designed in this work does not rely on an LDO power supply, which is more suitable for higher frequency.
The working sequence of this circuit is shown in Figure 3. When the TBDC detects that the bootstrap voltage is lower than the under-voltage threshold V THL , the under-voltage signal uv will pull down the driving signal in the control logic circuit to turn off the power device, thereby avoiding the efficiency loss caused by insufficient driving voltage.
When the TBDC detects that the bootstrap voltage exceeds the over-voltage threshold V THH , the non-over-voltage signal _ov is set to 0, and the gate of the PMOS switch (PM) is pulled up to V IN by the bias resistor R b , resulting in the shutdown of PM and charging path. Moreover, the bootstrap voltage slowly decreases until the TBDC detects that the bootstrap is lower than the over-voltage threshold V THH . Additionally, the _ov signal remains high. The high-voltage NMOS (NM) is turned on, and the bias current I b causes a voltage drop on the bias resistor R b . Next, the PM is turned on, and the BUS voltage V IN charges the bootstrap capacitor C boot through the bootstrap diode D boot . The charging path is shown as a red arrow, and the bootstrap voltage increases immediately. The above processes are repeated during normal operation. Due to a slight delay in the DCBV circuit, the bootstrap voltage is controlled within a voltage range with a small ripple (V THH ± ∆V).
In the case of high-frequency operation, the traditional structure has relatively high requirements for the bandwidth and load regulation rate of the LDO. However, the structure designed in this work does not rely on an LDO power supply, which is more suitable for higher frequency.
The working sequence of this circuit is shown in Figure 3.

Power on (Under-Voltage)
When the BUS voltage V IN is powered on, the LDO starts to work, and then the low-voltage power supply V DD increases to 5 V as shown in Figure 3, status 1 . The enable signal EN then turns from low to high. At this time, the external input signal pwm is low. The high-side power NMOS remains off, and the switch node V SW is 0. Moreover, the bootstrap voltage is lower than the under-voltage threshold V THL , and the under-voltage signal uv is the V DD . The uv signal turns off the high-side N-type power device in the control logic circuit.
The _ov signal is also the V DD , so the bootstrap charging path is opened, and the bootstrap voltage increases.

Power on (Under-Voltage)
When the BUS voltage VIN is powered on, the LDO starts to work, and then the lowvoltage power supply VDD increases to 5 V as shown in Figure 3, status ①. The enable signal EN then turns from low to high. At this time, the external input signal pwm is low. The high-side power NMOS remains off, and the switch node VSW is 0. Moreover, the bootstrap voltage is lower than the under-voltage threshold VTHL, and the under-voltage signal uv is the VDD. The uv signal turns off the high-side N-type power device in the control logic circuit.
The _ov signal is also the VDD, so the bootstrap charging path is opened, and the bootstrap voltage increases.

Charging
When the bootstrap voltage increases to the under-voltage threshold VTHL as shown in Figure 3, status ②, the under-voltage signal uv reverses from the VDD to the GND, and the pwm signal can normally control the high-side power NMOS.
Additionally, the _ov signal is still the VDD, and the bootstrap charging path remains open, causing the bootstrap voltage to continue increasing.

Charging
When the bootstrap voltage increases to the under-voltage threshold V THL as shown in Figure 3, status 2 , the under-voltage signal uv reverses from the V DD to the GND, and the pwm signal can normally control the high-side power NMOS.
Additionally, the _ov signal is still the V DD , and the bootstrap charging path remains open, causing the bootstrap voltage to continue increasing.

Discharging (Over-Voltage)
When the bootstrap voltage exceeds the over-voltage threshold V THH as shown in Figure 3, status 3 , the _ov signal is flipped from the V DD to the GND. Therefore, the charging path is turned off, and the bootstrap voltage slowly decreases.

Repeating (pwm Remains Low)
When the external input signal pwm continues to be low and the bootstrap voltage decreases to less than the over-voltage threshold V THH as shown in Figure 3, status 4 , processes Charging (status 2 ) and Discharging (status 3 ) are repeated.

pwm Becoming High
When the external input signal pwm becomes high, the high-side power NMOS is turned on, and the switch node V SW voltage is pulled up to the BUS voltage V IN as shown in Figure 3, status 5 . At this time, since the voltage at the anode of the bootstrap diode D boot is the BUS voltage V IN and the voltage at the negative terminal of D boot is the high-side bootstrap power rail voltage V boot , the charging path cannot be charged. Additionally, the high-side bootstrap power rail slowly decreases due to the power supply to the high-side driver and the leakage of the bootstrap capacitor C boot .
2.1.6. pwm Becoming Low As status 6 shows in Figure 3, after the input signal pwm becomes low, processes Charging and Discharging are repeated, which behaves the same as status 4 .

Circuit Realization
The TBDC circuit is used to detect the over-voltage and under-voltage conditions of the bootstrap voltage, which is composed of three parts as shown in Figure 4, including a current bias and start-up circuit, an under-voltage detection circuit, and an over-voltage detection circuit. In addition, level shifter and driver are shown in Figures 5 and 6, respectively.

Repeating (pwm Remains Low)
When the external input signal pwm continues to be low and the bootstrap voltage decreases to less than the over-voltage threshold VTHH as shown in Figure 3, status ④, processes Charging (status ②) and Discharging (status ③) are repeated.

pwm Becoming High
When the external input signal pwm becomes high, the high-side power NMOS is turned on, and the switch node VSW voltage is pulled up to the BUS voltage VIN as shown in Figure 3, status ⑤. At this time, since the voltage at the anode of the bootstrap diode Dboot is the BUS voltage VIN and the voltage at the negative terminal of Dboot is the highside bootstrap power rail voltage Vboot, the charging path cannot be charged. Additionally, the high-side bootstrap power rail slowly decreases due to the power supply to the highside driver and the leakage of the bootstrap capacitor Cboot.

pwm Becoming Low
As status ⑥ shows in Figure 3, after the input signal pwm becomes low, processes Charging and Discharging are repeated, which behaves the same as status ④.

Circuit Realization
The TBDC circuit is used to detect the over-voltage and under-voltage conditions of the bootstrap voltage, which is composed of three parts as shown in Figure 4, including a current bias and start-up circuit, an under-voltage detection circuit, and an over-voltage detection circuit. In addition, level shifter and driver are shown in Figure 5 and Figure 6, respectively.

TBDC Circuit
• Current bias and start-up circuit The current bias and start-up circuit are shown in the left part in Figure 4, which are composed of isolated PMOS PM1-PM2, isolated NMOS NM1-NM2, and a resistor R1. PM1 mirrors the current of PM2, and resistor R1 is used to control the magnitude of the bias current. The bias current increases as the bootstrap voltage increases until it stabilizes. The stable bias current is [30]: (1) Figure 6. Circuit realization of driver and waveforms of hs_in, gate of PM 10 and NM 16 .

TBDC Circuit
• Current bias and start-up circuit The current bias and start-up circuit are shown in the left part in Figure 4, which are composed of isolated PMOS PM 1 -PM 2 , isolated NMOS NM 1 -NM 2 , and a resistor R 1 . PM 1 mirrors the current of PM 2 , and resistor R 1 is used to control the magnitude of the bias current. The bias current increases as the bootstrap voltage increases until it stabilizes. The stable bias current is [30]: where µ n is the electron mobility of NM 1 , C ox is the gate-oxide capacitance per unit area, (W/L) 1 is the ratio of width and length of NM 1 , and K is the ratio of NM 2 and NM 1 . The value of I out is set to 1 µA to balance the power consumption and area. The length of NM 1 is set to 2 µm so that the channel length modulation effect can be reduced. The value of K is set to 32 and resistance of R 1 is about 170 KΩ by calculation. To avoid the degenerate state when the current is 0, a start-up structure is introduced with isolated NMOS NM 3 -NM 4 and isolated PMOS PM 3 -PM 4 . When the bias current is 0, the gate-source voltage V GS2 of NM 2 is 0 V. At this time, the gate voltages of PM 3 and PM 4 are 0 V, and they are turned on. Then, the gate of NM 3 is pulled high and turned on, and there is current that flows through resistor R 1 . Therefore, the bias current is not 0, and the degenerate state is eliminated. Once there is flowing current, the gate-source voltage V GS2 of NM 2 increases to a value greater than the threshold voltage V THN , and then NM 4 is turned on. Moreover, the gate voltage of NM 3 is pulled down, and the start-up circuit is turned off. •

Under-voltage detection circuit
The under-voltage detection circuit is shown in the middle part of Figure 4, which is composed of isolated PMOS PM 5 -PM 6 , isolated NMOS NM 5 -NM 7 , resistors R 2 -R 3 , and a level shifter circuit. As the bootstrap voltage gradually increases from 0, the bias current I out rises. PM 5 mirrors the current of PM 2 , and the gate-source voltage V GS5 of PM 5 is equal to the V GS2 of PM 2 . Due to the existence of R 3 and PM 5 , NM 6 cannot be turned on immediately at a low current. At this time, the drain voltage of PM 6 is pulled up to V boot . After the first level shifter circuit, the output of the under-voltage signal uv is V DD .
By adjusting the size of PM 5 , NM 5 , R 2 , and R 3 , the under-voltage threshold V THL voltage can be set to 2.2 V to ensure a low on-resistance of the power NMOS. When the bootstrap voltage reaches V THL , which can be expressed as: NM 6 and NM 7 are turned on, and the drain voltage of NM 7 gradually decreases until it is lower than the threshold of the level shifter. At this time, the output of the under-voltage signal uv is GND. In this case, NM 5 is assumed to be critical saturation, and V DSP5 could be set to the overdrive voltage (about 200 mV to 300 mV). V THN is about 900 mV, and V GSN5 should be larger than threshold voltage. The above data are substituted in equation 2, and then the value of R 2 and R 3 is estimated at about 200 KΩ. •

Over-voltage detection circuit
Isolated PMOS PM 7 -PM 9 , isolated NMOS NM 8 -NM 15 , resistors R 4 -R 5 , Zener diode DZ, and another level shifter circuit constitute an over-voltage detection circuit, as shown in the right part of Figure 4.
The gate voltage of NM 9 is a fixed value when the bias current I out is determined, which is: The source voltage of NM 9 is: Therefore, the gate-source voltage of NM 9 is: When the gate-source voltage of NM 9 is lower than V THN , NM 9 will be turned off, and the gate voltage of NM 15 will be pulled up to V boot , while the drain voltage will be pulled low. Therefore, the output of _ov signal is GND after the level shifter circuit. Therefore, the over-voltage threshold is deduced as: However, there is another device, a Zener diode DZ, used in the over-voltage circuit, which double guarantees _ov signal to be low during its over-voltage. DZ will clamp the source voltage of NM 9 through providing enough current when the bootstrap voltage reaches its threshold. At this time, the threshold voltage is: where V DZ is the clamp voltage of Zener diode. The constant current of this circuit is set to 1 µA each branch, and the size of PM 7 and PM 8 is the same as PM 1 and PM 2 . By adjusting the size of NM 8 , NM 10 -NM 14 , and R 4 , the V THH voltage is set to 6 V, thereby avoiding the breakdown of the power NMOS.
The TBDC circuit is designed with fully isolated devices due to area consideration, and the bootstrap capacitor is directly charged from the BUS voltage with the DCBV circuit, which can be used for higher frequency. Due to the usage of a digital control method, the bootstrap voltage is stable when V IN varies from 6 V to 48 V; therefore, the line regulation of this circuit can be considered close to 0.

Level Shifters
There are two types of level shifters employed in the proposed bootstrap structure. One is a level-up shifter used to control the power NMOS, and the other is a level-down shifter in the TBDC circuit. •

Level-up shifter
The pwm_in signal is the output of control logic, and it is 3.3 V or 5 V relative to ground, which is not suitable to control the driver directly. Therefore, the level-up shifter is adopted to shift the voltage relative to ground to the voltage relative to V SW . The level-up shifter used in the proposed structure is illustrated in Figure 5a. HPM 1 , HPM 2 , HNM 1 , and HNM 2 are the only high-voltage devices in this circuit, and other devices are low-voltage devices (INV1) or isolated devices (PM 11 , PM 12 and INV2). R 7 is a pull-up resistor to ensure the initial condition of hs_in, preventing from floating gate of INV2. •

Level-down shifter
A level-down shifter is used in the TBDC circuit to shift the uv and _ov signal from floating voltage to voltage relative to ground, so that uv can be an input of control logic and _uv is appropriate for controlling NM in the DCBV. The principle of the level-down shifter is similar to that of the level-up shifter, and the circuit is shown in Figure 5b.

Driver
The driver circuit shown in Figure 6 provides sufficient driving current for the power device through PM 10 and NM 16 . The source and sink current are determined by the gate capacitance C GS of the power device, turn-on/off voltage of the power device and required rising/falling time, and can be adjusted by changing the size of PM 10 and NM 16 . Deadtime is used to prevent the power rail from shooting through, and the waveforms of hs_in, gate of PM 10 , and NM 16 are also shown in Figure 6.

Results
The circuit is implemented by the CSMC 0.25 µm 60 V BCD process. Figure 7 shows the micrograph and testbench photos using the proposed bootstrap structure. The chip area is 1.4 × 1.3 mm 2 , of which the bootstrap circuit only occupies 0.149 mm 2 . The maximum input voltage can be up to 48 V, and the operating frequency can reach 5 MHz.  Figure 8 shows the DC simulation result of the TBDC circuit. When the bootstrap voltage is lower than VTHL (2.101 V), uv and _ov are high. When the voltage is between the VTHL and VTHH (2.101-6.099 V), the uv output is low and the _ov output is high. When the voltage between Vboot and VSW is higher than the VTHH (6.099 V), the uv output is low and  Figure 8 shows the DC simulation result of the TBDC circuit. When the bootstrap voltage is lower than V THL (2.101 V), uv and _ov are high. When the voltage is between the V THL and V THH (2.101-6.099 V), the uv output is low and the _ov output is high. When the voltage between V boot and V SW is higher than the V THH (6.099 V), the uv output is low and the _ov output is low.  Figure 8 shows the DC simulation result of the TBDC circuit. When the bootstrap voltage is lower than VTHL (2.101 V), uv and _ov are high. When the voltage is between the VTHL and VTHH (2.101-6.099 V), the uv output is low and the _ov output is high. When the voltage between Vboot and VSW is higher than the VTHH (6.099 V), the uv output is low and the _ov output is low. The overall and enlarged simulation results are shown in Figure 9a,b. When the pwm is 0 and the bootstrap voltage is higher than VTHH (6 V), the output of the _ov signal is 0 V and NM is turned off. Therefore, there is no voltage drop on the bias resistor Rb, and the voltage of VSGP is 0 V, which causes the charging path to be turned off. When the bootstrap voltage is lower than VTHH, the output of the _ov signal is 5 V and NM is turned on. A voltage drop can be formed on the bias resistor Rb, and the voltage of VSGP can increase to 3 V, causing the charging path to be opened. However, the voltage of VSGP only increases to 3 V instead of 5 V, which can be attributed to the fact that the bootstrap voltage is The overall and enlarged simulation results are shown in Figure 9a,b. When the pwm is 0 and the bootstrap voltage is higher than V THH (6 V), the output of the _ov signal is 0 V and NM is turned off. Therefore, there is no voltage drop on the bias resistor R b , and the voltage of V SGP is 0 V, which causes the charging path to be turned off. When the bootstrap voltage is lower than V THH , the output of the _ov signal is 5 V and NM is turned on. A voltage drop can be formed on the bias resistor R b , and the voltage of V SGP can increase to 3 V, causing the charging path to be opened. However, the voltage of V SGP only increases to 3 V instead of 5 V, which can be attributed to the fact that the bootstrap voltage is quickly charged to 6 V by the V IN when the PM is turned on. During this period, the ripple of V boot -V SW is only 1.583 mV.

Simulation Results
The temperature simulation result is shown in Figure 10a. The minimum bootstrap voltage is 5.866 V at −40 • C, and the maximum bootstrap voltage is 6.210 V at 120 • C. The bootstrap voltage is positively correlated with the temperature, and the temperature coefficient is calculated as: The simulation results for different load currents are shown in Figure 10b, indicating a good load regulation. The maximum bootstrap voltage is 6.210 V at 1 A, and the minimum voltage is 6.208 V at 1 mA. The load regulation S v can be calculated as: The simulated result of the buck converter at I load = 1 A configured by this bootstrap structure is shown in Figure 11. The input and output voltages are 14.5 V and 5 V, respectively. The ripple of the output voltage is 2.612 mV with an efficiency of 92.7%. The highest simulated efficiency is 94.87% at 600 mA. The temperature simulation result is shown in Figure 10a. The minimum bootstrap voltage is 5.866 V at −40 °C, and the maximum bootstrap voltage is 6.210 V at 120 °C. The bootstrap voltage is positively correlated with the temperature, and the temperature coefficient is calculated as: The simulation results for different load currents are shown in Figure 10b, indicating a good load regulation. The maximum bootstrap voltage is 6.210 V at 1 A, and the minimum voltage is 6.208 V at 1 mA. The load regulation can be calculated as:  The temperature simulation result is shown in Figure 10a. The minimum bootstrap voltage is 5.866 V at −40 °C, and the maximum bootstrap voltage is 6.210 V at 120 °C. The bootstrap voltage is positively correlated with the temperature, and the temperature coefficient is calculated as: The simulation results for different load currents are shown in Figure 10b, indicating a good load regulation. The maximum bootstrap voltage is 6.210 V at 1 A, and the minimum voltage is 6.208 V at 1 mA. The load regulation can be calculated as:  The simulated result of the buck converter at Iload = 1 A configured by this bootstrap structure is shown in Figure 11. The input and output voltages are 14.5 V and 5 V, respectively. The ripple of the output voltage is 2.612 mV with an efficiency of 92.7%. The highest simulated efficiency is 94.87% at 600 mA.

Test Results
The test result, as shown in Figure 12a, indicates that the voltage power-up time of bootstrap voltage is approximately 170 µs, and the stable voltage is approximately 6 V, which are consistent with the simulation result. The results of different operation frequencies are shown in Figure 12b, indicating good support over a wide frequency range.

Test Results
The test result, as shown in Figure 12a, indicates that the voltage power-up time of bootstrap voltage is approximately 170 µs, and the stable voltage is approximately 6 V, which are consistent with the simulation result. The results of different operation frequencies are shown in Figure 12b, indicating good support over a wide frequency range. Figure 11. Simulation results of buck converter (VIN = 14.5 V, VOUT = 5 V, Iload = 1 A).

Test Results
The test result, as shown in Figure 12a, indicates that the voltage power-up time of bootstrap voltage is approximately 170 µs, and the stable voltage is approximately 6 V, which are consistent with the simulation result. The results of different operation frequencies are shown in Figure 12b, indicating good support over a wide frequency range. A comparison of the simulation and actual measurement results of the buck converter are shown in Figure 13. Under the following conditions, VIN = 14.5 V and VOUT = 5 V, the highest tested efficiency of the circuit is 83.6% (Iload = 400 mA). The figure-of-merit (FOM) is defined as: where A is the silicon area, Iload,max is the maximum load, and η is the efficiency at maximum load [31]. For this definition, a low value indicates a better performance and the circuit achieves a good FOM of 0.074. Due to diode conduction loss, MOS conduction loss, A comparison of the simulation and actual measurement results of the buck converter are shown in Figure 13. Under the following conditions, V IN = 14.5 V and V OUT = 5 V, the highest tested efficiency of the circuit is 83.6% (I load = 400 mA). The figure-of-merit (FOM) is defined as: FOM = A I load,max × η 0.5 (10) where A is the silicon area, I load,max is the maximum load, and η is the efficiency at maximum load [31]. For this definition, a low value indicates a better performance and the circuit achieves a good FOM of 0.074. Due to diode conduction loss, MOS conduction loss, and MOS switching loss, there is a certain gap between the simulation results and the actual measurement results.   Table 1 shows the comparison results between the structure designed in this paper and those reported in previous literature. Compared with the previous research, this work has the advantages of a wider input voltage from 3.6 V to 48 V, higher switching frequency 2 Figure 13. Comparison between the simulated and test results of the buck converter efficiency at different currents (V IN = 14.5 V, V OUT = 5 V). Table 1 shows the comparison results between the structure designed in this paper and those reported in previous literature. Compared with the previous research, this work has the advantages of a wider input voltage from 3.6 V to 48 V, higher switching frequency up to 5 MHz, larger output current of 2.7 A, and a smaller chip area of 1.82 mm 2 with a good FOM of 0.074 while maintaining the same efficiency. With the digital control method being different from previous research, the simulation and test result implicate that the novel DCBV and TBDC methods in the proposed bootstrap structure is feasible and stable. The proposed circuit can be applied to some power areas such as dc-dc converters. However, due to the lack of research on temperature compensation, the temperature coefficient of this structure is not as low as traditional LDOs. Therefore, future research on this circuit include decreasing the temperature coefficient and scaling higher power.

Conclusions
Bootstrap is a key structure for driving and protecting a high-side N-type power device. In this paper, a novel bootstrap circuit has been proposed, which is directly charged by the BUS voltage and employs a digital method to achieve a stable output. With an area of 1.82 mm 2 , this structure exhibits strict voltage control in a wide range of input voltages and frequencies.
It is found that when using the dc-dc asynchronous buck converter, the maximum efficiency of the protype is 83.6%, and the FOM is 0.074, showing its future potential in a wide range of scenarios, such as in power converters, motor drivers, and automobiles.