Theoretical and Experimental Substractions of Device Temperature Determination Utilizing I-V Characterization Applied on AlGaN/GaN HEMT

: A differential analysis of electrical attributes, including the temperature proﬁle and trapping phenomena is introduced using a device analytical spatial electrical model. The resultant current difference caused by the applied voltage variation is divided into isothermal and thermal sections, corresponding to the instantaneous time- or temperature-dependent change. The average temperature relevance is explained in the theoretical section with respect to the thermal proﬁle and major parameters of the device at the operating point. An ambient temperature variation method has been used to determine device average temperature under quasi-static state and pulse operation, was compared with respect to the threshold voltage shift of a high-electron-mobility transistor (HEMT). The experimental sections presents theoretical subtractions of average channel temperature determination including trapping phenomena adapted for the AlGaN/GaN HEMT. The theoretical results found using the analytical model, allow for the consolidation of speciﬁc methodologies for further research to determine the device temperature based on spatially distributed and averaged parameters.


Introduction
The commercial wireless market requires more demanding microwave operation with higher requirements in terms of self-heating, high operating voltage and inherent processes and their impact on the device reliability in consumer electronics [1][2][3]. The presence of two-dimensional electron gas (2DEG) in a gallium nitride (GaN) based structure presents the potential to fabricate high electron mobility transistors (HEMTs) with Schottky diodes employed as excellent devices for application in the microwave and power conversion field. The suppression of the critical temperature increase, caused by high power density along the device active area, requires the utilization of high thermal conductance substrates e.g., silicon carbide (SiC) [4]. Since the devices are microscopic in size, the conventional methods lack the accuracy to estimate the device operating temperature.
Numerous experimental methods were developed to determine the temperature inside and nearby active device area such as Raman spectroscopy or interferometric mapping [5][6][7]. Additionally, various methods utilizing external heating, or a low-power operating regime were employed, taking advantage of specific electro-thermal device properties. However, these methods, that are widely applied to determine average temperature of HEMT operating in the saturation regime, suffer from a lack of accuracy due to the marginalization of the drain current increase caused by, e.g., gate length modulation or leakage effects [8][9][10]. Moreover, the current comparison at the defined operating point to the peak current under short-pulsed operation at various ambient temperatures [11] in these devices does not account for time dependent isothermal phenomena caused processes such as by charge trapping.
Although device thermal simulations, based on non-linear equations, resolve thermal processes inside the structure [12], the combined integral and differential analysis of the resultant current and the separation of the isothermal and thermal sections are emphasized in this work. The complex theoretical considerations, utilizing thermal profile variation, were simplified and adapted for the practical purposes to acquire the average HEMT channel temperature. The theoretical and experimental results obtained are present the potential to improve and consolidate the already utilized methodologies described empirically for specific devices.

Electrical Model
The presented model is possible to be applied to an n-port device with applied voltage V n considering resultant current I at one port and neglecting the other port current. Devices meeting these requirements are e.g., Schottky diode, ungated or gated transmission line model (TLM) structure such as field-effect transistor (FET) when neglecting the gate current.
The resultant current change dI (∆I) consists of an isothermal section dI E (∆I E ) induced by applied voltage change dV n (∆V n ) and isothermal trapped charge variation dQ TE (X) (∆Q TE (X)) and thermal section dI T (∆I T ) assigned to spatial temperature change dT(X) (∆T(X)) and the thermal trapped charge variation dQ TT (X) (∆Q TT (X)): The current change is defined for the time interval dt (∆t) considering the device area consisting of spatial elements dX (∆X) and thermal profile T(X). The resultant trapped charge dQ T (X) (∆Q T (X)) is defined in a similar way, as follows: In general, dI E is related to dV n and dQ TE (X) by time invariant coefficients k Vn and k Q (X), respectively, whereas dI T is related to dT(X) and dQ TT (X) by time invariant coefficients k T (X) and k Q (X), respectively: In (4) k TT (X) = dQ TT (X)/dT(X) is time and state dependent variable. The coefficients k Q (X), k T (X), k TT (X) and k Vn at the operating point defined by V n , I and T(X) at time t can be obtained using an analytical solution or advanced simulation software calibrated by experimental results. Although the majority of commercially utilized simulation software allows for self-heating to be switched off/on [12] or DC measurements to be realized in a pulse or quasi-static state [13], it is impossible to turn self-heating on separately to obtain T(X) and I at a predefined operating point and to subsequently turn it off for ∆t and ∆V n to separate ∆I T and ∆I E .
It is recommended that the device current response of a stepping and rectangular pulse source is differentiated into time elements ∆t to find the particular ∆I E and ∆I T as shown in Figure 1a,b, respectively. The small parasitic capacitance, typical for GaN-based devices, and a short switching time of the stepping source in comparison with thermal and trapping time constants make it possible for ∆I T to be obtained as the difference between I acquired at t 1 +∆t and at t 1 +∆t in the case of a negligible ∆Q TE (X). To reach an equilibrium state during quasi-static stepping, the voltage source measurements shown in Figure 1a, ∆t is utilized much higher than the thermal and trapping time constants. For the pulse voltage source measurements initialized at time t 0 depicted in Figure 1b, the temperature T(X) ≈ T 0 is found along the active device area at t ≈ t 1 , that it is zero ∆V n at t > t 1 and a negligible ∆Q TE (X) results in ∆I T ≈ ∆I. Otherwise, ∆Q TE (X) is required to be incorporated into ∆I E as illustrated below.
shown in Figure 1a,b, respectively. The small parasitic capacitance, typical for GaN-based devices, and a short switching time of the stepping source in comparison with thermal and trapping time constants make it possible for ∆IT to be obtained as the difference between I acquired at t1+t ' and at t1+t in the case of a negligible QTE(X). To reach an equilibrium state during quasi-static stepping, the voltage source measurements shown in Figure 1a, t is utilized much higher than the thermal and trapping time constants. For the pulse voltage source measurements initialized at time t0 depicted in Figure 1b, the temperature T(X)  T0 is found along the active device area at ≈ , that it is zero Vn at > and a negligible QTE(X) results in IT  I. Otherwise, QTE(X) is required to be incorporated into IE as illustrated below.

Average Temperature Definition
To avoid thermal gradient calculations, the average temperature contribution dTA in the active device area XA is defined by the substitution of ( ) = ( ) + ( ) ( ) and the spatially independent thermal coefficient kT related to the operating point: To eliminate the ( ) spatial determination, the approximation, demonstrated by an infinite thermal conductance for which the power density of XA does not perform a function, is usually utilized to calculate average temperature TA with trapping centers thermally excited by the same dTA. Therefore the = ∭ ( ) as TA, Vn and t dependent are used in the following way: The deviation between (5) and (6) leads to a discrepancy in TA determination, especially for different heat flux distributions caused by power dissipation, ambient temperature and time variation. For a spatially independent kT(X), kQ(X) or kTT(X) in XA, (5) and (6) appear identical, resulting in = ( ) and subsequently dTA as the thermodynamic average temperature contribution in XA:

Average Temperature Definition
To avoid thermal gradient calculations, the average temperature contribution dT A in the active device area X A is defined by the substitution of k I T (X) = k T (X) + k Q (X)k TT (X) and the spatially independent thermal coefficient k T related to the operating point: To eliminate the k I T (X) spatial determination, the approximation, demonstrated by an infinite thermal conductance for which the power density of X A does not perform a function, is usually utilized to calculate average temperature T A with trapping centers thermally excited by the same dT A . Therefore the k T = X A k I T (X)dX as T A , V n and t dependent are used in the following way: The deviation between (5) and (6) leads to a discrepancy in T A determination, especially for different heat flux distributions caused by power dissipation, ambient temperature and time variation. For a spatially independent k T (X), k Q (X) or k TT (X) in X A , (5) and (6) appear identical, resulting in k T = k I T (X)X A and subsequently dT A as the thermodynamic average temperature contribution in X A : Electronics 2021, 10, 2738 4 of 12

Ambient Temperature Variation
The average temperature determination method depicted in Figure 2a is based on the resultant current I comparison with an isothermal device current I E at time t 1 after the measurement initialization at time t 0 , where the maximum I and I E should be reached at time t 0 '. The trapping effects must be included in I E as illustrated below. In spite of the zero thermal contribution X k I T (X)dT E (X)dX to I E , the variation of the isothermal temperature profile T E (X), together with a spatially dependent k I T (X), results in a thermodynamic average temperature deviation from the initial temperature at t 0 , caused by the difference between (5) and (6). Therefore, this method is found to be sufficient for devices with a relatively small active area or negligible spatial k I T (X) variation.

Trapping Effects Approximation in FET
We further consider the TA determination of the FET-neglecting parasitic gate, a its entire electric capacitance. Even a relative carrier velocity v change, and pinch-off ar formation are thought to have no impact on channel potential distribution along t channel [15,16].
The threshold voltage VTH shift is related to the time and temperature variation energy barrier height, free charge concentration along the conductive channel as well charge trapping, resulting in the additional virtual gate electrode. The gate voltage V drain voltage VDS and ambient temperature T0 variation causes dTA, with a direct imp on the v and VTH change. These variations result from the isothermal section dVT caused by an immediate band energy diagram and free charge concentration change. T isothermal section dVTHE, is a result of the trapping phenomena during the defined tim and the thermal section dVTHT originates from thermal carrier and trap center dens change.
A widely utilized FET approximation [15] in the case of stepping VDS and/or VGS a defined T0 is as follows: It is possible to acquire the isothermal transconductance gM0 and output conductan gD0 via immediate isothermal VDS and VGS responses, including / a / . The term dITV represents the thermal change caused by dVDS, dVGS and d and has a major impact on v, excluding dVTH. A substitution of = + and = + , as applied in (11), results in: A common way to obtain VTH is pulsed and/or quasi-static transfer I-V character tics utilization at defined T0 and VDS assuming VTH independent on VGS as well as an a proximation of isothermal and measured I-V characteristics pointing on the same V shift at T0 in the operating range. Trapping phenomena and voltage drop in t Two identical measurements at distinct ambient temperatures, such that T 01 ≈ T 0 and T 02 ≈ T 0 + ∆T * with a small temperature difference ∆T* result in the current I 1 and I 2 , temperature profiles T 1 (X) and T 2 (X), as depicted in Figure 2b, and exhibit the temper- The assumption of a low ∆t means that the following formula is applicable for quasi-static and pulsed operations: (8), utilized for the dI T comparison with ∆I T = X k I T (X)∆T(X)dX based on the comparison of difference and differential substitution dI T /∆I T = dT(X)/∆T(X), results in: As a result, a T A definition utilizing (6) and substitution X ≈ X A , dI T and ∆I * caused by ∆V n and ∆T 0 leading to dT A and ∆T A * , respectively, leads (9) to the following relationship: However, despite the zero I E thermal current, a non-zero ∆T E (X) variation results in a discrepancy between the definition of dT A and ∆T A * by (7) and the definition utilizing infinite thermal conductance of the device active area, on the other side. Nevertheless, the T A determination methods utilizing (10) are found to be sufficient for devices with a negligible spatial k I T (X) variation or a relatively small active area. Already known ∆T A * and ∆I E time dependence allows to obtain T A as the sum of dT A calculated in (10) in the quasi-static or pulsed operating regime. Temperature dependent thermal resistance and thermal capacity result in a ∆T A * deviation from ∆T 0 . Quasi-static state methods, utilizing the T 0 variation, allows for the calculation of dT A and ∆T A * [9,14].

Trapping Effects Approximation in FET
We further consider the T A determination of the FET-neglecting parasitic gate, and its entire electric capacitance. Even a relative carrier velocity v change, and pinch-off area formation are thought to have no impact on channel potential distribution along the channel [15,16].
The threshold voltage V TH shift is related to the time and temperature variation of energy barrier height, free charge concentration along the conductive channel as well as charge trapping, resulting in the additional virtual gate electrode. The gate voltage V GS , drain voltage V DS and ambient temperature T 0 variation causes dT A , with a direct impact on the v and V TH change. These variations result from the isothermal section dV THN , caused by an immediate band energy diagram and free charge concentration change. The isothermal section dV THE , is a result of the trapping phenomena during the defined time and the thermal section dV THT originates from thermal carrier and trap center density change.
A widely utilized FET approximation [15] in the case of stepping V DS and/or V GS at a defined T 0 is as follows: It is possible to acquire the isothermal transconductance g M0 and output conductance g D0 via immediate isothermal V DS and V GS responses, including dV THN /dV DS and dV THN /dV GS . The term dI TV represents the thermal change caused by dV DS , dV GS and dT 0 and has a major impact on v, excluding dV TH . A substitution of dI 0 = g M0 dV GS + g D0 dV DS and dI = dI E + dI T , as applied in (11), results in: A common way to obtain V TH is pulsed and/or quasi-static transfer I-V characteristics utilization at defined T 0 and V DS assuming V TH independent on V GS as well as an approximation of isothermal and measured I-V characteristics pointing on the same V TH shift at T 0 in the operating range. Trapping phenomena and voltage drop in the source-to-gate and drain-to-source area have a partial influence on the V TH determination especially for low applied V DS or non-linear V TH vs. V DS dependence. The following ways of trapping effects incorporation in T A calculation coming out of V TH determination from transfer I-V characteristics are explained.
In the case of the quasi-static state operation V TH shift, resulting in (dV THE + dV THN )/ dV DS caused by T 0 and V DS variation, can be simply obtained from quasi-static I-V characteristics. Transfer I-V characteristics, measured by short-pulsed V GS and V DS offering trap influence separation, allow to get dV THN /dV DS obtained from negative V TH shift caused by roll-off effect in short-channel FET [15,17]. Subsequently, the ratio dV THE /dV DS dependent on V DS and T 0 is acquired and utilized in (12), whereby dI 0 is acquired at the beginning of V DS and/or V GS step, a measured transconductance g M |g M − g M0 | is supposed. For a significant g M dV THE /dV DS temperature variation in comparison with dI T /dV DS an iteration process is required for T A determination.
For V DS and/or V GS pulse responses, depicted in Figure 1b, the pulsed transfer I-V characteristics are measured utilizing V GS and/or V DS quiescent biasing and/or voltage pulses. At T 0 and the defined time t 1 after the increase of constant amplitude V DS and the sweeping amplitude V GS, drain currents are acquired to extract the V TH as t 1 and T 0 functions. At the time interval ∆t, during the pulse, t 1 ) gives the opportunity to utilize ∆I E = −g M0 ∆V THE for both a small ∆t and ∆V THE corresponding to the virtual gate electrode potential shift, neglecting the g M0 time variation. The maximum resultant current I E and V TH , obtained immediately after V GS and/or V DS rising edges at t 0 , provides the opportunity to plot the I E time dependence at T 0 , depicted in Figure 2a: In the considerations above a thermal gradient along the active device area that effects the trap spatial localization is truncated. Isothermal trapping phenomena and a voltage drop in the source-to-gate and the drain-to-source area having a partial influence on V TH shift are neglected as well. Despite this, an appropriate analytical approximation of the I-V characteristics provides an opportunity to predict the trapping phenomena in particular devices. An advantage of the T 0 variation method during the device operation is that the calibration of for dI TV /dT A vs. T A , V DS and V GS with an additional trapping phenomena analysis is not required.

Short Time Response Current Utilization
Many of the experimental methods that are widely utilized for the T A acquisition of FET in a saturation regime are based on a zero isothermal drain current change dI E /dV DS at constant V GS . The requirement of zero dI E in (12) is satisfied for a gate length modulation or a leakage current increase compensated by the trapping phenomena in the saturation regime, resulting in dI E dI T . Long-channel FET excluding V DS such as V GS dependent charge trapping variation meets this condition therefore the methods to acquire T A in quasi-static operation coming out from temperature calibration of major electrical parameters [8,16] or ambient temperature variation [9,18] require standard DC measuring equipment. The dI E prediction at various ambient temperatures, using an analytical model or simulation software also makes such methods applicable for short-channel FET [17,18].
In general, the resultant current acquisition after a short period after the voltage step/pulse is required, to obtain the dI 0 . The method depicted in Figure 2a is simply applicable for devices exhibiting relatively short time responses t 0 '-t 0 , operating in the quasi-static and dynamic state as well providing the opportunity to obtain an isothermal trapping effects approximation. However a switching time of~10 −8 s is required for full load turning-on, which makes the experimental setup more expensive.

Structure Design and Experimental Setup
The investigated Al 0.25 Ga 0.75 N/GaN HEMT structure, including 14 nm Al 0.25 Ga 0.75 N/ 1.5 nm AlN/1700 nm GaN/75 nm thermal boundary resistance layer (TBR) heterostructure was grown by MOVPE on a 70 µm thick 4H-SiC substrate, containing the backside Au contact, which was soldered to 1 mm thick CuMo leadframe using a 60 µm thick AuSn solder. The top ohmic drain/source and gate contacts were created via standard Au-based metallization. A gated transmission line model (GTLM) HEMT with a width of w ≈ 100 µm, a gate with a length of d G ≈ 0.15 µm, asource to gate gap of length d GS ≈ 0.75 µm and the drain to gate gap of length d GS ≈ 1.5 µm was investigated [14]. The device is placed in an open package located on the Al thermal chuck and maintainedat a constant temperature.
A semiconductor parameter analyzer Agilent 4155C and controlled thermal chuck were utilized to acquire the output characteristics at zero gate-source voltage V GS and the drain-source voltage V DS varied from 0 V up to 20 V. The chuck temperature was set in the range of 25-185 • C to demonstrate methods based on ambient temperature and threshold voltage variation. The device trapping level was reset via white LED illumination for one minute between quasi-static measurements. The 3D model incorporating device geometry, layout and thicknesses of individual layers was created using the 3D thermal FEM simulations performed by Synopsys TCAD Sentaurus [12]. The material thermal conductivity and capacity values were obtained from the previous work and calibrated utilizing the measurements provided [19,20]. The constant ambient temperature boundary condition was set to the structure backside, assuming an ideal heat transfer between leadframe and heatsink. The structure's self-heating is simulated by three thermal contacts placed along 2DEG, between the drain and source, representing heat contribution from the drain to the source access region, under the gate electrode and the pinch-off region located at the drain side gate edge [19].

Average Channel Temperature Determination
The drain-source current I DS dependence on drain-source voltage V DS for gate-source voltage V GS = 0 V at varying ambient temperature T 0 in the range of 25-105 • C was acquired during the V DS step, for a period of period~1 s using the quasi-static operation as depicted in Figure 3. The maximum I DS obtained at the beginning of the extended V DS step ∆V DS ≈ 2 V, and subtracted by I DS value, that were acquired under quasi-static operation from the previous V DS step, results in dI 0 . Quasi-static and pulsed transfer I-V characteristics show soft g M and a g M0 decrease with rising V DS and T 0 as illustrated in Figure 4. In particular, the V TH and V THT were obtained from square rooted transfer I-V characteristics resulting in constant dV THE /dV DS for a defined T A . Therefore dV THE /dV DS ≈ (dV TH − dV THN )/dV DS is approximately dV THE /dV DS ≈ k THE (T A − T 00 ) + k TH00 , T 00 ≈ 25 • C, k THE ≈ 8.8·10 −6 K −1 and k TH00 ≈ 1.97·10 −3 for T A ( • C) in the saturation area. However, T A above T 0 ≈ 105 • C was reached, which results in g M dV THE /dV DS being linearly approximated, exhibiting variations of~8·10 −8• V/K in the range of 25-225 • C, corresponding to~10% of dI T /dV DS . Interpolated thermal and isothermal parts of dI DS /dV DS vs. V DS at T 0 ≈ 25 • C are depicted in Figure 5. Moreover, the dissipated power contribution dP * = V DS ∆I * , caused by dT 0 for low V DS negligible in comparison with dP = V DS dI DS + I DS dV DS caused by dV DS , results in the simplified formula for differential thermal resistance R A0 (T 0 ) calculation [14] utilizing (12): Electronics 2021, 10, x FOR PEER REVIEW 8 of 12        The linear approximation T A − T 0 ≈ R A0 P, utilized in the first g M dV THE iteration step in (15), leads to a formula resulting in R A0 (T 0 ) plot at different T 0 and V DS as shown in Figure 6: Increasing V DS results in different R A0 values at a defined T 0, which is partially caused by spatially distributed electrical parameters of the active device area such as the g M dV THE /dV DS variation. The approximation R A0 ≈ k RA (T 0 − T 00 ) + R 00 , T 00 ≈ 25 • C, k RA ≈ 0.2 W −1 , R 00 ≈ 57.0 K/W at the defined T 0 was utilized to calculate T A in a recurrent way [14] as illustrated in Figure 7. In [8] the major contribution of the thermal I DS section is assigned to the serial source area resistance increase, caused by self-heating in a saturation regime for AlGaN/GaN HEMT. The simulated average channel temperature of the source to the gate area is in acceptable agreement in comparison to the calculated T A . Increasing VDS results in different RA0 values at a defined T0, which is partially caused by spatially distributed electrical parameters of the active device area such as the / variation. The approximation ≈ ( − ) + , T00 ≈ 25 C, ≈ 0.2 W , ≈ 57.0 K/W at the defined T0 was utilized to calculate TA in a recurrent way [14] as illustrated in Figure 7. In [8] the major contribution of the thermal IDS section is assigned to the serial source area resistance increase, caused by self-heating in a saturation regime for AlGaN/GaN HEMT. The simulated average channel temperature of the source to the gate area is in acceptable agreement in comparison to the calculated TA.
For the TA investigation of HEMT in the pulse operation, VGS and VDS bias was set to zero, superimposed by a VDS= 20 V pulse of length ~1 s. In the case of non-zero biasing, the initial condition of zero power dissipation is required to be satisfied. The period of 5 s between voltage pulses was found sufficient because of the absence of the automated white LED illumination during the pulse breaks. The resultant current IDS acquired at T0 and delay t1 after the rising edge of constant amplitude VDS= 20 V and VGS amplitude sweeping from −4 V to −2 V at defined points, allowed us to plot the transfer I-V characteristics and to subsequently obtain the VTH dependent on t1 in the logarithmic scale in the range of 10 −7 -1 s, where the T0 step is set linearly in the range of 25-185 C. Experimentally acquired IDS in the range of 20-100 ns and 25-185 C for pulsed VDS= 20 V and zero VGS are depicted in Figure 8. Setting the VGS=−0.5 V allows us to obtain the supposed gM0 constant at the defined T0 due to a small deviation under isothermal conditions. Although in the theoretical section the maximum IDS obtained at t0 ≈ 60-90 ns is suggested as the initial resultant current IDS0 at T0, simulation results exhibit higher TA than T0 by 30-50 C at t0 which is caused by the rapid device self-heating. The real parasitic capacitance time constant and carrier transit time of the investigated device and measurement setup are the causes of this discrepancy. Linear extrapolation of IDS rising edge for t < t0 resulting in a linear dissipated power P increase, provides an opportunity to estimate IDS0 from / = ~ utilizing the dIT sum as the quadratic time dependence. This approximation is found to be sufficient, although further VDS and IDS time dependence investigations for t < t0 are recommended. The trapping time constants of at least one order higher than ~10 −7 s allow the calculation of the isothermal time dependence utilizing (14).
The intersection of the measured IDS time dependence and IE at defined T0 allows TA determination as depicted in Figures 7 and 8. The difference between the TA obtained by  (5) and (6), as well as in the electric parameters from the source to the gate area, influencing dIT and IE approximation.

Conclusions
The average temperature significance was underlined in the theoretical section to avoid spatially distributed device parameters acquisition. The particular methods, based For the T A investigation of HEMT in the pulse operation, V GS and V DS bias was set to zero, superimposed by a V DS = 20 V pulse of length~1 s. In the case of non-zero biasing, the initial condition of zero power dissipation is required to be satisfied. The period of~5 s between voltage pulses was found sufficient because of the absence of the automated white LED illumination during the pulse breaks. The resultant current I DS acquired at T 0 and delay t 1 after the rising edge of constant amplitude V DS = 20 V and V GS amplitude sweeping from −4 V to −2 V at defined points, allowed us to plot the transfer I-V characteristics and to subsequently obtain the V TH dependent on t 1 in the logarithmic scale in the range of 10 −7 -1 s, where the T 0 step is set linearly in the range of 25-185 • C. Experimentally acquired I DS in the range of 20-100 ns and 25-185 • C for pulsed V DS = 20 V and zero V GS are depicted in Figure 8. Setting the V GS =−0.5 V allows us to obtain the supposed g M0 constant at the defined T 0 due to a small deviation under isothermal conditions.

Conclusions
The average temperature significance was underlined in the theoretical section to avoid spatially distributed device parameters acquisition. The particular methods, based on an ambient temperature variation for a device under a quasi-static state and a device under pulse operation, were compared by taking the trapping process into account as a result of the FET threshold voltage shift that neglects electric capacitance. In the experimental section, the theoretical subtractions were adapted for the AlGaN/GaN HEMT channel temperature determination. The calculations were a result of the isothermal and Although in the theoretical section the maximum I DS obtained at t 0 ≈ 60-90 ns is suggested as the initial resultant current I DS0 at T 0 , simulation results exhibit higher T A than T 0 by 30-50 • C at t 0 which is caused by the rapid device self-heating. The real parasitic capacitance time constant and carrier transit time of the investigated device and measurement setup are the causes of this discrepancy. Linear extrapolation of I DS rising edge for t < t 0 resulting in a linear dissipated power P increase, provides an opportunity to estimate I DS0 from dI T /k T = dT A ∼ P utilizing the dI T sum as the quadratic time dependence. This approximation is found to be sufficient, although further V DS and I DS time dependence investigations for t < t 0 are recommended. The trapping time constants of at least one order higher than~10 −7 s allow the calculation of the isothermal time dependence utilizing (14).
The intersection of the measured I DS time dependence and I E at defined T 0 allows T A determination as depicted in Figures 7 and 8. The difference between the T A obtained by the quasi-static and the pulsed measurements at t 1~1 s can be explained by the partially compensated I DS during the rising time for the voltage pulse ∆V DS ≈ 20 V and the uncompensated I DS during the rising time at the voltage step ∆V DS ≈ 2 V, which were utilized in the quasi-static measurements. The difference of~20 • C (13%) between simulated and experimental T A values is assigned to the different heat-flux distributions, resulting in the deviation between (5) and (6), as well as in the electric parameters from the source to the gate area, influencing dI T and I E approximation.

Conclusions
The average temperature significance was underlined in the theoretical section to avoid spatially distributed device parameters acquisition. The particular methods, based on an ambient temperature variation for a device under a quasi-static state and a device under pulse operation, were compared by taking the trapping process into account as a result of the FET threshold voltage shift that neglects electric capacitance. In the experimental section, the theoretical subtractions were adapted for the AlGaN/GaN HEMT channel temperature determination. The calculations were a result of the isothermal and thermal current sections separation, by taking into account the threshold voltage shift caused by trapped and free carrier concentration, the band diagram variation in operating temperatures and the applied voltage. The calculated and simulated average channel temperature~160 • C of the source to the gate area for power dissipation~2 W exhibits a difference of~20 • C (13%). The considerations applied in the analytical model offer methodological consolidation for use in further research. Funding: This work received funding from the ECSEL JU under grant agreement No 783274, project 5G_GaN2. The JU receives support from the European Union's Horizon 2020 Research and Innovation Program and France, Germany, Slovakia, Netherlands, Sweden, Italy, Luxembourg, Ireland. This publication reflects only the author's view and the JU is not responsible for any use that may be made of the information it contains. The work was also supported by Grant VEGA 1/0733/20 through the Ministry of Education, Science, Research and Sport of Slovakia.
Institutional Review Board Statement: Not applicable.