Modeling of Average Current in Non-Ideal Buck and Synchronous Buck Converters for Low Power Application Modeling of Average Current in Non-Ideal Buck and Synchronous Buck Converters for Low Power Application

: In this paper, a comparative analysis of the average switch/inductor current between ideal and non-ideal buck and synchronous buck converters is performed and veriﬁed against a standard LTspice model. The mathematical modeling of the converters was performed using volt-sec and amp-sec balance equations and analyzed using MATLAB/Simulink. The transients in the output voltage and the inductor current were observed. The transfer function of the switch current to the duty cycle (G id ) in open loop conﬁguration for low-power converters operating in continuous conduction mode (CCM) was modeled using thestate space averaging (SSA) technique and analyzed using MATLAB/Simulink. Initially, using the volt-sec and amp-sec, balance equations for the converters were modeled. The switch current to duty ratio (G id ) was derived using the SSA technique and veriﬁed using standard average models available in LTspice software. Though the G id was derived using various methods in earlier works, the analyses of parameters such as low frequency gain, stability, resonant frequency and the location of poles and zeros were not presented. It was observed that the converters were stable, and the non-ideal converter showed smaller resonant frequency than the ideal converter due to the equivalent series resistances (ESR) of the inductor and the capacitor. The non-ideal converters showed higher stability than the ideal converters due to the placement of the poles closer to the s-plane. However, the G id of the non-ideal converters remained the same in the open loop conﬁguration. Abstract: In this paper, a comparative analysis of the average switch/inductor current between ideal and non-ideal buck and synchronous buck converters is performed and verified against a standard LTspice model. The mathematical modeling of the converters was performed using volt-sec and amp-sec balance equations and analyzed using MATLAB/Simulink. The transients in the output voltage and the inductor current were observed. The transfer function of the switch current to the duty cycle (G id ) in open loop configuration for low-power converters operating in continuous conduction mode (CCM) was modeled using thestate space averaging (SSA) technique and analyzed using MATLAB/Simulink. Initially, using the volt-sec and amp-sec, balance equations for the converters were modeled. The switch current to duty ratio (G id ) was derived using the SSA technique and verified using standard average models available in LTspice software. Though the G id was derived using various methods in earlier works, the analyses of parameters such as low frequency gain, stability, resonant frequency and the location of poles and zeros were not presented. It was observed that the converters were stable, and the non-ideal converter showed smaller resonant frequency than the ideal converter due to the equivalent series resistances (ESR) of the inductor and the capacitor. The non-ideal converters showed higher stability than the ideal converters due to the placement of the poles closer to the s-plane. However, the G id of the non-ideal converters remained the same in the open loop configuration.


Introduction
The average current control (ACC) of DC-DC converters plays a vital role in designing PFC (power factor correction) converters, DC-AC inverters, electric vehicle (EV) chargers, LED lighting, etc. The most popular control methods for maintaining the unity power factor for DC-DC converters are shown in Figure 1.

Introduction
The average current control (ACC) of DC-DC converters plays a vital role signing PFC (power factor correction) converters, DC-AC inverters, electric vehicl chargers, LED lighting, etc. The most popular control methods for maintaining the power factor for DC-DC converters are shown in Figure 1.  The current control of DC-DC converters consists of two categories, namely ACC and peak current mode (PCM) control. In ACC, variation in the perturbed inductor current with respect to the perturbed duty ratio is considered. Though ACC cannot provide instantaneous control, some of the advantages of ACC over PCM include (a) better noise immunity and (b)possible control for a wide range of applications. In the past, multiple attempts have been made in modeling the open loop transfer function of average current for different converters operating in CCM and discontinuous conduction mode (DCM) operations. The modeling approach for CPM (Current Programmed Mode) was clearly shown for buck and boost regulators using the generalized small signal model. The small signal modeling approach for the basic converters and the modeling approach of the ACC for an ideal boost converter was presented in [1][2][3].
Electric vehicle (EV) charging systems, power factor correction (PFC) circuits, LED drivers, power supplies for processors etc., are some of the applications of DC-DC converters. The various AC-DC and DC-DC converters used in EVs are shown in [4]. Zero voltage (ZV) and zero current (ZC) switched DC-DC converters are the most popular converters used in the EV industry. For the generation of high gain, a KY converter integrated with the boost converter is used as it provides low current ripple and high efficiency.
In the average current control, capturing the inductor or the switch current is extremely critical. One of the major applications of the ACC is power factor control [5]. In [6], a novel method for measuring the inductor current is proposed for digitally controlled synchronous buck converters based on switch node voltage. To estimate the inductor current, switch node voltage is measured using a digital comparator. The inductor average current and the current ripple contents are simultaneously estimated as having independent gains. The estimation of the current ripple was validated against the hysteretic current mode control ofthe synchronous buck converter. However, no information on the low frequency gain during the open loop configuration was discussed.
In order to study the dynamics of the converter, modeling and simulation are extremely important. Transient values obtained through modeling help in designing the critical elements such as the inductor and the capacitor [7]. This type of modeling provides an insight on steady-state and transient behaviors.
The DC-DC converters used for battery charging applications are Cuk and Single Ended Primary Converter (SEPIC). The functioning of such switched converters under CCM and DCM conditions was modeled using the LTspice software tool [8]. These switch models require less computation time and memory for estimating frequency responses such as the G id , G vd and G vg . The converters showed instability during the CCM operation. However, they showed high stability during DCM operation.
In [9], a synchronous buck converter operating in CCM was used as a battery charging application. A PID controller was implemented instead of a maximum power point tacking (MPPT) algorithm to observe the charging of a lead acid battery at various irradiance levels. Though simulations show that MPPT provides better results, the PID controller has faster charging and lower costs. In [10], the DCM analysis for the Cuk and SEPIC converter operating in DCM was carried out. It was shown that the converter was unstable for G vd operations in an open loop. Hence, during the closed loop operation the controller should (a) stabilize the system and (b) provide enough phase margin (PM) to achieve stability in closed loop configuration.
The modeling of an ideal and non-ideal buck converter operating in CCM was performed for an open loop configuration [11]. The output voltage and the inductor current were smaller in the non-ideal buck converter. The non-ideal buck converter showed a greater number of zeros than the ideal buck converter. However, the modeling and analysis of the synchronous buck converter were not discussed.
The modeling of the G id in open loop configuration for boost and synchronous boost converters is presented in [12]. It was shown that the G id for the non-ideal synchronous boost converter showed higher resonance than the non-ideal boost converter.
Frequency control techniques have been employed in DC-DC converters to keep the switching frequency constant, instead of a phase-locked loop (PLL) [13]. The objective of frequency response identification for DC-DC converters is to ensure high accuracy, flexible operation in open or closed loop modes, and the optimal performance of the converter [14]. In [15], the authors proposed a wide input voltage range DC-DC converter for auxiliary power supplies on solar power conversion circuits or railway vehicles, making use of the buck/boost and resonant circuits to realize this wide range. The authors in [16] designed a four-switch buck-boost (FSBB) converter with a wide input voltage range voltage conversion, catering to variable-speed energy storage systems with AC inputs and DC outputs. The switching average model is used to establish the small signal model of a non-ideal FSBB converter in all working conditions. A digital control strategy [17] is modeled and implemented for a multi-leg interleaved DC-DC buck converter for electrical vehicle (EV) charging based on a discrete averaged model. The control system objective is the current flow regulation in each leg of the converter. Point-of-load applications require a lower-level distribution voltage. However, the control is not easy, which is why there is a need to choose the right fixed frequency for the buck regulator control [18,19]. Moreover, the control loop compensation [20,21] cannot be overlooked, and the impact of the phase margin is significant. The crossover frequency affects the output impedance. In some cases [22], small signal averaging for variable switching frequency DC-DC converters is derived by separately considering the on-time and the off-time of the switching period. This is used to ensure very good voltage regulation and optimal dynamic performance. The converters used in EV industry and cyber security are shown in [23][24][25][26] and closed loop control using classical controllers is shown in [27] • The existing works featured on steady-state and transient performance analysis of the DC-DC ideal and non-ideal converters for low-power application based on the specifications shown in [11].

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The G id for a current loop is considered. However, the outer voltage loop is not taken into account.

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The G id of a non-ideal buck converter was compared with a non-ideal synchronous buck converter. Sensitivity analysis of the G id was carried out by analyzing the bode plots for varying ESR.

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The modeling of the converters was presented considering all the non-idealities such as the switch and diode resistances and ESRs of inductor and capacitor. • However, very few works have focused on the mathematical modeling of the average current control strategy for the same.
In this paper, • The average current model for ideal and non-ideal buck and synchronous buck converters is modeled using the SSA technique.

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The emphasis is on modeling the G id and observations are made on low frequency gain, crossover frequency, resonant frequency, location of poles and zeros, and gain and phase margins.

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The objective of the work is to aid the understanding and significance of mathematical modeling and the effect of the G id on this proposed strategy and its significance in stability and control.
The paper is organized as follows: Section 1 provides the motivation and background of the proposed work. Sections 2 and 3 establish the mathematical foundation of the average current control strategy for the non-ideal buck and the non-ideal synchronous buck converter. Section 4 provides the specifications of the converter. Section 5 shows the mathematical modeling of the converters. Section 6 shows the analyses of the results obtained for the ACC in open-loop mode for both converters. Section 7 provides the validation of the same in the LTspice platform followed by the conclusion and future scope. Figure 2 shows the block diagram representation of the ACC in an ideal buck converter whereî L andd represent perturbed indictor current and duty cycle. The gate driver supplies the gate pulses to control the switching of MOSFET.

Average Current Modeling in Non-Ideal Buck Converter
verters. Section VII provides the validation of the same in the LTspice platform fo by the conclusion and future scope. Figure 2 shows the block diagram representation of the ACC in an ideal bu verter where iL and d̂ represent perturbed indictor current and duty cycle. The gat supplies the gate pulses to control the switching of MOSFET.   Switch closed condition,

Average Current Modeling in Non-Ideal Buck Converter
The state space representation is given by (6) and (7),  verters. Section VII provides the validation of the same in the LTspice platform f by the conclusion and future scope.    Switch closed condition,

of 16
Representing (1) and (2) in the form of (3) and (4), The output considered is the inductor current i L. Hence, where Switch opened condition, Reducing it to the form shown in (6) and (7), where where   Switch closed condition,

Average Current Modeling in Non-Ideal Synchronous Buck Converter
Switch opened condition, Electronics 2021, 10, 2672 Table 1 shows the specifications of the converters.

Mathematical Modeling of the Converters
The mathematical model can be obtained using the volt-sec and amp-sec balance equations, as shown in [7]. Figure 5 shows the results of mathematical modeling built and analyzed using Simulink for a non-ideal buck converter using appropriate step size and solver. As seen from Figure 5, the initial transient in output voltage and inductor current are 18 V and 3.6 A. Hence, while designing the capacitor and inductor, these values play a vital role. Equations (44) and (45) were used for modeling the converter.
Electronics 2021, 10, 2672 The modeling of the non-ideal synchronous buck converter is performed by making Vd = 0 and replacing Rd with Rsw2. It is observed that the duty cycle of the synchronous converter is slightly smaller than that of the buck converter. This is mainly due to the lesser conduction loss in the MOSFET. Figure 6 shows the bode plot of the Gid for ideal and non-ideal buck converters operating in CCM. The plots were obtained using MATLAB software. It is observed that the ideal and the non-ideal converters are stable with the phase margin (PM) equal to 90.2° and 91.9°. It is observed that the ideal converter showed higher resonant frequency than the non-ideal converter. This is due to the presence of the ESRs of inductor and capacitor. The modeling of the non-ideal synchronous buck converter is performed by making V d = 0 and replacing R d with R sw2. It is observed that the duty cycle of the synchronous converter is slightly smaller than that of the buck converter. This is mainly due to the lesser conduction loss in the MOSFET. Figure 6 shows the bode plot of the G id for ideal and non-ideal buck converters operating in CCM. The plots were obtained using MATLAB software. It is observed that the ideal and the non-ideal converters are stable with the phase margin (PM) equal to 90.2 • and 91.9 • . It is observed that the ideal converter showed higher resonant frequency than the non-ideal converter. This is due to the presence of the ESRs of inductor and capacitor. Figure 7 shows the bode plot of the converters when R c = R L = 0. It is observed that the resonant frequency of the converters matched.

Results of ACC in Open Loop Configuration
However, the non-ideal converter showed higher stability, which is due to the placement of poles closer to the left-hand side (LHS) of the s-plane. This is evident from the root locus plot shown in Figure 8. Equations (46) and (47) show the transfer functions of the G id for ideal and non-ideal buck converters.
G id = 15162(s + 1054) s 2 + 1518s + 1.074 * 10 7 (47) Figure 9 shows the bode plot of the G id for ideal and non-ideal synchronous buck converters. It is observed that the ideal and the non-ideal converters are stable with the phase margin (PM) equal to 90.2 • and 92 • . As observed in Figure 7, the ideal converter showed higher resonant frequency than the non-ideal converter. This is due to the presence of ESRs in the inductor and the capacitor. Figure 10 shows the bode plot of the converters Electronics 2021, 10, 2672 9 of 16 when R c = R L = 0. Figure 11 shows the root locus of the converters. Equations (48) and (49) show the G id for ideal and non-ideal synchronous buck converters.
G id = 14545(s + 1082) s 2 + 1082s + 1.082 * 10 7 (48) Electronics 2021, 10, x FOR PEER REVIEW 10 of 18 Figure 7 shows the bode plot of the converters when Rc = RL = 0. It is observed that the resonant frequency of the converters matched. However, the non-ideal converter showed higher stability, which is due to the placement of poles closer to the left-hand side (LHS) of the s-plane. This is evident from the root locus plot shown in Figure 8. Equations (46) and (47) show the transfer functions of the Gid for ideal and non-ideal buck converters.     Figure 9 shows the bode plot of the Gid for ideal and non-ideal synchronous buck converters. It is observed that the ideal and the non-ideal converters are stable with the phase margin (PM) equal to 90.2° and 92°. As observed in Figure 7, the ideal converter showed higher resonant frequency than the non-ideal converter. This is due to the presence of ESRs in the inductor and the capacitor. Figure 10 shows the bode plot of the converters when Rc = RL = 0. Figure 11 shows the root locus of the converters. Equations (48) and (49) show the Gid for ideal and non-ideal synchronous buck converters.     The bode plot of the Gid is analyzed for non-ideal buck and synchronous buck converters and is shown in Figure 12. The phase margins for the converters were 91.9° and 92°, respectively. It is observed from the frequency response of the converters that there is no change in the characteristics of the Gid. Hence, the placement of poles and zeros also remains the same. This is evident from Figure 13. The bode plot of the G id is analyzed for non-ideal buck and synchronous buck converters and is shown in Figure 12. The phase margins for the converters were 91.9 • and 92 • , respectively. It is observed from the frequency response of the converters that there is no change in the characteristics of the G id . Hence, the placement of poles and zeros also remains the same. This is evident from Figure 13.
The bode plot of the Gid is analyzed for non-ideal buck and synchronous buck converters and is shown in Figure 12. The phase margins for the converters were 91.9° and 92°, respectively. It is observed from the frequency response of the converters that there is no change in the characteristics of the Gid. Hence, the placement of poles and zeros also remains the same. This is evident from Figure 13.

Validation Using LTspice
The Gid derived using SSA was verified using standard switch models provided in the LTspice software tool. Figure 14 shows the average model of the non-ideal buck converter; the CCM2 library model was used for validation [16]. Figure 15 shows the frequency response of the Gid of the practical buck converter. It is observed that the low frequency gain, resonant frequency, and the cut-off frequency match with Figure 6.

Validation Using LTspice
The G id derived using SSA was verified using standard switch models provided in the LTspice software tool. Figure 14 shows the average model of the non-ideal buck converter; the CCM2 library model was used for validation [16]. Figure 15 shows the frequency response of the G id of the practical buck converter. It is observed that the low frequency gain, resonant frequency, and the cut-off frequency match with Figure 6.

Validation Using LTspice
The Gid derived using SSA was verified using standard switch models provided in the LTspice software tool. Figure 14 shows the average model of the non-ideal buck converter; the CCM2 library model was used for validation [16]. Figure 15 shows the frequency response of the Gid of the practical buck converter. It is observed that the low frequency gain, resonant frequency, and the cut-off frequency match with Figure 6.   Figure 16 shows the bode plot of the non-ideal synchronous buck converter obtained using the average model. This perfectly matches with Figure 12.

Conclusions
Low-power DC-DC converters are mainly used in mobile chargers and electric vehicle applications. In such converters, the voltage and current ripples are precise. In this paper: • ACC modeling for ideal and non-ideal buck and synchronous buck converters operating in CCM is carried out from basic equations of volt-sec and amp-second balance equations for a single current loop. • The converters were initially modeled using volt-sec and amp-sec balance equations. Using MATLAB/Simulink software, the mathematical model was analyzed and the transients in output voltage and inductor current were clearly seen. • Later, using the state space averaging technique, the average current transfer function Gid was derived for the ideal and non-ideal converters. Figure 16. Frequency response of G id for the practical synchronous buck converter using LTspice.

Conclusions
Low-power DC-DC converters are mainly used in mobile chargers and electric vehicle applications. In such converters, the voltage and current ripples are precise. In this paper: • ACC modeling for ideal and non-ideal buck and synchronous buck converters operating in CCM is carried out from basic equations of volt-sec and amp-second balance equations for a single current loop.

•
The converters were initially modeled using volt-sec and amp-sec balance equations. Using MATLAB/Simulink software, the mathematical model was analyzed and the transients in output voltage and inductor current were clearly seen. • Later, using the state space averaging technique, the average current transfer function Gid was derived for the ideal and non-ideal converters.
• The ideal and non-ideal converters were highly stable. However, the ideal buck converter showed higher resonant frequency than the non-ideal converter. This is due to the presence of ESRs in the inductor and the capacitor. A similar phenomenon was observed in ideal and non-synchronous converters.

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The derived transfer function was validated against standard switch models using the LTspice software. The plots show a perfect match between the derived transfer function and the actual switch model.

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The ACC modeling with closed loop control is to be carried out for different converter CCM/DCM configurations with inner current and outer voltage loops, and the effect of the capacitor ESR in the closed loop configuration is to be analyzed. The input current and the voltage can be controlled in order to achieve a power factor close to unity.