A High Bandwidth-Power Efficiency, Low THD2,3 Driver Amplifier with Dual-Loop Active Frequency Compensation for High-Speed Applications

This paper presents a driver amplifier with high bandwidth-power efficiency, high capacitor-driving capacity, and low total harmonic distortion (THD). One complementary differential pair composed of self-cascode transistors is incorporated to obtain a full input voltage swing. Flipped voltage follower (FVF) buffers are applied as second stage to drive the last class-AB output stage. Moreover, a dual-loop active-feedback frequency compensation (DLAFC) is presented, which can stabilize the proposed multistage amplifier and keep the dominant pole on high frequency to obtain high-frequency total harmonic distortion (THD) suppression. To achieve a low-frequency phase margin protection (PMP), one left half-plane (LHP) zero is introduced to compensate for the nondominant pole caused by the load capacitor. Meanwhile, two high-frequency LHP zeros are injected to achieve high-frequency phase margin boosting (PMB) and reduce the amplifier’s settling time and integration area. This proposed amplifier is implemented in a standard DBH 0.18 μm 5 V CMOS process, and it achieves over 115-dB DC gain, 150–300 MHz GBW under 0–100 p load capacitors, ultra-high THD2,3 suppression ranges from 100 kHz to 10 MHz under 1–2 V output swing, and over 250 V/μs average slew rate, by only dissipating 12.5 mW at 5 V power supply.


Introduction
Driving amplifiers with high speed, low distortion, and strong capacitive driving ability are widely used in many industrial and measurement applications, such as high resolution (>16-bit) analog-to-digital converters (ADCs) [1][2][3][4][5], liquid crystal display (LCD) [6][7][8][9][10][11], etc. In high-resolution ADCs, the challenge is that the driver amplifiers should be able to drive the sampling capacitors with a wide range of capacitance while maintaining the distortion and noise levels lower than those of the ADCs. Driving amplifiers also determine the speed, resolution, voltage swing, and power dissipation of the LCD drivers [7][8][9][10]. LCD panels on multimedia products have become larger with higher definition, and their color quality requires more accuracy. With the advancement of liquid crystal display (LCD), there is a large demand for developing driving amplifiers in high-resolution and high color-depth driver ICs [6][7][8][9][10][11].
Multistage amplifier design has proven to be a very effective approach in driver amplifier design. As known, multistage amplifiers can be very power-efficient in driving a large capacitive load and generally achieve a high bandwidth compared with singlestage amplifiers [12,13]. The common challenge of multistage amplifiers is to achieve stability under a wide range of load and high power-bandwidth efficiency. A three-stage amplifier has at least three high-impedance nodes; therefore, each will contribute a pole in the frequency domain. Without a dedicated frequency compensation scheme, these poles will be located at low frequency, leading to stability problems. The simple polesplitting effect can help amplifiers achieve stability by shrinking the dominant pole to the lower frequency; however, it will reduce the amplifier's bandwidth. In recent years, various frequency compensation techniques have been developed to ensure system stability, such as damping-factor-control frequency compensation (DFCFC) [12], active-feedback frequency-compensation (AFFC) [13], and nested/reversed Miller compensation (NMC, RNMC) [14,15]. Most of these structures are derived from the nested Miller compensation (NMC). The major challenge of NMC is to maintain the balance between the complex-pole frequency and the quality factor Q. The major contribution of the proposed DLAFC is to optimize the complex conjugate poles by injecting two left half-plane (LHP) zeros before the complex-pole frequency. Meanwhile, one extra LHP zero is generated to compensate for the negative phase shift caused by the nondominant pole, which improves the phase margin protection. Finally, the proposed amplifier will result in high gain-bandwidth products (GBW), high total harmonic distortion (THD) suppression, and fast settling time. This paper is organized as follows. Section 2 will give a detailed analysis of architecture selection and the proposed frequency compensation technique for the proposed amplifier. In Section 3, the simulations based on the proposed design and the comparison table of state-of-art will be presented to validate the proposed design principles. In Section 4, the conclusion is drawn.

Zinput Stage and Class-AB Output Stage
The circuit's implementation, shown in Figure 1, is proposed to prove the theoretical analysis and proposed amplifier design strategy. In this design, a complementary CMOS input stage is adopted for rail-rail common-mode level. As Figure 2a shows, the input stage consists of an nMOS differential pair and a pMOS differential pair in parallel. Due to the input voltage swing limitations, a traditional differential pair is not capable of processing signals with rail-to-rail common-mode levels. Each differential pair in the complementary stage can keep operating even if the input common-mode voltage is close to the positive (negative) power supply rail. When the input common-mode voltage is in the mid-supply range, both pairs are active. Therefore, no matter where the input common-mode voltage is between the two supply rails, the input stage will contribute transconductance (gmp+gmn, as shown in Figure 2b). It is worth mentioning that the first output stage uses a triple cascode to achieve high DC gain rather than a regulated loop for gain boosting because the regulated loop will introduce more extra poles within the bandwidth, which will create extra unnecessary difficulty and limitation on frequency compensation.
To further increase the input stage output impedance, the composite cascode structures, also referred to as the self-cascode structure, are applied to replace normal NMOS and PMOS transistors in the differential pairs. As shown in Figure 2c, two transistors M1 and M2 are stacked while their gates are connected. The ratio of channel width and length (W/L) of the transistor M1 is set larger than M2's; consequently, M1 will work in saturation region while M2 operates in triode region since the drain-source voltage of M1 in Figure 2b, V S2 -V S , is smaller than its overdrive voltage. Therefore, the output resistance of the self-cascode transistors can be calculated as: wherein g m2 and r o2 are the transconductance and drain-source resistance of M2, respectively, r o1 is M1's drain-source resistance. Since M1 is in the saturation region while M2 is in the triode region, if the body effect of M2 is ignored, we can get that: wherein β 1 and β 2 are the channel parameters of M1 and M2, respectively, V th is the threshold voltage of the transistors. From (2), we can calculate M1's transconductance and M2's drain-source resistance respectively, by:  The rail-to-rail CMOS input stage with nMOS and pMOS differential pairs in parallel is adopted as the input stage: (a) Schematic and (b) the transconductance versus input common-mode range and (c) self-cascode input transistors. Therefore, we can get that: wherein (W/L) 2 and (W/L) 1 are the channel width and length ratios of M2 and M1, respectively. The output equivalent resistance of the self-cascode transistors can be rewritten as: As shown in Equation (5), the output resistance of self-cascode transistors can be increased by choosing a large W/L for M2 or a small W/L for M1.

The Flipped Voltage Follower (FVF) Buffer
The general purpose of the driver amplifier is to buffer output that follows the characteristics of the input signal under a large load while maintaining high THD suppression and low power consumption. The class-A or class-B output stage is not a viable option due to low power efficiency, output swing or high distortion. The push-pull class-AB output stage is a good alternative often used as an output stage in CMOS buffer amplifiers. The push-pull stage consists of a pair of complementary common-source transistors, allowing the rail-to-rail output voltage swing. The gates of the two output transistors are normally driven by two in-phase ac signals separated by a dc voltage.
The last class-AB stage should be constructed with large transistors to supply large current. Among many existing topologies, flipped voltage follower (FVF)-based buffers are an attractive topological choice to drive the output class-AB stage. The main advantage of the FVF is the reduced output resistance due to shunt feedback connection, which is the key for obtaining fast transient response and minimal area requirements for implementing amplifiers for on-chip applications. The schematic of a PMOS version of FVF is shown in Figure 3a, which consists of PMOS input transistor M 1 , shunt feedback transistor M 2 and bias-current-source transistor M 0 .  Figure 3b illustrates the equivalent small-signal model of FVF. According to the smallsignal model, the output resistance of FVF buffer can be calculated as: wherein g m1 , r o1 are M1's transconductance and output resistance respectively, g m2 , r o2 are M2's transconductance and output resistance, respectively, and r o0 is M0's output resistance.
It is reasonable to assume that g m1 r o1 1, g m2 r o0 1 Therefore, Equation (6) can be simplified to: r o1 r o0 r o0 +r o1 (7) As shown by Equation (7), the output resistance of FVF can be greatly reduced by g m1 (r o1 ||r o0 ) . Figure 4 shows the equivalent small signal model of the adopted DLAFC in this work. It consists of the two in-parallel signal paths (indicated by the blue dotted lines in Figure 4) and three active feedback paths (indicated by the red dotted lines, namely PMP and PMB). The amplifier's DC gain is dominated by the first input stage and the last output class-AB stage to achieve over 115 dB (refer to Figure 1). Therefore, the dominant pole ω don occurred at the first stage while the nondominant pole ω non−don contributed in the last output stage because of the large capacitance load. The most important issue in driver amplifier is to maintain high bandwidth and high DC gain, which can enhance the amplifier settling behavior and suppress THD, respectively. However, due to the class-AB output stage, that requires a large transistor size and large supply current for high slew rate and large output swing; it is very hard to move the nondominant location. Hence it is necessary to design a low-frequency LHP zero (z 1 = −gm a2 /C a2 ) to compensate for the phase loss caused by the nondominant pole and achieve phase margin protection (PMP). Meanwhile, to achieve stability by mitigating the effect from the complex conjugate poles, two LHP zeros (z 2−3 ), one from R m -C m pair and the other one from PMB (z 3 = −gm a1 /(C a1 + C B )), are generated to compensate the phase margin. It is important to realize that to protect the THD suppression and achieve high-speed operation, the proposed DLAFC structure must prevent any direct connection between the Miller capacitor from the output gain stage to the first input gain stage. Therefore, the proposed DLAFC does not suffer from the bandwidth reduction caused by the Miller capacitive loading overhead at the amplifier output. The amplifier uses the proposed DLAFC compensation network with the following key characteristic components:

The Proposed Dual-Loop Active Frequency Compensation
(1) Capacitor C c is connected in the current buffer configuration in the inner loop, where its advantage is to shift the dominant pole location without any pole-splitting effect to protect the amplifier from PVT variations. (2) Phase Margin Boosting (PMB) is introduced to achieve nondominant pole compensation by creating 2 low-frequency LHP zeros from the PMB feedback path. A one-pair of Miller capacitor C m with nulling resistor R m in parallel with G M,FVF1 is introduced to add 1-pole-zero pair to the inner loop effectively. The extra pole ω extra (generated by capacitor C m with nulling resistor R m in the second stage) will not influence the amplifier stability because the AFFC network is connected between the FVF buffer stages and the class-AB output stage in cascode frequency compensation to generate pole splitting and to push this extra pole ω extra into high-frequency pole ω HF (Refer to the pole-zero placement relationship before and after compensation analyzed in the following sections along with systematic complete calculations ). AFFC topology is adopted to reduce the value of C c and push the dominant pole to higher frequency to obtain better THD+N suppression in higher frequency. The primary function of this RC pair is to create an extra zero along with the AFFC zero effectively: z 3 = −gm a1 /(C a1 + C B ) to achieve phase margin boosting (PMB) against the complex poles. (3) Due to the phase margin loss from the second nondominant pole, it is necessary to introduce an extra LHP zero to achieve low-frequency phase margin protection (PMP). This is done through the PMP path, which effectively adds one more LHP zero (z 1 = −gm a2 /C a2 ) to protect the phase margin.
The proposed DLAFC frequency compensation technique is capable of maintaining high gain (over 115 dB) at the high frequency when the amplifier is in a closed-loop configuration. To acquire the frequency property of the small-signal model in Figure 4, the analysis will start from the transfer function of the proposed three-stage amplifier, which can be characterized as: The transfer function is derived under the assumptions of the parasitical capacitances C 1 , C 2 C 3 shown in Figure 4 that are much smaller than the frequency-compensation capacitances C c , C m , and the capacitance load C L .
As previously mentioned, the extra pole ω extra influence (generated by capacitor C m with nulling resistor R m in the second stage) along with the proposed LHP zero z 2 will be analyzed below with the model shown in Figure 5 before the complete analysis of the proposed DLAFC.  Based on the equivalent small-signal model shown in Figure 5, the following Equations can be derived: From Equation (9), the transfer function of the FVF buffer can be expressed as: v out v in = g m1 r o1 g m2 r o2 r o0 g m1 r o1 g m2 r o2 r o0 + r o1 + r o0 1 + sC m R m + r o1 +r o0 g m2 g m1 r o1 r o0 1 + sC m R m + r o1 +r o0 g m1 r o1 g m2 r o0 + r o1 +r o0 r o2 Therefore, the compensation zero z 2 and the extra pole ω extra can be calculated by: ω extra = − 1 C m R m + r o1 +r o0 g m1 r o1 g m2 r o0 + r o1 +r o0 r o2 (12) It is obvious that the z 2 and ω extra are inevitably generated, and the ω extra must be removed in order to make the frequency compensation effective, which allows the circuit only to take advantage of the effect of z 2 rather than being influenced by ω extra . Therefore, the cascode compensation by AFFC is used to generate pole-splitting effect to eliminate pole ω extra .
Secondly, it is necessary to analyze the frequency property of the AFFC cascade compensation shown in Figure 6. From the figure, we can obtain the following Equations: sC a1 +g ma1 +g ma1 +sC B v OUT (13) wherein v P is the output voltage of buffer FVF1 while v FB1 is the voltage feedback from the amplifier's output voltage v OUT through the AFFC capacitaor C a1 .R L , C L are the amplifier's output resistance load and capacitance load, respectively. After combination and simplification of Equations in (13), we get: Substituting (14) in (13), we can get the transfer function of AFFC in the form of: wherein the denominator of (15) is expressed as: HD(s) = s 3 C a1 g ma1 C L R L C 2 r FVF1 + s 2 C a1 g ma1 C 2 r FVF1 1 + C L C a1 + 1 R L g ma1 + C L R L C 2 r FVF1 + sC a1 r FVF1 R L g mP +s(C L + C a1 )R L + s C a1 g ma1 + sC 2 r FVF1 + 1 It is obvious that the AFFC can generate one low-frequency dominant LHP zero expressed as: Nondominant pole ω non−don and high-frequency pole ω HF by pole-splitting effect from AFFC shown in Figure 6 can be calculated from the derivations of the cascode frequency compensation as follows: wherein g m3 is the transconductance of the last class-AB stage, which equals g mp + g mn , C 2 is the total parasitical capacitance on FVF buffers' output. As implied by Equation (19), ω HF can be in the GHz range when g m3 is sufficiently large, and becomes a very highfrequency pole. Finally, the frequency property of the entire circuit can be summarized in Table 1.

DC gain
High-frequency LHP zero 1 High-frequency LHP zero 2 The most advantage of the proposed technique compared with conventional simple Miller compensation (SMC), cascode frequency compensation (CFC), or nested/reversed nested Miller (NMC, RNMC) compensation techniques is that the proposed DLAFC is using the pole-splitting effect in an unconventional way between the second and third stage to only push the inevitable extra pole generated from the R m -C m pair outside the gain-bandwidth product (GBW). Thanks to the positive phase shift provided by z 2−3 , the stability of the DLAFC amplifier can still be achieved even when the GBW is set to be closer to p 1−2 . Therefore, the GBW of the DLAFC amplifier can be improved by using the proposed pole-zero placement strategy, as shown in Figure 7, instead of using the third-order Butterworth response. As shown in Figure 8, the importance of the locations of the nondominant complex pole pairs gives rise to minor magnitude peaking. However, the effect on phase margin is mitigated by the presence of z 2 and z 3 .  The designed complex conjugate poles implied by Equation (8) are given by: And their phase-shifted amount can be calculated by: wherein ω cpi is the frequency of the designed complex conjugate poles.
The reason for designing the Q-value according to Equations (20)-(22) can be understood using Figure 8, which shows that the effect of a pair of nondominant complex poles can cause different Q-values on the voltage gain and phase shift of a generic three-stage amplifier. To avoid gain overshooting and dramatic phase reduction, as shown in Figure 8, Q-value of complex poles must be ensured to be smaller than 1. Therefore, the feature of having an additional positive phase shift due to two LHP zeros z 2−3 creates an opportunity to achieve stability by using an advanced pole-zero placement strategy. Due to the presence of two separate LHP zeros, the positive phase shift generated by z 2−3 will cancel out the amount of the negative phase shift caused by the nondominant complex poles p 1−2 . The stability of the DLAFC amplifier is determined by its phase margin (PM) that is given as: wherein ω p2 is the nondominant pole and ω zi is the frequency of the i-th zero.

Simulation Results and Discussions
To verify the functionality of the proposed DLAFC-based scheme driver amplifier design, the proposed prototype is implemented in the 0.18 µm DBH 5V technology process. The amplifier is expecting to drive a maximum load of less than 60 pF, including the probe capacitance. The first dominant pole is pushed around 5 KHz to contain enough loop gain to suppress THD. Figure 9 shows the frequency responses of the proposed amplifier with the loading of 10 pF, and the poles and zeros from the previous analysis are labeled on the plot. It shows that under the proposed delicate pole-zero placement, the phase margin of a multistage amplifier can be optimized to approximately equal 90 o; the nominal GBW is around 250 MHz.  Figure 10 shows that the proposed diver amplifier can achieve a robust operation under a wide range of load capacitance. The simulated results for the proposed DLAFC amplifier are further verified with different capacitive loads to prove the robustness of the proposed design. Figures 11 and 12 show the proposed amplifier can achieve slew rate SR+-greater than 250 V/µs under small voltage swing and large voltage swing. The SR test can also be a reasonable verification of the robustness of the proposed frequency compensation technique in this work.        Figures 16 and 17 show the excellent performance of the input-referred noise, PSRR, and CMRR, output impedance under all different process corners to demonstrate the proposed circuits can maintain high immunity to power-supply noise and common-mode noise, and maintain a low noise floor under high-frequency operation. The ultra-low output impedance (less than 10 ohms) within 100 MHz shows the proposed amplifier can have a very powerful driving capacity without suffering from signal distortion. Overall, it is clear that the proposed design is robust in terms of the circuit's architecture, THD suppression, and frequency compensation scheme.  The performance of this work is summarized in Table 2 and is compared with the state-of-art. As shown in the table, the proposed design can achieve a very high DC gain, a high GBW, a small input offset, and high THD suppressions simultaneously while its power consumption is relatively low compared with others, which proves that our design offers a very good bandwidth-power efficiency.

Conclusions
In this paper, a DLAFC-based driver amplifier is presented. The theoretical analysis and simulation results show good agreement regarding excellent DC gain, GBW, speed, input-referred noise and THD, which is suitable for high-speed applications. Moreover, the proposed amplifier is proven stable in most extreme PVT variations to validate the design robustness. The proposed amplifier has competitive performance compared with state-of-art amplifiers used as products.

Conflicts of Interest:
The authors declare no conflict of interest.