A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

: In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 µ A, sub-threshold swing of 69 mV/dec, and ON / OFF current ratio of 1.28 × 10 11 . Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the inﬂuence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications. and so on. Another index demonstrating an excellent gate controllability in the proposed transistor is the low drain induced barrier lowering (DIBL), which is less than 20 mV between cases of V DS = 0.1 V and 2 V.


Introduction
Given the ever-increasing requirement for high-density and high-performance integrated circuits (IC), semiconductor processes has evolved along with Moore's law constantly for more than half a century [1]. However, with the process approaching the physical limit of the material, various undesirable problems, such as short channel effect emerge in planar MOSFETs, and thereby hinder the IC development [2]. In order to address with these issues, monolithic three-dimensional (M3D) IC, which possesses excellent performance and power efficiency, has been proposed and is now rapidly developing [3]. M3D ICs are implemented in silicon-on-insulator (SOI) technology, and through-oxide vias (TOV) are patterned through the buried oxide (BOX) to offer electrical connectivity between tiers [4,5].
In addition to the improvements in integration technology, significant efforts have been devoted to the optimization of transistors. In the past several years, vertical MOSFETs have attracted much attention and been extensively studied, due to their advantages in occupying small areas and electrostatic control ability [6,7]. In [8], a Si nanowire-based tunneling field-effect transistor (TFET), with vertical gate-all-around (GAA) structure was proposed. A very low room-temperature (RT) subthreshold swing (SS) was achieved. The low SS of TFET arises from the silicidation of the nanowire, which can activate the sourceside dopants to achieve a steep dopant profile. However, the diameter nonuniformity along the nanowire length results in asymmetry in the device's subthreshold characteristic. To solve this issue, an improved InGaAs dry etch technology was reported in [9], and the subthreshold asymmetry improved to some extent. Based on conventional FinFET, Zheng et al. reported on an improved device architecture, which was named as iFinFET [10]. It was demonstrated that iFinFET exhibits better electrostatic integrity and scalability than FinFET, as well as less gate capacitance than GAA FET. In [11], a vertical InAs MOFET was fabricated on Si substrate for low power and high frequency applications, but its large parasitic capacitance, induced by metal overlap, limits its performance. Some impressive high power vertical transistors were reported. In [12], a vertical power MOSFET with high-κ gate insulator and hexagonal structure was designed, and exhibited a low onresistance but slow response speed. In [13], a large-area in-situ oxide, GaN interlayer-based vertical trench MOSFET was presented, with extensive potential for its application in power electronics.
Considering their various advantages, it has been intuitive to apply vertical MOSFETs in M3D ICs. The transistors in M3D are implemented with SOI technology, which could effectively reduce the parasitic capacitance, leakage current, and power consumption [14][15][16]. While, the reported research on SOI transistors mainly focused on planar devices [17][18][19], there has rarely been any reports on SOI-based vertical MOSFET; the motivation for our present research. On the other hand, it is worth noting that thermal issues are critical in M3D ICs due to the stacking of power devices, and high temperatures can cause the degradation of device performance [20]. Therefore, special attention should be given to the self-heating effect (SHE) of transistors. Electrothermal simulation is an effective way to predict device characteristics and various tools have been developed to conduct numerical analyses [21,22]. Among these tools, COMSOL Multiphysics software is capable of modeling and simulating the electrothermal process of semiconductor devices [23][24][25], and thus has been adopted in this study.
The rest of this paper is arranged as follows. The design and geometry of the proposed SOI-based vertical MOSFET, as well as a practical fabrication scheme are detailed in Section 2. The potential applications for the proposed device are briefly described. In Section 3, numerical simulation schemes for the electrical and electrothermal coupling simulations of the proposed device are presented. Then, the characteristics of the proposed vertical MOSFET are numerically simulated by following the designed schemes, and reliable results are achieved to evaluate the performance of the proposed device in Section 4. Some conclusions are finally drawn in Section 5. Figure 1 shows the geometry of the proposed vertical MOSFET. A thin SiO 2 layer is formed on top of the Si wafer for isolation, with the source electrode and interconnects processed on it. The doped Si film bonds on the dioxide layer works as the active layer for transistor fabrication. Contrary to the conventional planar SOI-based MOSFET, the heavily doped drain and source regions are located at the top and bottom surface of the proposed device, respectively. TOV is processed to construct the gate electrode. In particular, the hydrogen silsesquioxane layer is formed to determine the position of the gate electrode, and the insulator layers are fabricated on top of the active Si film for the electrodes and layout.

Device Model
The proposed vertical MOSFET is potential in the implementation of M3D ICs. For example, the low on-resistance of vertical transistor can work as switch to control the electrical connection between tiers, and a 3-D inverter could be constructed in M3D ICs, as shown in Figure 2. The drains of PMOS and NMOS are connected by conductor trace line as the output, and their gates act as the input. The proposed vertical MOSFET is potential in the implementation of M3D ICs. For example, the low on-resistance of vertical transistor can work as switch to control the electrical connection between tiers, and a 3-D inverter could be constructed in M3D ICs, as shown in Figure 2. The drains of PMOS and NMOS are connected by conductor trace line as the output, and their gates act as the input.

Fabrication Process
Here, a possible fabrication process is described in detail for the proposed vertical MOSFET to illustrate the feasibility of the proposed design scheme. As shown in Figure  3, the proposed transistor can be fabricated in two stages. In the first stage, a SiO2 is formed on the top of the Si wafer through thermal oxidation to serve as BOX, and the source electrode is deposited. In the second stage, a p-doped Si wafer is pre-treated by piranha (98% H2SO4: 30% H2O2 = 3:1) and DI water first [26], and then impurity doping and silicon direct bonding are conducted. During this process, the device region on the bonded surface is firstly doped by ion implantation method and then the Si film is boned onto Si/SiO2 substrate by direct bonding technology. Following is the doping on the other side of SOI is conducted and a rapid thermal anneal (RTA) is carried out in N2 ambient to activate ndoping ions and restore crystal lattices damage. Next, a hole is etched with the assistance of a photoresist mask. An improved Bosch is employed for hole etching, followed by several steps to remove CFx polymers in the inside of the hole [27,28]. A SiO2 layer is grown by thermal oxidation on the top of wafer, followed by a thermal atomic layer deposition (thALD) of Al2O3. After that, the drain electrode is deposited on the top of n + -doped region. At last, a HSQ spacer layer is processed [29], and a layer of metal film is sputtered on the spacer to form the gate electrode. So far, the proposed vertical transistor is fabricated. The 3-D CMOS inverter, shown in Figure 2, can effectively reduce the interconnect length, based on the direct interconnection between PMOS and NMOS through the hole via. The proposed vertical MOSFET is potential in the implementation of example, the low on-resistance of vertical transistor can work as switch to co trical connection between tiers, and a 3-D inverter could be constructed in shown in Figure 2. The drains of PMOS and NMOS are connected by condu as the output, and their gates act as the input.

Fabrication Process
Here, a possible fabrication process is described in detail for the prop MOSFET to illustrate the feasibility of the proposed design scheme. As sho 3, the proposed transistor can be fabricated in two stages. In the first stage, a S on the top of the Si wafer through thermal oxidation to serve as BOX, and th trode is deposited. In the second stage, a p-doped Si wafer is pre-treated by H2SO4: 30% H2O2 = 3:1) and DI water first [26], and then impurity doping and bonding are conducted. During this process, the device region on the bond firstly doped by ion implantation method and then the Si film is boned ont strate by direct bonding technology. Following is the doping on the other conducted and a rapid thermal anneal (RTA) is carried out in N2 ambient doping ions and restore crystal lattices damage. Next, a hole is etched with of a photoresist mask. An improved Bosch is employed for hole etching, foll eral steps to remove CFx polymers in the inside of the hole [27,28]. A SiO2 la by thermal oxidation on the top of wafer, followed by a thermal atomic lay (thALD) of Al2O3. After that, the drain electrode is deposited on the top of gion. At last, a HSQ spacer layer is processed [29], and a layer of metal film on the spacer to form the gate electrode. So far, the proposed vertical trans cated. The 3-D CMOS inverter, shown in Figure 2, can effectively reduce the length, based on the direct interconnection between PMOS and NMOS thro

Fabrication Process
Here, a possible fabrication process is described in detail for the proposed vertical MOSFET to illustrate the feasibility of the proposed design scheme. As shown in Figure 3, the proposed transistor can be fabricated in two stages. In the first stage, a SiO 2 is formed on the top of the Si wafer through thermal oxidation to serve as BOX, and the source electrode is deposited. In the second stage, a p-doped Si wafer is pre-treated by piranha (98% H 2 SO 4 : 30% H 2 O 2 = 3:1) and DI water first [26], and then impurity doping and silicon direct bonding are conducted. During this process, the device region on the bonded surface is firstly doped by ion implantation method and then the Si film is boned onto Si/SiO 2 substrate by direct bonding technology. Following is the doping on the other side of SOI is conducted and a rapid thermal anneal (RTA) is carried out in N 2 ambient to activate n-doping ions and restore crystal lattices damage. Next, a hole is etched with the assistance of a photoresist mask. An improved Bosch is employed for hole etching, followed by several steps to remove CF x polymers in the inside of the hole [27,28]. A SiO 2 layer is grown by thermal oxidation on the top of wafer, followed by a thermal atomic layer deposition (thALD) of Al 2 O 3 . After that, the drain electrode is deposited on the top of n + -doped region. At last, a HSQ spacer layer is processed [29], and a layer of metal film is sputtered on the spacer to form the gate electrode. So far, the proposed vertical transistor is fabricated. The 3-D CMOS inverter, shown in Figure 2, can effectively reduce the interconnect length, based on the direct interconnection between PMOS and NMOS through the hole via.

Simulation
In this section, the electrical characteristics of the proposed vertical transistor ing SS, Ion/Ioff ratio, threshold voltage and drain current in the conduction state are using the COMSOL Multiphysics software. At the same time, the electrothermal c simulation is also conducted to estimate the degradation in device performance a a significant concern about device performance and reliability [30]. In the simulat drift-diffusion model, composed of carrier current continuity equations and Poisso tion, is employed to characterize the electrical property, which reads: where is electron density, is hole density, is the potential, is the unit and represent the net recombination rate, and represent the co tion of ionized donor and acceptor, ⃗ and ⃗ are the electron and hole current which can be written as: is the Boltzmann constant, T is the temperature, and are the con band and valence band, , and , are carrier diffusivities, and and electron mobility and hole mobility, respectively. In the semiconductor module, t vol approach, combined with Scharfetter-Gummel current model is utilized to im the numerical calculation of carrier current continuity equations.

Simulation
In this section, the electrical characteristics of the proposed vertical transistor, including SS, I on /I off ratio, threshold voltage and drain current in the conduction state are studied using the COMSOL Multiphysics software. At the same time, the electrothermal coupling simulation is also conducted to estimate the degradation in device performance as SHE is a significant concern about device performance and reliability [30]. In the simulations, the drift-diffusion model, composed of carrier current continuity equations and Poisson equation, is employed to characterize the electrical property, which reads: where n is electron density, p is hole density, ϕ is the potential, q is the unit charge, R n and R p represent the net recombination rate, N + D and N − A represent the concentration of ionized donor and acceptor, → J n and → J p are the electron and hole current density, which can be written as: J n = qnµ n ∇E c + µ n k B T∇n + qnD n,th ∇ln(T) (4) where k B is the Boltzmann constant, T is the temperature, E c and E v are the conduction band and valence band, D n,th and D p,th are carrier diffusivities, and µ n and µ p are the electron mobility and hole mobility, respectively. In the semiconductor module, the finite vol approach, combined with Scharfetter-Gummel current model is utilized to implement the numerical calculation of carrier current continuity equations. To implement the thermal simulation, the Fourier heat transfer equation is numerically calculated by finite element method in the solid heat transfer module. The heat transfer equation can be written as: where ρ is the material density, C P is the heat capacity, u is the translatory velocity, k is the thermal conductivity and Q is the unit volume heat source which provided by the semiconductor module. To verify the accuracy of simulation process, a nanowire MOSFET, shown in Figure 4a, with 20 nm channel length, 1nm gate oxide thickness, 5 nm nanowire radius is simulated. In Figure 4b, the simulated results are compared with experimental data reported in [31], and good agreement is achieved.
where is the material density, is the heat capacity, is the trans is the thermal conductivity and is the unit volume heat source which semiconductor module. To verify the accuracy of simulation proc MOSFET, shown in Figure 4a, with 20 nm channel length, 1nm gate oxid nanowire radius is simulated. In Figure 4b, the simulated results are co perimental data reported in [31], and good agreement is achieved.

Electrical Performance
To simulate the characteristics of the proposed vertical transistor, a is established in COMSOL with 3 μm Si film thickness, 300 nm TOV ra width, and 30 nm gate oxide layer thickness. Then, an analytical dopin is employed to achieve doping distribution in the active region of the v Implantations of donor with a peak of 1 × 10 20 cm −3 and a 0.15 μm depth bution junction are made over a p-type background with a constant acce 10 16 cm −3 magnitude to form source and drain regions. The detail dopin illustrated in Figure 5, where Figure 5a presents the n-type ion doping d ure 5b displays donor ion concentration Nd and acceptor ion concentratio of doping depth.

Electrical Performance
To simulate the characteristics of the proposed vertical transistor, a geometric model is established in COMSOL with 3 µm Si film thickness, 300 nm TOV radius, 1.5 µm gate width, and 30 nm gate oxide layer thickness. Then, an analytical doping physical model is employed to achieve doping distribution in the active region of the vertical transistor. Implantations of donor with a peak of 1 × 10 20 cm −3 and a 0.15 µm depth Gaussian distribution junction are made over a p-type background with a constant acceptor profile of 1 × 10 16 cm −3 magnitude to form source and drain regions. The detail doping information is illustrated in Figure 5, where Figure 5a presents the n-type ion doping diagram, and Figure 5b displays donor ion concentration N d and acceptor ion concentration N a as a function of doping depth.
In order to feature the physical process in a transistor, the classical drift-diffusion model is applied. In the simulations, the metal-semiconductor contacts of the source and drain are set to be ideal ohmic contacts, while Schottky contact is assigned to the gate. Moreover, the Shockley-Read-Hall model is adopted to describe the recombinationgeneration occurring in the active region. The analysis of electrical performance mainly focuses on transfer curve and output curve. During the simulations, the result of the transfer curve is utilized as the initial value for the output curve calculation. bution junction are made over a p-type background with a constant ac 10 16 cm −3 magnitude to form source and drain regions. The detail do illustrated in Figure 5, where Figure 5a presents the n-type ion doping ure 5b displays donor ion concentration Nd and acceptor ion concentra of doping depth. In order to feature the physical process in a transistor, the clas model is applied. In the simulations, the metal-semiconductor contac drain are set to be ideal ohmic contacts, while Schottky contact is as Moreover, the Shockley-Read-Hall model is adopted to describe the

Electrothermal Coupling Simulation
As mentioned above, SHE is a main cause for the performance degradation, as SHE can induce a temperature rise in the transistors. The temperature rise in transistor could result in the reduction of electron/hole mobility, thereby increasing the on-resistance and affecting the transistor performance. Therefore, the electrothermal coupling simulation should be conducted to estimate the influence of SHE on the transistor performance.
Compared to the electrical simulation, the electrothermal coupling process is described by a mathematical equation system composed of drift-diffusion equation, thermal conduction equation, and coupling equations. The coupling equations work as the bridge linking the electric and thermal fields. In COMSOL software, two modules, i.e., Semiconductor and Heat Transfer in Solids, are utilized to realize the electrothermal coupling simulation of transistors. The semiconductor heat source and temperature-dependent parameters are utilized as the direct and indirect coupling equations. In the simulations, the initial temperature in the calculation region is set to be RT, i.e., 293.15 K. The electrical equations are firstly solved utilizing the Semiconductor module, and with the heat source achieved by electrical simulation as an input, the thermal conduction equation is subsequently solved to update the temperature distribution. Based on the calculated temperature, the temperature-dependent parameters are updated and arranged for the next calculation loop. After the coupling simulation, the output curve affected by SHE can be measured, and by comparing it with the curve achieved by pure electrical simulation, the influence of SHE can be observed intuitively.

Results and Discussion
Following the modeling and simulation schemes described above, the electrical and electrothermal characteristics of the proposed vertical MOSFET are captured.
The electrical simulations of the proposed transistor are carried out first. In Figure 6, the threshold voltages (Vth), SS, Ion/Ioff ratio curves versus gate biasing voltage are presented. The transfer curves with drain voltage of 0.01 V, 0.1 V and 2 V are presented in Figure 6a, and a 0.45V threshold voltage is observed. This low threshold voltage is mainly due to the low background doping. In Figure 6b, the I DS -V GS characteristic curves of the vertical transistor are presented in log-scale, and it can be observed that the proposed vertical transistor exhibits a high I on /I off ratio and low SS. For example, the I on /I off ratio for V DS = 0.1 V could reach as high as 9.6 × 10 9 and a low SS of 69 mV/dec is achieved for case of V DS = 0.01 V. The SS depends on minority carrier, i.e., the subthreshold current of MOSFET is the minority carrier diffusion current [32]. Accordingly, the SS is related to the factors that affect the minority carrier injection efficiency and its movement, and the factors affecting the gate control ability, include substrate doping concentration, temperature, and so on. Another index demonstrating an excellent gate controllability in the proposed transistor is the low drain induced barrier lowering (DIBL), which is less than 20 mV between cases of V DS = 0.1 V and 2 V. The electrical characteristics of the proposed vertical transistor are summar Table 1. It can be concluded that the proposed transistor possesses excellent sw performance with a low SS (69 mV/dec), which approaches the limit value of 60 m indicating that the proposed vertical MOSFET is qualified to be a switch. In additi high Ion/Ioff ratio exhibits excellent gate controllability, owing to vertical channel b any parasitic leakage path [33]. The output characteristic curves of the vertical M with changing VGS are shown in Figure 7a, where a maximum drain saturation cur 1500 μA is obtained in case of VGS = 4 V. Moreover, the 3-D electron concentration bution of the on-state is illustrated in Figure 7b, where the formation of vertical channel can be clearly observed. The electrical characteristics of the proposed vertical transistor are summarized in Table 1. It can be concluded that the proposed transistor possesses excellent switching performance with a low SS (69 mV/dec), which approaches the limit value of 60 mV/dec, indicating that the proposed vertical MOSFET is qualified to be a switch. In addition, the high I on /I off ratio exhibits excellent gate controllability, owing to vertical channel blocking any parasitic leakage path [33]. The output characteristic curves of the vertical MOSFET with changing V GS are shown in Figure 7a, where a maximum drain saturation current of 1500 µA is obtained in case of V GS = 4 V. Moreover, the 3-D electron concentration distribution of the on-state is illustrated in Figure 7b, where the formation of vertical current channel can be clearly observed. The electrical characteristics of the proposed vertical transistor are summarized in Table 1. It can be concluded that the proposed transistor possesses excellent switching performance with a low SS (69 mV/dec), which approaches the limit value of 60 mV/dec, indicating that the proposed vertical MOSFET is qualified to be a switch. In addition, the high Ion/Ioff ratio exhibits excellent gate controllability, owing to vertical channel blocking any parasitic leakage path [33]. The output characteristic curves of the vertical MOSFET with changing VGS are shown in Figure 7a, where a maximum drain saturation current of 1500 μA is obtained in case of VGS = 4 V. Moreover, the 3-D electron concentration distribution of the on-state is illustrated in Figure 7b, where the formation of vertical current channel can be clearly observed.    The performance indexes of the proposed vertical transistor are compared with previous reported works in Table 2. The improvement in the I on /I off ratio is achieved from the gate electrode surrounding the whole channel region which enhances the gate controllability, and the low SS due to the low substrate doping concentration and outstanding gate controllability. In practice, however, the SHE in active region could induce temperature rise, and then result in performance degradation. Consequently, the electrothermal coupling simulations are conducted to evaluate the influence of SHE on the transistor performance. The obtained temperature distributions on the cross-section along the axis direction for different biasing configurations are presented in Figure 8. A maximum temperature of 410 K is observed in case of V DS = 5 V and V GS = 4 V, as the channel current is larger than in other three cases, as shown in Figure 7. Generally, there is no significant increase in the device temperature, which is mainly due to the satisfactory heat dissipation performance of TOV [36].
It can be observed that a high temperature region is located at the current channel near the drain side, and the heat gradually propagates outward to form temperature gradient. As the drain voltage increases, the distribution of high temperature region becomes more concentrated. This is mainly because the current channel near the drain region is the narrowest, which results in the largest current density, i.e., the maximum power density. To intuitively observe this phenomenon, the distributions of the generated heat power with V DS = 3 V, V GS = 4 V and V DS = 5 V, V GS = 4 V are shown in Figure 9.
During the transistor operation, the internal joule heat accumulates and induces the temperature rise. The excessive temperature rise could degrade the device performance and affect the reliability [37]. The output characteristics of the proposed vertical MOSFET, based on the electrothermal coupling simulations, are obtained and illustrated in Figure 10. It is evident that the drain currents obtained by electrothermal coupling simulation are slightly smaller than those obtained by electrical simulations. Compared with high V GS case, the difference between I DS, achieved by electrical and electrothermal simulations, is smaller than in low V GS . This is mainly because a lower channel current corresponds to lower temperature rise, i.e., lower performance degradation. On the other hand, for the same V GS , the current drop increases with V DS . Similarly, this arises from the device temperature increases with V GS . As the device current level drops slightly, it can be concluded that the proposed transistor possesses good thermal stability. The obtained temperature distributions on the cross-section along the axis directi different biasing configurations are presented in Figure 8. A maximum temperat 410K is observed in case of VDS = 5V and VGS = 4V, as the channel current is larger t other three cases, as shown in Figure 7. Generally, there is no significant increase device temperature, which is mainly due to the satisfactory heat dissipation perform of TOV [36]. It can be observed that a high temperature region is located at the current ch near the drain side, and the heat gradually propagates outward to form temperatur dient. As the drain voltage increases, the distribution of high temperature region be more concentrated. This is mainly because the current channel near the drain region narrowest, which results in the largest current density, i.e., the maximum power de  During the transistor operation, the internal joule heat accumulates an temperature rise. The excessive temperature rise could degrade the device and affect the reliability [37]. The output characteristics of the proposed vert based on the electrothermal coupling simulations, are obtained and illustr 10. It is evident that the drain currents obtained by electrothermal coupling slightly smaller than those obtained by electrical simulations. Compared ). However, the increase in drain current could res consumption and then aggravate SHE. The electrothermal couplin been carried out, and the maximum temperatures in MOSFETs are pre Consistent with the saturation current, the maximum temperature in with the decrease in channel length and gate oxide thickness. It can a the maximum temperature in MOSFET with = 1200 nm, = 30 is lower than those in MOSFETs with = 600 nm, = 30 nm, a with = 1200nm, = 20 nm, and = 4.5, although it possess current. This is mainly due to the high thermal conductivity of HfO creasing gate oxide thickness could increase the saturation current to s would be aggravated, and the probability for reliability issues such as down, would arise [38]. ε gate = 4.5 Further, the influences of geometric parameters on the performance of the proposed vertical MOSFET are investigated, with some results illustrated in Figure 11. It can be observed that the saturation current of the MOSFET is improved with decreasing channel length (L) and gate oxide thickness (t ox ), and with the increasing relative permittivity of gate oxide (ε gate ). However, the increase in drain current could result in larger power consumption and then aggravate SHE. The electrothermal coupling simulations have been carried out, and the maximum temperatures in MOSFETs are presented in Figure 12. Consistent with the saturation current, the maximum temperature in MOSFETs increases with the decrease in channel length and gate oxide thickness. It can also be observed that the maximum temperature in MOSFET with L = 1200 nm, t ox = 30 nm, and ε gate = 20 is lower than those in MOSFETs with L = 600 nm, t ox = 30 nm, and ε gate = 4.5, and with L = 1200nm, t ox = 20 nm, and ε gate = 4.5, although it possesses largest saturation current. This is mainly due to the high thermal conductivity of HfO 2 . Although the decreasing gate oxide thickness could increase the saturation current to some extent, the SHE would be aggravated, and the probability for reliability issues such as electric field breakdown, would arise [38]. with = 1200nm, = 20 nm, and = 4.5, although it possess current. This is mainly due to the high thermal conductivity of HfO creasing gate oxide thickness could increase the saturation current to s would be aggravated, and the probability for reliability issues such as down, would arise [38].

Conclusions
A vertical MOSFET, based on silicon-on-insulator technologies its characteristics were investigated through numerical simulations. A tion was firstly carried out, and the results indicated that the propo sesses excellent electrical performance. A 1500 μA on-state current (I case of VGS = 4 V and VDS = 5 V, and excellent current control ability w a 1.28 × 10 11 Ion/Ioff ratio was obtained. Moreover, an extremely low of 69mV/dec was obtained, which makes the proposed MOSFET a us olithic 3-D ICs. Further, the electrothermal coupling simulations were uate the influence of self-heating effect on the transistor performanc

Conclusions
A vertical MOSFET, based on silicon-on-insulator technologies was proposed, and its characteristics were investigated through numerical simulations. An electrical simulation was firstly carried out, and the results indicated that the proposed transistor possesses excellent electrical performance. A 1500 µA on-state current (I DS ) was achieved in case of V GS = 4 V and V DS = 5 V, and excellent current control ability was demonstrated as a 1.28 × 10 11 I on /I off ratio was obtained. Moreover, an extremely low subthreshold swing of 69mV/dec was obtained, which makes the proposed MOSFET a useful switch in monolithic 3-D ICs. Further, the electrothermal coupling simulations were conducted to evaluate the influence of self-heating effect on the transistor performance. The results illustrated that the self-heating effect induced a temperature rise in the channel, and then reduced performance.