A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.


Introduction
The increasing appearance of long-life autonomous portable and wearable equipment [1][2][3][4][5][6][7][8] demanding miniaturized systems with decreasing power consumption has brought to the forefront the design of efficient power management units (PMU), where low dropout (LDO) regulators play a key role [9][10][11][12][13]. As shown in Figure 1, in battery-operated systems, the LDO generates, from the battery voltage V BAT , a stable, low-noise and accurate supply voltage V out under substantial changes of the battery voltage and the load current demanded to bias a specific system module, typically making use of multiple LDOs so as to optimize each module power consumption and, therefore, the global power efficiency.
Conventional LDOs rely on external µF capacitors located at the output node to guarantee stability and at the same time to minimize the variations on V out under transient operation [14][15][16]. Nonetheless, the reduction in power and size of the systems is leading toward complete system-on-chip (SoC) devices, where all the components need to be fully integrated. A key condition in the implementation of low-cost system-on-chip solutions is compatibility with complementary metal-oxide-semiconductor (CMOS) technology. This, in turn, has been associated with low-voltage compliance, since as CMOS technology downscales, the supply voltage also downscales, very nearly approaching the threshold voltage of MOS transistors, such that the new strategies must be followed when designing such low-voltage circuits.
Therefore, the design of CMOS capacitor-less low-dropout regulators has become a promising research topic, requiring low-voltage architectures with alternative on-chip compensation techniques that maintain the stability of the system over all the operating range while preserving the regulating performance. Moreover, a key parameter in portable devices is power consumption, since it determines the battery life. This implies the use of low quiescent currents I q . However, reducing I q degrades the dynamic performance: the maximum output current is limited, thus limiting parameters such as slew-rate and settling time. This makes necessary the introduction of transient enhancement circuit techniques to balance the dynamic performance with a minimum effect on power efficiency and circuit complexity. There is extensive research on low dropout regulators for portable applications by taking advantage of the miniaturization of CMOS technology [17][18][19][20][21][22][23][24][25][26]. However, some of them report load capacitor values that do not comply with the size constraint of portable SoC devices ( [17] and [18] report external load capacitors of 1 µF and 3 nF, respectively). Among those that are fully integrated, power consumption is jeopardized by quiescent currents too high to be used in short-lived battery-operated devices ( [19] reports 495 µA, [20] 188 µA, [21] 76 µA and [22] 265 µA). Other proposals enhance the transient response by using adaptive biasing but jeopardizing the circuit complexity and power consumption ( [23] increases the I q from 4.45 µA for I Load = 100 µA up to 130 µA for I Load = 100 mA; and the I q from [24] goes from 42.1 µA for I Load < 1 mA up to 108 µA I Load > 1 mA). Moreover, some LDOs require a minimum load current for stability, and therefore, the total current consumption is actually I q + I Load,min , further reducing the battery life ( [25] reports a minimum load current of 250 µA, [21,23,26] 100 µA, [22] 10 µA and [20] 1 mA). Accordingly, there exists an overall power-area-transient behavior trade-off that makes the design of a fully integrated stable LDO a significant challenge, with high regulation performance and good dynamic performance, preserving ultralow power consumption and a compact topology.
In this proposal, an all-MOS capacitor-less low dropout (LDO) regulator is presented with improved performance aimed at this demanding scenario of portable on-chip devices. Thus, design guidelines are used to minimize both the power and area consumption, while maintaining an adequate regulating performance with a low-voltage topology for our requirements: a 1.2 V output voltage, V out , compatible with battery supply voltage values V BAT = 3.3 − 1.3 V, for a maximum I Load = 50 mA over a C Load,max = 50 pF. In this attempt, we have followed the compensation and dynamic-enhancement strategies successfully adopted in [27] but adapted to provide the required low-voltage compatibility, further optimizing the transient response by introducing a multiple dynamic feedback strategy. Moreover, a fully integrated temperature and voltage-supply-independent voltage reference are also proposed to further advance into a truly integrated device.
Some preliminary results were reported in [28]. In this paper, the optimized design and complete postlayout characterization of the LDO are presented. The organization of this paper is as follows: in Section 2, the design of the low dropout (LDO) regulator is presented; the characterization and comparison with other LDO regulators is reported in Section 3. Finally, in Section 4, conclusions are drawn.

Proposed Topology
In this section, the operating principle of a LDO regulator is introduced together with the schematic design of the proposed 1.2 V LDO regulator. Figure 2a illustrates the basic scheme of a linear regulator, which provides a regulated voltage V out from an unregulated input voltage V in , which is the battery voltage V BAT for the power management unit of a battery-operated portable device [29]. A sampling circuit is responsible for sensing the variations over V out because of variations in the power supply and/or in the load current. An error amplifier (EA) compares the difference between this signal and a reference voltage, V ref , and drives the control element, which makes the necessary modifications to set the desired voltage at the output.

Proposed Topology
In this section, the operating principle of a LDO regulator is introduced together with the schematic design of the proposed 1.2 V LDO regulator. Figure 2a illustrates the basic scheme of a linear regulator, which provides a regulated voltage Vout from an unregulated input voltage Vin, which is the battery voltage VBAT for the power management unit of a battery-operated portable device [29]. A sampling circuit is responsible for sensing the variations over Vout because of variations in the power supply and/or in the load current. An error amplifier (EA) compares the difference between this signal and a reference voltage, Vref, and drives the control element, which makes the necessary modifications to set the desired voltage at the output.  Figure 2b presents the typical scheme of a CMOS LDO regulator, which uses a PMOS transistor as the control element to minimize the dropout voltage Vdo = VBAT − Vout and a resistive network Rfb1 − Rfb2 as a sampling circuit. This negative feedback resistive network samples the output voltage Vout through a feedback voltage Vfb, which is compared against the reference voltage, Vref. The variation is amplified and applied to the PMOS transistors gate, Vg, acting as the control element to keep the desired output voltage constant regardless of the changes in the supply voltage, Vin, or the current required by the load, modelled through RLoad and CLoad.
Assuming an ideal amplifier, the output voltage is then given by The main design parameters for low dropout regulators include stability, line regulation (LNR), load regulation (LDR), line transient regulation, load transient regulation and power supply rejection (PSR). To achieve a high level of precision in the regulation, the use of high gain error amplifiers is required, as shown by Equations (2) and (3) [30]. The load regulation is approximated to: and line regulation  Figure 2b presents the typical scheme of a CMOS LDO regulator, which uses a PMOS transistor as the control element to minimize the dropout voltage V do = V BAT − V out and a resistive network R fb1 − R fb2 as a sampling circuit. This negative feedback resistive network samples the output voltage V out through a feedback voltage V fb , which is compared against the reference voltage, V ref . The variation is amplified and applied to the PMOS transistors gate, V g , acting as the control element to keep the desired output voltage constant regardless of the changes in the supply voltage, V in , or the current required by the load, modelled through R Load and C Load .
Assuming an ideal amplifier, the output voltage is then given by The main design parameters for low dropout regulators include stability, line regulation (LNR), load regulation (LDR), line transient regulation, load transient regulation and power supply rejection (PSR). To achieve a high level of precision in the regulation, the use of high gain error amplifiers is required, as shown by Equations (2) and (3) [30]. The load regulation is approximated to: and line regulation where g mP is the pass transistors transconductance, A V the open-loop gain of the EA, and α is the feedback factor set by R fb2 /(R fb1 +R fb2 ). Therefore, since both LNR and LDR are inversely dependent to the error amplifier DC gain, the higher the A V, the better the regulation. The simplest amplifier topology is a differential pair. To increase its gain without power penalty, a cascode configuration is used, obtaining the so-called telescopic amplifier. This structure, however, implies the use of several stacked transistors, a technique unfit for low-voltage solutions. To take advantage of the cascode technique to increase the amplifier gain with a topology suitable for low-voltage operations with minimum power penalty, the folded-cascode amplifier is used. Thus, a folded-cascode structure is considered. By using this simple one-stage topology, we are able to lower both the requirements for power and area consumption, simplifying altogether the LDO compensation, which corresponds to a two-pole system (Figure 2b), one at the pass transistor gate, and given by: where R oa and C oa characterize the output impedance of the error amplifier and C gs P the gate-source capacitance of the PMOS pass transistor. The second pole is located at the LDO output and is given by: To achieve a stable SoC LDO regulator over all the I Load operating conditions, the dominant pole of the system must be placed, through internal compensation techniques, at the output of the error amplifier, f EA , while the pole located at the output of the LDO regulator must satisfy f OUT f EA .

Core Structure
The core structure, as shown in Figure 2b consists of a reference voltage V ref = 0.4 V, a PMOS pass transistor MP, a resistive feedback network and an EA, and its schematic is shown in Figure 3. To guarantee the operation of the PMOS pass transistor in saturation for maximum I Load = 50 mA with a V do = 300 mV, its size is set to 9 mm/340 nm. In order to minimize the parasitic gate pass transistor capacitance C gs P -which is~11 pF with no load and up to 17 pF at the maximum load-the transistor length used is the minimum allowed by the technology.
The static current through the pass transistor is set to 1.5 µA at no load current condition to keep a low power consumption. With a V out = 1.2 V and a reference voltage V ref = 0.4 V, the resistive feedback network results in R fb1 + R fb2 = 800 kΩ with R fb1 = 2R fb2 . These resistances have been carried out through three identical low-voltage PMOS transistors in a P-substrate N-well technology (M0, size 1 µm/1 µm, with V BS = 0) in diode configuration to further optimize the area, resulting in an area reduction of~250 times, compared to its implementation with a highly resistive polysilicon layer of the technology (R square = 1039 Ω/square).
A folded-cascode PMOS-input differential amplifier implements the error amplifier. It is a single-stage high-gain structure specifically designed for low-voltage applications. Consequently, good line regulation (LNR) and load regulation (LDR)-Equations (2) and (3)-are achieved while the power consumption is maintained bounded and compensation is simplified [31]. Low-voltage transistors (native to the technology) are used for both the cascode transistors, using a self-biased scheme (gates of M4 and M4 C are connected, and the same happens with M3 and M3 C ); with this method, no additional bias branches are required ( Figure 3). All other transistors in the circuit are 3.3 V regular. Figure 3 also details the schematic view of the two transistors (native and regular) and their main parameters.  As shown in Figure 4, f moves toward higher frequencies for higher load currents rendering the system stable. However, as the load current reduces, f approaches f , reducing the phase margin down to 32°, i.e., under the (45°-60°) limit that guarantees stability [32]. Thus, to separate the poles and keep the system stable, a single MIM capacitor CC = 6.1 pF (78 µm/78 µm size) is used as a cascode compensation technique (in grey in Figure 3), attaining a PM above 60.3° over all the working conditions ( Figure 4). As shown in Figure 4, f OUT moves toward higher frequencies for higher load currents rendering the system stable. However, as the load current reduces, f OUT approaches f EA , reducing the phase margin down to 32 • , i.e., under the (45 • -60 • ) limit that guarantees stability [32]. Thus, to separate the poles and keep the system stable, a single MIM capacitor C C = 6.1 pF (78 µm/78 µm size) is used as a cascode compensation technique (in grey in Figure 3), attaining a PM above 60.3 • over all the working conditions ( Figure 4).  As shown in Figure 4, f moves toward higher frequencies for higher load currents rendering the system stable. However, as the load current reduces, f approaches f , reducing the phase margin down to 32°, i.e., under the (45°-60°) limit that guarantees stability [32]. Thus, to separate the poles and keep the system stable, a single MIM capacitor CC = 6.1 pF (78 µm/78 µm size) is used as a cascode compensation technique (in grey in Figure

Transient Response
The combination of a low quiescent current, I q , coupled with the limited slew-rate at the error amplifier output node due to the high pass transistor gate capacitance, as well as the small load capacitor compared to the conventional externally compensated µF load capacitor LDOs results in large time responses and voltage peaks, as it can be seen in the characterization of the transient load regulation without any circuit to enhance the dynamic behavior, shown in Figure

Transient Response
The combination of a low quiescent current, Iq, coupled with the limited slew-rate at the error amplifier output node due to the high pass transistor gate capacitance, as well as the small load capacitor compared to the conventional externally compensated µF load capacitor LDOs results in large time responses and voltage peaks, as it can be seen in the characterization of the transient load regulation without any circuit to enhance the dynamic behavior, shown in Figure   This is performed through a simple but effective dynamic transient control (TC) circuit, only active during the transients, so that both the additional circuit complexity and power consumption remain bounded as shown in grey (transient control circuit, TC) in Figure 6. The overshoot (OS) transient detection circuit consists of a NMOS quasifloating gate (QFG) transistor MQFG,N, with the voltage gate set to a DC bias VBN connected using a large resistance realized by two series reversed-biased PMOS transistors in diode configuration and linked to the output node through a capacitor CQFG = 1 pF. In a steady state, the gate to source voltage is VGS = VBN = 0.4 V < VTH,N = 0.59 V; therefore, MQFG,N stays in the cut-off region with a weak leakage current consumption. Meanwhile, when ILoad suddenly decreases, the overshoot at Vout couples through CQFG triggering on the transistor and generating a current. This current is directly added to the error amplifiers lower Ibias branch at node C, assisting the gate capacitance CPASS charge. In addition, MQFG,N is duplicated to MQFG,N' dynamically sinking supplementary current at the output node of the LDO regulator, aiding to discharge the path made by (Rfb1 + Rfb2) and CLoad. When Vout is regulated back to its nominal value, MQFG,N returns to the off region. This is performed through a simple but effective dynamic transient control (TC) circuit, only active during the transients, so that both the additional circuit complexity and power consumption remain bounded as shown in grey (transient control circuit, TC) in Figure 6. The overshoot (OS) transient detection circuit consists of a NMOS quasifloating gate (QFG) transistor M QFG,N, with the voltage gate set to a DC bias V BN connected using a large resistance realized by two series reversed-biased PMOS transistors in diode configuration and linked to the output node through a capacitor C QFG = 1 pF. In a steady state, the gate to source voltage is V GS = V BN = 0.4 V < V TH,N = 0.59 V; therefore, M QFG,N stays in the cut-off region with a weak leakage current consumption. Meanwhile, when I Load suddenly decreases, the overshoot at V out couples through C QFG triggering on the transistor and generating a current. This current is directly added to the error amplifiers lower I bias branch at node C, assisting the gate capacitance C PASS charge. In addition, M QFG,N is duplicated to M QFG,N dynamically sinking supplementary current at the output node of the LDO regulator, aiding to discharge the path made by (R fb1 + R fb2 ) and C Load . When V out is regulated back to its nominal value, M QFG,N returns to the off region.
For the undershoot (US) transient detection circuit, a similar circuit based on two identical QFG PMOS transistors M QFG,P is used. Again, with a DC bias voltage V BP connected to the voltage gate through a R Large resistive element and to V out through a C QFG capacitor of 1 pF. In a steady state, the transistor remains in the cut-off region with the voltage gate being V SG = (V BAT − V BP ) = 0.55 V < |V TH,P | = 0.72 V. Afterward, when V out suddenly decreases, the variation is conveyed to M QFG,P transistors gate, turning V SG > |V TH,P | entering the on region of the transistors. The newly generated currents are added to the error amplifiers upper I bias branches at nodes A and B, respectively, hastening the gate capacitance C PASS discharge. When V out is taken back to its nominal value, M QFG,P returns to the off region. For the undershoot (US) transient detection circuit, a similar circuit based on two identical QFG PMOS transistors MQFG,P is used. Again, with a DC bias voltage VBP connected to the voltage gate through a RLarge resistive element and to Vout through a CQFG capacitor of 1 pF. In a steady state, the transistor remains in the cut-off region with the voltage gate being VSG = (VBAT − VBP) = 0.55 V < |VTH,P| = 0.72 V. Afterward, when Vout suddenly decreases, the variation is conveyed to MQFG,P transistors gate, turning VSG > |VTH,P| entering the on region of the transistors. The newly generated currents are added to the error amplifiers upper Ibias branches at nodes A and B, respectively, hastening the gate capacitance CPASS discharge. When Vout is taken back to its nominal value, MQFG,P returns to the off region.
To further improve the US transient behavior, Figure 6 shows in red another QFG approach (transient enhancement circuit, TEC) that adds dynamic current sources MDB in parallel to the currents at nodes A and B. In a steady state, VG,MDB = VG,M2 and transistors are in a saturation region driving a static current of 1 µA each. When Vout decreases, the variations are coupled to their gate through capacitor CQFG, accelerating the discharge process.
Transistor   To further improve the US transient behavior, Figure 6 shows in red another QFG approach (transient enhancement circuit, TEC) that adds dynamic current sources M DB in parallel to the currents at nodes A and B. In a steady state, V G,MDB = V G,M2 and transistors are in a saturation region driving a static current of 1 µA each. When V out decreases, the variations are coupled to their gate through capacitor C QFG , accelerating the discharge process.
Transistor  For the undershoot (US) transient detection circuit, a similar circuit based on two identical QFG PMOS transistors MQFG,P is used. Again, with a DC bias voltage VBP connected to the voltage gate through a RLarge resistive element and to Vout through a CQFG capacitor of 1 pF. In a steady state, the transistor remains in the cut-off region with the voltage gate being VSG = (VBAT − VBP) = 0.55 V < |VTH,P| = 0.72 V. Afterward, when Vout suddenly decreases, the variation is conveyed to MQFG,P transistors gate, turning VSG > |VTH,P| entering the on region of the transistors. The newly generated currents are added to the error amplifiers upper Ibias branches at nodes A and B, respectively, hastening the gate capacitance CPASS discharge. When Vout is taken back to its nominal value, MQFG,P returns to the off region.
To further improve the US transient behavior, Figure 6 shows in red another QFG approach (transient enhancement circuit, TEC) that adds dynamic current sources MDB in parallel to the currents at nodes A and B. In a steady state, VG,MDB = VG,M2 and transistors are in a saturation region driving a static current of 1 µA each. When Vout decreases, the variations are coupled to their gate through capacitor CQFG, accelerating the discharge process.

Voltage Reference Circuit
Finally, to truly achieve a fully integrated LDO, the voltage reference V ref = 0.4 V is also implemented on-chip. Observe that as per Equation (1), V out is directly dependent of the reference voltage. Therefore, any dependence on the temperature and/or the battery voltage in V ref is transferred to V out . This voltage reference is typically implemented as a bandgap voltage reference with a combination of complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages or currents to provide a reliable temperature and supply independent solution [33][34][35][36][37][38]. However, the classical approaches typically provide higher values than the low-voltage 0.4 V approach herein adopted, while usually demanding high levels of power and area consumption not suitable for miniaturized portable systems.
Therefore, the 0.4 V voltage reference proposed here is based in the technique used for a 2-transistor (2T) V ref ( [39], Figure 8a), which takes advantage of different transistors with different threshold voltages V th (one regular thick oxide V th,r and one native device V th,n ) operating in the subthreshold region. Therefore, the voltage reference performance can be modelled from the subthreshold current equation: where β = µC OX (W/L) with µ being the mobility of the electrons, C OX the oxide-capacitance and (W/L) the transistors dimensions; m is the emission coefficient; V T = K B T/q corresponds to the thermal voltage with K B Boltzmann's constant, T the temperature and q the electron charge; V gs is the gate-to-source voltage; V th the threshold voltage and V ds the drain-to-source voltage.

Voltage Reference Circuit
Finally, to truly achieve a fully integrated LDO, the voltage reference Vref = 0.4 V is also implemented on-chip. Observe that as per Equation (1), Vout is directly dependent of the reference voltage. Therefore, any dependence on the temperature and/or the battery voltage in Vref is transferred to Vout.
This voltage reference is typically implemented as a bandgap voltage reference with a combination of complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages or currents to provide a reliable temperature and supply independent solution [33][34][35][36][37][38]. However, the classical approaches typically provide higher values than the low-voltage 0.4 V approach herein adopted, while usually demanding high levels of power and area consumption not suitable for miniaturized portable systems.
Therefore, the 0.4 V voltage reference proposed here is based in the technique used for a 2-transistor (2T) Vref ( [39], Figure 8a), which takes advantage of different transistors with different threshold voltages Vth (one regular thick oxide Vth,r and one native device Vth,n) operating in the subthreshold region. Therefore, the voltage reference performance can be modelled from the subthreshold current equation: where β = µCOX(W/L) with µ being the mobility of the electrons, COX the oxide-capacitance and (W/L) the transistors dimensions; m is the emission coefficient; VT = KBT/q corresponds to the thermal voltage with KB Boltzmann's constant, T the temperature and q the electron charge; Vgs is the gate-to-source voltage; Vth the threshold voltage and Vds the drain-to-source voltage. For the topology in Figure 8a, setting the current equal through the native and the regular transistor, the reference voltage is given by [39]: By using this 2T topology, Vref values are below the 0.4 V target reference voltage. To achieve the required voltage level, the 2T variant cascades three stages as shown in Figure  8b increasing the voltage reaching the 0.4 V, similar to the 4T Vref presented in [39] and the 6T used in [40]. In the 180 nm technology used the threshold voltages for NMOS transistors are Vth,r = 0.592 V and Vth,n = 0.068 V. Transistor sizes (µm/µm) are M5 = 0.5/0.5, M6 = 0.24/0.5, M7 = 225/0.5, such that Vref = 0.4 V with a total Iq of 20.4 nA and an output capacitor Cref = 0.5 pF is added to the output to enhance its transient performance. For the topology in Figure 8a, setting the current equal through the native and the regular transistor, the reference voltage is given by [39]: By using this 2T topology, V ref values are below the 0.4 V target reference voltage. To achieve the required voltage level, the 2T variant cascades three stages as shown in Figure 8b increasing the voltage reaching the 0.4 V, similar to the 4T V ref presented in [39] and the 6T used in [40]. In the 180 nm technology used the threshold voltages for NMOS transistors are V th,r = 0.592 V and V th,n = 0.068 V. Transistor sizes (µm/µm) are M5 = 0.5/0.5, M6 = 0.24/0.5, M7 = 225/0.5, such that V ref = 0.4 V with a total I q of 20.4 nA and an output capacitor C ref = 0.5 pF is added to the output to enhance its transient performance.

Characterization
The proposed LDO design has been implemented in the 180 nm CMOS technology from UMC. The layout view is shown in Figure 9 with a total area consumption of

Characterization
The proposed LDO design has been implemented in the 180 nm CMOS technology from UMC. The layout view is shown in Figure 9 with a total area consumption of 382 µm x 285 µm. The reported postlayout simulation results have been executed using Spectre with a BSIM3v3 level 53 transistor model. A 0.5 µA bias current is inserted to the circuit through a 1:2 current mirror, displaying a total Iq in steady state of 5.5 µA if the TC transient circuit is used and of 8.6 µA if the TEC transient circuit is added-including the generation of the bias voltages VBN and VBP-. It presents a temperature-independent voltage supply-independent Vout = 1.2 V, for a battery-supplied Vin ranging from 3.3 V down to ~1.3 V, with a Vdo ~ 100 mV and a maximum load of 50 mA and 50 pF. First, the proposed Vref is characterized against voltage and temperature variations to validate its design. Then, the static (characterized by the load regulation (LDR), the line regulation (LNR) and the quiescent current, Iq) and dynamic (characterized by the transient load and line regulations) behavior are characterized. Figure 10a shows the temperature and Figure 10b the battery voltage, VBAT, dependence of the reference voltage, Vref, which remains almost constant at 400 mV. For a temperature variation from −40 to 120°C the maximum Vref variation is 87.5 ppm/°C (at VBAT = 2.5 V), and for a power supply variation from 1.3 to 3.3 V, the Vref variation is 0.0155%/V (at 27°C).  Figure 11 shows the static VBAT − Vout characteristic. Figure 11a presents the results for a voltage sweep from 3.3 V down to 1.0 V, at room temperature, Troom, for different ILoad from 0 to 50 mA. The LDO regulator provides a constant Vout of 1.2 V for VBAT > 1.31 V (dropout voltage, Vdo of 110 mV) with an error <1 % for all range of load currents. Figure  11b present the same characteristic against temperature (from −40 to 120 °C) for the de-  Figure 11 shows the static V BAT − V out characteristic. Figure 11a presents the results for a voltage sweep from 3.3 V down to 1.0 V, at room temperature, T room , for different I Load from 0 to 50 mA. The LDO regulator provides a constant V out of 1.2 V for V BAT > 1.31 V (dropout voltage, V do of 110 mV) with an error < 1 % for all range of load currents. Figure 11b present the same characteristic against temperature (from −40 to 120 • C) for the designed V ref with maximum load current, showing a maximum variation of 26.8 mV (168 ppm/ • C) in Figure 11b.  Figure 11 shows the static VBAT − Vout characteristic. Figure 11a presents the results for a voltage sweep from 3.3 V down to 1.0 V, at room temperature, Troom, for different ILoad from 0 to 50 mA. The LDO regulator provides a constant Vout of 1.2 V for VBAT > 1.31 V (dropout voltage, Vdo of 110 mV) with an error <1 % for all range of load currents. Figure  11b present the same characteristic against temperature (from −40 to 120 °C) for the designed Vref with maximum load current, showing a maximum variation of 26.8 mV (168 ppm/°C) in Figure 11b. The consumed current, Iq, by the system over the battery voltage is shown in Figure  12. Figure 12a shows the variation with both the ideal reference voltage and the designed one, showing no significant difference (around ±20 nA difference). With the proposed reference voltage, the average current consumption is 8.59 µA ± 40 nA. Figure 12b displays the quiescent current for different temperatures, showing a current increase over temperature, with a maximum deviation of ~70 nA/°C. The consumed current, I q , by the system over the battery voltage is shown in Figure 12. Figure 12a shows the variation with both the ideal reference voltage and the designed one, showing no significant difference (around ±20 nA difference). With the proposed reference voltage, the average current consumption is 8.59 µA ± 40 nA. Figure 12b Figure 15 presents the performance for a full load transition (0 mA-50 mA-0 mA with 1 µs rise/fall times) for VBAT = 3.3 V, with and without the TC and TEC transient circuits. Figure 15a presents the undershoot (US) performance and Figure 15b Figure 15 presents the performance for a full load transition (0 mA-50 mA-0 mA with 1 µs rise/fall times) for V BAT = 3.3 V, with and without the TC and TEC transient circuits. Figure 15a presents the undershoot (US) performance and Figure 15b the overshoot (OS) performance. Figure 15a shows that the suggested low-dropout regulator achieves stability for undershoot (US) variations with a 1% error for a maximum variation of 499 mV within 5.9 µs (TC); this means an enhancement of 8.3 µs and 260 mV. With the TEC circuit, shown in grey in Figure 6, the discharge process can be enhanced reducing the maximum variation down to 340 mV within 1.3 µs. Figure 15 presents the performance for a full load transition (0 mA-50 mA-0 mA with 1 µs rise/fall times) for VBAT = 3.3 V, with and without the TC and TEC transient circuits. Figure 15a presents the undershoot (US) performance and Figure 15b Figure 15a shows that the suggested low-dropout regulator achieves stability for undershoot (US) variations with a 1% error for a maximum variation of 499 mV within 5.9 µs (TC); this means an enhancement of 8.3 µs and 260 mV. With the TEC circuit, shown in grey in Figure 6, the discharge process can be enhanced reducing the maximum variation down to 340 mV within 1.3 µs. Figure 15b shows this behavior for overshoot (OS) variations; the stability is achieved with a 1% error for a maximum variation of 406 mV and within 7.5 µs (TC); and this means an enhancement of 27.9 µs and 1.23 V. With the TEC circuit, the process is enhanced reducing the maximum variation down to 326 mV within 3.0 µs.   Figure 16a shows that for undershoot (US) variations stability is achieved with a 1% error for a maximum variation of 307 mV within 13.6 µs (TC). This means an enhancement of 0.6 µs and 475 mV. With the TEC circuit, the undershoot is slightly enhanced, down to 314 mV within 12.8 µs. Figure 16b shows the performance for overshoot (OS) variations. The stability is achieved with a 1% error with a maximum variation of 283 mV and within 7.3 µs (TC), this means an enhancement of 28.5 µs and 1.041 V. While in the TEC circuit, the process is enhanced, reducing the maximum variation down to 288 mV within 4.8 µs. Table 1 summarizes the performance of the postlayout results of the main characteristics of the reported low dropout regulator and compares them with previously reported works with similar design specifications. To show the influence of Vref, the results for an ideal Vref are also included. In addition, to compare the performance between the different proposals, two figures of merit (FoM) are introduced next. FoM1 previously defined in  Figure 16a shows that for undershoot (US) variations stability is achieved with a 1% error for a maximum variation of 307 mV within 13.6 µs (TC). This means an enhancement of 0.6 µs and 475 mV. With the TEC circuit, the undershoot is slightly enhanced, down to 314 mV within 12.8 µs. Figure 16b shows the performance for overshoot (OS) variations. The stability is achieved with a 1% error with a maximum variation of 283 mV and within 7.3 µs (TC), this means an enhancement of 28.5 µs and 1.041 V. While in the TEC circuit, the process is enhanced, reducing the maximum variation down to 288 mV within 4.8 µs. Table 1 summarizes the performance of the postlayout results of the main characteristics of the reported low dropout regulator and compares them with previously reported works with similar design specifications. To show the influence of V ref , the results for an ideal V ref are also included. In addition, to compare the performance between the different proposals, two figures of merit (FoM) are introduced next. FoM 1 previously defined in [27] compares the power-efficiency regulation-performance (both line and load) trade-off. It is defined as:

Discussion
where C Load is the output capacitor in pF, LNR the line regulation in mV/V, LDR the load regulation in mV/mA, I q the quiescent current in µA and I Load,max the maximum load current in mA. The factor 1000 is introduced to have FoM 1 dimensioned in (s). FoM 2 [41,42] evaluates the transient performance: where T settle is the settling time required in a full load transition.  In the two figures of merit, the smaller the value, the better the performance metric. Note that for some of the reported works in Table 1, the full load transition is from minimum current to maximum, not necessarily being from zero to maximum current. Therefore, a γ correction factor as proposed in [43] is added in both FoMs (FoM i † = γFoM i ) γ = I q + I Load,min I q (10) It takes into account the minimum I Load at which the low dropout regulator operates, thus adding to the I q the I Load,min requirement. In the same way, FoM 1 † and FoM 2 † properly evaluate the regulation performance with the effective power consumption and the transient response for a full load transition, respectively.
The proposed fully integrated 1.2 V LDO regulator with the reference voltage, V ref , embedded in the circuit reports a 5.9 µs settling time with a dynamic transient circuit with a quiescent current of 5.5 µA. It can be reduced up to 1.3 µs with the TEC increasing the total quiescent current up to 8.6 µA. It shows a good static line and load regulation, compared with the state of the art.
From FoM 1,2 † we see the reported LDO regulator presents a better performance both in terms of power efficiency-regulation trade-off and in terms of settling time-current efficiency.
Compared between the ideal and the designed reference voltage: the ideal reference voltage presents a slightly better dropout and PSR, while the temperature dependency of the designed reference voltage compensates the deviation of the core circuit reducing the overall temperature dependency. Overall, the main advantage of the ideal reference voltage is a better LNR and PSR as they are related parameters.

Conclusions
The design and postlayout simulation results of an output capacitor-less low-dropout regulator has been reported in this paper. The presented LDO regulator has been simulated in a 180 nm CMOS technology, providing a 1.2 V regulated V out from a 3.3 to 1.3 V supply voltage. It has been specifically designed to meet the constraints of battery-operated devices, with minimum power (8.6 µA) and area consumption (0.109 mm 2 ), including the voltage-independent and temperature-independent reference voltage. Compared to the state-of-art solutions, it achieves excellent transient and efficiency FoMs performances thanks to the low I q combined with dynamic transient control circuits only active during the transients.
The proposed LDO regulator is a competitive solution for the current scenario of low-power, portable on-chip devices.