Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

: Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational ampliﬁers. Two operational ampliﬁers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.


Introduction
In comparison with the mainstream bulk CMOS, CMOS FD-SOI technology [1,2] provides a set of benefits for analog circuits, such as better transconductance efficiency (g m /I D ), higher bandwidth (f T and f max ), better matching, and lower subthreshold leakage. It has also been demonstrated that FD-SOI CMOS can be a technology of choice for cryogenic integrated circuits [3,4]. However, a really unique feature of FD-SOI MOS devices is that they are double-gate transistors. The semiconductor region under the transistor channel (called similarly as in the bulk CMOS: N-well or P-well) is isolated from the channel by a buried oxide (BOX) layer and can be used as the second, namely the back gate. N-wells are isolated from the p-type substrate by a pn junction. P-wells can also be isolated from the p-type substrate by the third deep well (Figure 1). This allows for applying a bias voltage to N-wells as well as to P-wells. Back bias, i.e., voltage applied to the back gate, can be applied to each device individually or to a group of devices located over a common P-well or N-well. Back bias allows for changing the threshold voltage V T as seen by the front gate and fine tune the performance and power consumption of FD-SOI-based circuits.
It is worth noting that FD-SOI technologies can be technologies of choice for ultra-low voltage CMOS circuits. With proper back bias, the supply voltage in digital circuits can be reduced to 0.4-0.5 V. Such a reduction is more difficult in the case of analog circuits, but even without it, the maximal supply voltages in industrial deep submicron FD-SOI technologies are at the level of 0.8-1 V.
While in digital circuits back bias is applied as a constant (but often variable) voltage, in analog circuits, AC signals can be applied to the back gate as well (see, e.g., [5][6][7]). This creates new opportunities for analog circuit design. However, in the majority of analog circuits published so far, back biasing is used in a similar way as in digital circuits-to enhance or the tune circuit performance by means of DC forward or reverse back bias (see, e.g., four amplifiers [8][9][10][11]).
It has been shown experimentally in [7] that a negative feedback loop between the output and the back gate of one of the input transistors can very effectively linearize the characteristics of an operational amplifier. This paper extends the results published in [7] in the following ways: it provides a theoretical analysis of this linearization technique, including its limitations, in Section 2, and Section 3 also describes another amplifier, in which this linearization technique was used. In Section 3, the characteristics of these two opamps designed and fabricated in 22 nm FD-SOI technology are compared with theory. It is also shown how this linearization technique affects the frequency response and variability of the amplifiers. Conclusions and possible extensions of this linearization technique are presented in Section 4.

Opamp Linearization Technique: The Concept and Theory
Many methods of linearization of operational amplifiers' characteristics, applicable to bulk CMOS technologies, have been proposed, see, e.g., [12][13][14][15][16][17][18][19]. In this paper, a technique is proposed that is specific to CMOS FD-SOI: a negative feedback loop between the output of the opamp and the back gate of one of the transistors in the input differential pair, see Figure 2. The front gates of the devices of the input differential pair are driven by the input voltage v in and the back gates of these devices are driven by the output voltage v out . The output voltage of the input differential pair v 1 is given by where g mf is the transconductance related to the front gate of M2; g mb is the transconductance related to the back gate of M2; and g ds2 and g ds4 are output conductances of M2 and M4, respectively. The output voltage of the input differential pair is amplified by the second stage with voltage gain k u2 : This gives the voltage gain k u of the amplifier with the feedback loop It can be safely assumed that (g ds2 + g ds4 )/k u2 g mb . As a result, the voltage gain k u can be approximated with good accuracy by This small signal analysis suggests the necessary linearity condition of the feedback loop. The ratio g m f /g mb must be constant in the whole range of gate voltages at the front and back gates V GSf and V GSb and the drain current I D of the input transistors. This condition is satisfied when the input transistors work in a weak inversion region for all combinations of the front and back gate voltages. In the weak inversion, the transconductance efficiency g m /I D is constant. It is demonstrated in [20] that both transconductance efficiencies g m f /I D and g mb /I D are constant in a weak inversion. As the drain current is, of course, the same for both gates, g mf and g mb are proportional to each other and their ratio is constant.
In Section 3, the properties of two simple OTA (operational transconductance amplifier)-type amplifiers, to be used for the acquisition of biological signals, are discussed. They have been designed and fabricated in an industrial 22 nm FD-SOI technology. Their properties will be discussed in three configurations ( Figure 3). In these schematic diagrams, VGND is the virtual ground. The voltage at this node equals 0.5V DD . FB is the connection to the back gate of the transistor M1. In the first configuration ( Figure 3a, direct feedback configuration) the output voltage is applied directly to the body of M1, as in Figure 2. In the second configuration ( Figure 3b, feedback with voltage divider), the output voltage applied to the body of M1 is reduced by a voltage divider R 1 -R 2 . This is equivalent to a reduction of g mb in (4) by R 2 /(R 1 + R 2 ). If (g ds2 + g ds4 )/k u2 g mb R 2 /(R 1 + R 2 ), the voltage gain is as follow: The voltage divider can be used to adjust the voltage gain to any value between the minimal gain (3) and the maximal gain that is obtained without direct feedback, i.e., when no output signal is applied to the back gate of the input transistor. The maximal gain is given by From (3) and (6), a general expression for the voltage gain, in terms of the minimal gain k umin and maximal gain k umax , is obtained where it is assumed that the minimal voltage gain is given by (4) with sufficient accuracy.
As it will be shown in the next section, the minimal gain of the amplifiers discussed in this paper is quite small. It is sufficient for the purpose for which these amplifiers were designed, but for other applications, a much higher gain may be needed. A higher gain can be obtained with the voltage divider R 1 -R 2 (see (5) where (R 1 + R 2 )/R 2 is always larger than 1); however, a reduction of the feedback signal by the divider results in a reduced range of linearity of the response of the amplifier. When R 1 is very large, k u reaches k umax and the linearization effect vanishes.
It is worth noting here that bulk-driven CMOS circuits, i.e., the circuits in which AC signals are applied to the bodies of the MOS devices, are well known [17][18][19][21][22][23][24][25][26]. However, in bulk CMOS technologies, the linearization technique described here would not be possible. The body (either N-well or P-well) of a MOS device in bulk CMOS technologies is separated from the channel by the depletion region, not by BOX dielectric, and by pn junctions from the source and drain regions. This limits the range of voltages that can be applied to the body because reverse bias of the body vs. the channel means that the source and drain must be maintained.

The First Amplifier
The first amplifier is shown in Figure 4. Its supply voltage is 0.8 V. Such a low supply voltage dictates the simplest OTA-type amplifier architecture, without more than three MOS devices in series between the supply and ground. A detailed description of this amplifier, including the layout and results of the measurements (voltage gain, input offset, bandwidth, noise, and power consumption) can be found in [7]. In [7], the performance of the first amplifier is also compared with other CMOS operational amplifiers, including one that is FD-SOI based [9].
The input transistors M1 and M2 are located over P-wells isolated from the p-type substrate by deep N-wells. Electrical contacts to the wells are located in "hybrid" regions where the BOX has been removed ( Figure 1). Deep N-wells are connected to V DD1 (connection not shown in Figure 4). The voltages applied to the isolated P-wells, in particular output voltage applied to the P-well of M1, are always lower or equal to V DD . As a result, a reverse bias of all pn junctions is maintained. Figure 5a shows the simulated response of the amplifier. Simulations were performed with device models provided by the foundry. The curve labeled "direct feedback" shows the response in the direct feedback configuration (Figure 3a). For comparison, the curve labeled "external feedback" shows the response obtained in configuration with external linear negative feedback (Figure 3c). The resistances R 1 and R 2 and the bias voltage V bias were chosen in such a way that both curves match for the differential input voltage V in equal to zero. The simulated response (Figure 5a) has been confirmed experimentally. Figure 5b shows measured response in one of 50 fabricated and measured prototype chips.  The direct feedback from the output to the body of the input transistor gives a linear response extending almost "rail to rail".
Experimental results are in agreement with (4). Transconductances of M1 obtained from the simulation for the differential input voltage equal to zero are g mb = 0.523 × 10 −6 A/V, g m f = 7.64 × 10 −6 A/V. This gives k u = 14.616 V/V. The measured voltage gain (average for 49 fabricated chips [7]) is 14.5 V/V. Figure 6 shows the schematic diagram of the second amplifier. The design goal of the second amplifier ( Figure 6) was to increase the maximum output amplitude to 0.9 V. This amplifier is similar to the first one. The input stage is the same. In the output stage, transistors for 1.8 V maximum V DS and V GS were used. The supply voltage for the input stage is 0.8 V, as in the first amplifier. The voltage divider M8-M10 is the source of this voltage. Deep N-wells are connected to V DD2 (+1.8 V) (connection not shown in Figure 6). The layout of the second amplifier (Figure 7) is very similar to the layout of the first one shown in [7]. The input transistors M1-M2 (Figure 4) are visible at the upper left corner. Each transistor is divided into two connected in parallel in the common centroid configuration. Each of these four transistors is internally designed as four arrays of 100 relatively small (W/L = 10 µm/90 nm) devices. All of the other transistors are also designed as arrays of smaller devices. The big M5 (Figure 4) device can be seen as three rows of arrays of smaller transistors in the bottom part of the layout. The empty space between these rows is needed to meet the layout density rules. The big rectangle in the upper right corner is a MOM capacitor C. The divider (transistors M8-M10) and the output transistors M6A and M7A can be seen in the upper right part of the layout. Figure 8 shows the simulated response of the second amplifier. The curve labeled "direct feedback" shows the response in the direct feedback configuration (Figure 3a). For comparison, the curve labeled "external feedback" shows the response obtained in configuration with the external linear negative feedback (Figure 3c). The resistances R 1 and R 2 and the bias voltage V bias were chosen in such a way that both curves match for the differential input voltage V in equal to zero. The simulated response (Figure 8a) has been confirmed experimentally. Figure 8b shows the measured response in one of 25 fabricated and measured prototype chips. As the input stage is the same as in the first amplifier, and the operating point of M1 and M2 for the differential input voltage equal to zero is the same, the measured voltage gain (average for 25 fabricated chips) for the differential input voltage equal to zero is almost the same: 15.5 V/V. However, the linearity in the configuration with direct feedback is worse than in the case of the first amplifier. Deviation from linearity is clearly visible for the input voltages exceeding 20 mV. The reason is that the amplitude of the output voltage applied to the back gate of M1 is higher than in the case of the first amplifier. As a result, the maximum back gate voltage V GSb1 of M1 reaches 970 mV at the boundary between weak and moderate inversion.

The Second Amplifier
To improve the linearity of the response of the second amplifier, the amplitude of the voltage applied to the back gate of M1 can be reduced by means of a voltage divider, as in the configuration shown in Figure 3b. Figure 9a shows the result of a simulation with R 1 = 9.4 MΩ and R 2 = 4.7 MΩ, and Figure 9b shows the measured results in a fabricated chip. Linearity in the input voltage range from −15 mV to +15 mV is almost perfect. As shown in the previous section, the attenuation of the feedback signal by the voltage divider results in a higher voltage gain. The simulated gain k u = 46.19 V/V and measured gain k u = 46.39 V/V are in quite good agreement with (5). Figure 9 shows that with increased gain, the range of linearity of the response of the amplifier decreases. The response is no longer "almost rail to rail", as in the case of the first amplifier with direct feedback ( Figure 5).

Frequency Response
As shown in Section 2, the necessary condition of linearity is that the input transistors must work in a weak inversion region for all combinations of the voltages at the front and back gates. This is acceptable for low power amplifiers, but reduces the achievable bandwidth. An additional problem with the frequency response is that the output resistance of the output stage together with the capacitance of the back gate creates a low pass filter for the feedback signal. As a result, the amplitude of this signal decreases with frequency. This leads to a peak in the frequency response. It can be suppressed by appropriate Miller compensation. This is illustrated in Figure 10.

Variability
Direct feedback (Figure 3a) may result in a reduction of variability of the amplifier in comparison with the same amplifier with an external feedback loop (Figure 3c). The results of the Monte Carlo simulations of the response of the first amplifier (pre-layout, N = 100, nominal process corner, both process and mismatch variabilities included) are shown in Figure 11. While the nominal responses in both kinds of feedback loop (shown in Figure 5) are almost identical, the variabilities are not. It can be seen (Figure 11) that the statistical spread of the responses of the amplifier with a direct feedback loop (Figure 3a) is noticeably lower than that of the amplifier with an external feedback (Figure 3c).

Discussion and Conclusions
As the input differential pair must work in weak inversion (i.e., low drain currents), the linearization technique discussed in this paper is a good technique for low power amplifiers. The first one (Section 3.1) consumes an average of 1 µA only at 0.8 V supply voltage [7]. The second one consumes more: 58 µA at 1.8 V supply voltage. The larger current consumption is as a result of the design of the output stage ( Figure 6, larger devices M6A and M7A) and additional current consumption by the voltage divider ( Figure 6, devices M8-M10).
The advantages of this linearization technique include a very good linearity and simplicity. There are no additional devices in the case of the direct feedback configuration (Figure 3a), and in particular, no circuit components (e.g., resistors, as in the case of resistive degeneration) connected in series with the transistors in the input stage. As a result, this linearization technique is suitable for low voltage amplifiers. A reduction of variability may be an additional benefit. A voltage divider in the feedback loop (R 1 -R 2 , Figure 3b) allows for achieving the desired voltage gain (Equation (5)). These resistors can be either external or on chip. If one of them is variable (e.g., voltage-dependent), a variable gain amplifier is obtained. Of course, attenuation of the feedback signal by the voltage divider reduces the linearity range of the response of the amplifier.
The operating point in the weak inversion of the input pair devices reduces the achievable bandwidth. However, both amplifiers described in this paper were designed as front end amplifiers for the acquisition of biological signals. In this particular application, a bandwidth extending from DC to several kHz is sufficient. As it has been shown in [7], not only linearity, but also low noise, and in particular low flicker noise can be achieved.
Funding: This work was supported by THINGS2DO, an international project co-funded by the European Commission (ENIAC grant agreement 621221) and the Polish National Centre for Research and Development (agreement ENIAC C-2013-2/1/2014).

Conflicts of Interest:
The author declares no conflict of interest.

Appendix A
The figures below illustrate the 22 nm FD-SOI chips in which the amplifiers were fabricated. The chips also contain other analog blocks not discussed in this paper. As a reference, the layouts of both chips are shown. Both amplifiers are located in the upper left corners of the chips. The layouts of the amplifiers are not clearly visible on the microphotographs, they are obscured by dummy fills (a.k.a. tiles) that have been added in order to maintain a uniform density of mask shapes on all of the mask layers. This is a technology-related requirement in all nanometer CMOS circuits.