Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

: Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and ﬂuctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor ﬁeld-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current ﬂows at the interface of different materials, such as SiO 2 /Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must ﬁrst understand their characteristics statistically, and then, sufﬁcient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s ﬁndings are presented.


Introduction
Semiconductor devices have been basically progressed with the shrinking of MOSFETs (metal-oxide-semiconductor field-effect-transistors), which are used as the key component in them. The shrinkage has been performed following the rule of the constant electric field in MOSFETs, which decreases signal voltage [1,2]. In addition, power consumption of electronic devices has skyrocketed because the amount of digital data generated is growing at a rate faster than Moor's law [3,4]. The reduction of power consumption strongly requires decreasing supply voltage of MOSFETs because power consumption (P) is proportional to the square of the supply voltage (V dd ) as follows [5].
where C L represents the load capacitor and f represents the switching frequency of the circuit. The growth of clock frequency in the leading edge logic devices has stopped by exceeding the heat extraction capability. However, the downscaling has been continued to reduce the cost. In the other devices, the downscaling the device size has also been continued to reduce the power consumption and the other reasons. As a result, as the device size is reduced, the signal voltage of MOSFETs decreases. Memory devices' power consumption and supply voltage also have to be reduced [6][7][8][9] because of the same reasons as the logic devices and reducing a leakage current. On the other hand, a decrease in signal voltage degrades the reliability of electronic circuits, including analog and digital devices. The logic (bit) error rate (LER) is given by the following equation.
where P 0 and P 1 represent the probabilities of signals "0" and "1", respectively, α represents the identification level between "0" and "1", and f 0 (x) and f 1 (x) represent noise amplitude where A S represents the signal amplitude and σ represents the standard deviation of the noise. When P 0 = P 1 = 1/2 and α = A S /2 are assumed, the LER is given by the following equation from Equations (2) and (3).
When Nyquist transmission rate is the same as the signal band, the signal to noise (S/N) ratio (dB) is given by the following equation.
where E b and N 0 represent signal and noise energy per second, respectively. From Equations (4) and (6), the LER is given by the S/N ratio as follows [10]. Figure 1 shows the LER as a function of S/N (dB) and A/σ ratios [10]. The LER decreases with an increase in S/N (A S /σ) ratio. On the other hand, to guarantee that a system does not make a mistake even once during the operation period, the LER should be reduced as shown in the following equation.
LER ≤ 1 N L × F × T (8) where N L , F, and T represent the number of logic gates in a chip, the number of operations per second, and the guarantee period, respectively. For example, the LER should be less than 3 × 10 −26 for a circuit with 10 8 logic gates, 10 9 Hz operations, and a 10-year (3 × 10 8 s) operation period, and then the S/N (A S /σ) ratio should be greater than 26.5 dB (21.1).
where AS represents the signal amplitude and σ represents the standard deviation of the noise. When P0 = P1 = 1/2 and α = AS/2 are assumed, the LER is given by the following equation from Equations (2) and (3).
When Nyquist transmission rate is the same as the signal band, the signal to noise (S/N) ratio (dB) is given by the following equation.
where Eb and N0 represent signal and noise energy per second, respectively. From Equations (4) and (6), the LER is given by the S/N ratio as follows [10]. LER = 1 2 erfc 1 2√2 10 (7) Figure 1 shows the LER as a function of S/N (dB) and A/σ ratios [10]. The LER decreases with an increase in S/N (AS/σ) ratio. On the other hand, to guarantee that a system does not make a mistake even once during the operation period, the LER should be reduced as shown in the following equation.
LER ≤ 1 N × F × T (8) where NL, F, and T represent the number of logic gates in a chip, the number of operations per second, and the guarantee period, respectively. For example, the LER should be less than 3 × 10 −26 for a circuit with 10 8 logic gates, 10 9 Hz operations, and a 10-year (3 × 10 8 s) operation period, and then the S/N (AS/σ) ratio should be greater than 26.5 dB (21.1). For example, we consider signal electrons required from a no error operation. Figure 2 shows (a) Variation in the number of electrons as a function of the number of signal electrons. (b) Logic error rate as a function of the number of signal electrons. When a signal is constructed by a constant number of electrons (N e ), the standard deviation of the number of electrons is (N e ) 1/2 , and then the A/σ ratio is (N e ) 1/2 . As a result, the number of electrons must be greater than 445 to maintain an S/N (A S /σ) ratio of 26.5 dB (21.1). If the number of signal electrons is 1, the LER must be equal to 0.3. Then, such a system produces the wrong output once every three calculations.
Electronics 2021, 10, x FOR PEER REVIEW 3 of 25 For example, we consider signal electrons required from a no error operation. Figure  2 shows (a) Variation in the number of electrons as a function of the number of signal electrons. (b) Logic error rate as a function of the number of signal electrons. When a signal is constructed by a constant number of electrons (Ne), the standard deviation of the number of electrons is (Ne) 1/2 , and then the A/σ ratio is (Ne) 1/2 . As a result, the number of electrons must be greater than 445 to maintain an S/N (AS/σ) ratio of 26.5 dB (21.1). If the number of signal electrons is 1, the LER must be equal to 0.3. Then, such a system produces the wrong output once every three calculations. The electronic circuit will be influenced by noise, such as thermal noise, quantum noise, and flicker noise. The noise voltage (vnf) in 1/f noise is defined by the following equation where KF represents the flicker noise coefficient, fL~fH is the frequency period for device operation, COX, L, and W represent the gate oxide capacitance, gate length, and gate width of a MOSFET, respectively. Noise increases with device shrinkage because vnf is inversely proportional to C LW [11][12][13][14]. It has been pointed out that 1/f noise may influence not only analog devices, but also digital devices when device shrinkage and the decreasing signal voltage are moved on [15]. Random telegraph noise (RTN), another low-frequency noise also affects electronic devices, such as CMOS image sensor [16][17][18][19][20][21], static random access memory (SRAM) [22][23][24][25], dynamic random access memory (DRAM) [25], and flash memory [26][27][28][29][30][31][32]. Low-frequency noise, such as 1/f noise and RTN, have high variability [33,34] because they must be statistical phenomena by nature, and statistical analysis is required to fully understand this phenomenon. The conventional evaluations of the noise in MOSFETs have performed with a few sample numbers, and then we could understand only typical noise characteristics of MOSFETs having relatively large noise. However, we need statistical information of the noise for the design of LSI. Then, low-frequency noise statistical evaluation methods and evaluation results are described in this study.

Test Pattern for Noise Evaluation
The test structure is constructed using 0.22 μm, 1-poly 2-metal standard CMOS technology and includes n-MOSFETs of various gate sizes [35][36][37][38] as shown in Table 1. The The electronic circuit will be influenced by noise, such as thermal noise, quantum noise, and flicker noise. The noise voltage (v nf ) in 1/f noise is defined by the following equation.
where K F represents the flicker noise coefficient, f L~fH is the frequency period for device operation, C OX , L, and W represent the gate oxide capacitance, gate length, and gate width of a MOSFET, respectively. Noise increases with device shrinkage because v nf is inversely proportional to √ C OX LW [11][12][13][14]. It has been pointed out that 1/f noise may influence not only analog devices, but also digital devices when device shrinkage and the decreasing signal voltage are moved on [15]. Random telegraph noise (RTN), another lowfrequency noise also affects electronic devices, such as CMOS image sensor [16][17][18][19][20][21], static random access memory (SRAM) [22][23][24][25], dynamic random access memory (DRAM) [25], and flash memory [26][27][28][29][30][31][32]. Low-frequency noise, such as 1/f noise and RTN, have high variability [33,34] because they must be statistical phenomena by nature, and statistical analysis is required to fully understand this phenomenon. The conventional evaluations of the noise in MOSFETs have performed with a few sample numbers, and then we could understand only typical noise characteristics of MOSFETs having relatively large noise. However, we need statistical information of the noise for the design of LSI. Then, lowfrequency noise statistical evaluation methods and evaluation results are described in this study.

Test Pattern for Noise Evaluation
The test structure is constructed using 0.22 µm, 1-poly 2-metal standard CMOS technology and includes n-MOSFETs of various gate sizes [35][36][37][38]  A schematic block diagram of a test pattern is shown in Figure 3a [35,37,39,40]. This is composed of MOSFETs measured in arrayed unit cells, vertical and horizontal shift registers for addressing measured MOSFETs, MOSFETs located on each column for current control of measured MOSFET, analog memories for storing the source voltage of the measured MOSFETs within one line, and a source follower circuit for amplifying the output signal. The drain (V D ) and gate (V G ) voltage in measured MOSFETs and the gate voltage applied to current source MOSFETs (V REF ) are supplied from the external voltage source simultaneously. V DD and V SS are the supply voltages in the peripheral circuits and ground voltage, respectively. The measured MOSFET and current source transistor construct a source follower circuit using a select transistor. This test structure uses simple peripheral circuits. Therefore, it can be used to evaluate various MOSFETs with varying gate lengths, gate widths, gate insulator films, thicknesses, and other characteristics. Figure 3b shows the circuit schematic of a unit cell and current source transistor in Figure 1, which is the principle of this measurement. A unit cell is constructed with a measured MOSFET and a select transistor. When the current source transistor operates at a saturation region, I REF is independent of the voltage between the source and drain in the current source transistor (V out ). When the gate bias of the select transistor (Φ x ) is applied from a vertical shift register, I REF flows into the measured MOSFET. The output voltage (V out ) is indicated as follows.
where R select is the channel resistance of the select switch transistor. The select transistor must be operated in the linear region to have sufficient high channel conductivity compared with the measured MOSFET, and then, I REF ·R select can be neglected. The output signal can be obtained as a source voltage for each measured MOSFET by shift register scanning, and then 1.2 million MOSFETs can be measured within approximately 0.7 s. The electrical characteristics of the measured MOSFETs can be observed as the V gs included in the output voltage V out (Figure 3b). In this frame measurement mode, each MOSFET can be measured every 0.7 s. This test pattern has another measurement mode, which can measure a specific MOSFET every 1 µs.

Extraction of Amplitude and Time Constant of RTN
Two-level type RTN is characterized by only three parameters, which are the mean time to capture (<τc>), mean time to emission (<τe>), and amplitude (ΔVgs). The time constants correspond to two physical states of a trap, that is, τc and τe represent spans in a low Vgs level (carrier trapping state) and high Vgs level (carrier emission state), respectively ( Figure 4a). The RTN amplitude ΔVgs is defined as the difference between two normal distributions in a voltage histogram (Figure 4b). We extract the time constants by fitting the distributions of τc and τe to the exponential distribution (Ae −t/<τ> ) because the phenomenon is governed by the Poisson process. The time constants can be extracted with μs accuracy using the specific MOSFET measurement mode.

Extraction of Amplitude and Time Constant of RTN
Two-level type RTN is characterized by only three parameters, which are the mean time to capture (<τ c >), mean time to emission (<τ e >), and amplitude (∆V gs ). The time constants correspond to two physical states of a trap, that is, τ c and τ e represent spans in a low V gs level (carrier trapping state) and high V gs level (carrier emission state), respectively ( Figure 4a). The RTN amplitude ∆V gs is defined as the difference between two normal distributions in a voltage histogram (Figure 4b). We extract the time constants by fitting the distributions of τ c and τ e to the exponential distribution (Ae −t/<τ> ) because the phenomenon is governed by the Poisson process. The time constants can be extracted with µs accuracy using the specific MOSFET measurement mode.  The time constant ratio <τe>/<τc> is also an important parameter in RTN because the energy level of a trap that causes RTN is related to the constant ratio as follows [12,[41][42][43].
where ET and EF represent the energy of the trap and Fermi energy of the channel, respectively; k, T, and g represent Boltzmann constant, temperature, and degeneracy factor, re- The time constant ratio <τ e >/<τ c > is also an important parameter in RTN because the energy level of a trap that causes RTN is related to the constant ratio as follows [12,[41][42][43]. (11) where E T and E F represent the energy of the trap and Fermi energy of the channel, respectively; k, T, and g represent Boltzmann constant, temperature, and degeneracy factor, respectively, where g is assumed to 1. Then, the energy of the trap level is indicated by (12).
We can use the frame measurement mode to extract the time constant ratio, and the 1.2 million MOSFETs can be measured 10,000 times in 7000 s (sampling period = 0.7 s). An average of the time constant ratio <τ e >/<τ c > is the same as Count-L/Count-H (shown in Figure 4b), where Count-L and count-H are the numbers of low and high states, respectively [41][42][43][44]. When the time constant is greater than a sampling frequency of 0.7 s, the detected number of transition times is the same as the transition time of RTS characteristics. However, when the time constant is less than 0.7 s, the detected number of transition times is less than the real one; however, it is proportional to the real one because the absolute value of the time constant, which is less than the sampling frequency, cannot be extracted in this measurement. Then, the number of transition times is defined as the detected ones in the sampling frequency of 0.7 s.

Root Mean Square of RTN Waveform
The root mean square (RMS) of the signal waveform is often used for the representative parameter of noise [45], and the RMS of the output voltage V RMS is defined as follows in this study.
where V out,i , V out , N, and A are the output voltage at ith sampling, average of V out , sampling numbers, and the amplitude of two-state RTN, respectively. Using V RMS , we can obtain MOSFETs with high noise from many measured MOSFETs. Figure 5 shows the relationship between V RMS and RTN waveform. The waveform with large RTN corresponds to large V RMS .

Root Mean Square of RTN Waveform
The root mean square (RMS) of the signal waveform is often used for the representative parameter of noise [45], and the RMS of the output voltage VRMS is defined as follows in this study.
where V , , V , N, and A are the output voltage at ith sampling, average of V , sampling numbers, and the amplitude of two-state RTN, respectively. Using VRMS, we can obtain MOSFETs with high noise from many measured MOSFETs. Figure 5 shows the relationship between VRMS and RTN waveform. The waveform with large RTN corresponds to large VRMS.

Statistical Evaluation of RTN Characteristics
The 1/f noise increases with downscaling of MOSFETs, as mentioned above, and RTN also increase with the downscaling [12,36,37]. Figure 6 shows the Gumbel plot of VRMS for

Statistical Evaluation of RTN Characteristics
The 1/f noise increases with downscaling of MOSFETs, as mentioned above, and RTN also increase with the downscaling [12,36,37]. Figure 6 shows the Gumbel plot of V RMS for the various MOSFET sizes [36,37]. A large V RMS can be observed in small-size MOSFETs (L/W = 0.22/0.28, 0.22/0.3, 0.24/0.3 µm). In this experiment, noise cannot be observed in large MOSFETs because the floor noise is relatively high at~2.5 mV.

Statistical Evaluation of RTN Characteristics
The 1/f noise increases with downscaling of MOSFETs, as mentioned above, and RTN also increase with the downscaling [12,36,37]. Figure 6 shows the Gumbel plot of VRMS for the various MOSFET sizes [36,37]. A large VRMS can be observed in small-size MOSFETs (L/W = 0.22/0.28, 0.22/0.3, 0.24/0.3 μm). In this experiment, noise cannot be observed in large MOSFETs because the floor noise is relatively high at ~2.5 mV.   [39]. The data in (a) and (b) were measured by the frame and specific MOSFET measurement modes, respectively. The number of MOSFETs with large noise increases with decreasing I DS , which is controlled by V gs . This means that the event probability of large noise increases with decreasing V gs because the number of channel electrons decreases with decreasing V gs , and then the effect of a trapped electron charge becomes large with decreasing number of channel electrons. The number of channel electrons also decreases with the shrinkage of transistor size shown in Figure 6, and then, the probability increases with decreasing channel size. Figure 7b shows the waveform of typical MOSFETs for I DS of 0.13, 0.38, and 1.3 µA [39]. The time constants and amplitude are modulated by I DS . With increasing I DS (V gs ), amplitude and τ c decrease, whereas τ e slightly increases. An increase in V gs decreases E T -E F , and then, the time to capture decreases as shown in Equation (11). The difference between the modulation of τ e and τ c is discussed later. The modulation of amplitude is caused by a decrease in the number of electrons, as discussed above. It is considered that decreasing the time to capture and increasing amplitude with decreasing V gs increases the event probability of large noise. Figure 8a shows the Gumbel plot of V RMS for the various back bias (V BS ). V BS varied from −0.075 to −1.38 V, and Figure 8b shows the waveform of typical MOSFETs for V BS of 0.6 1.0 and 1.3 V [39]. The probability increases with the absolute value of V BS in (a). In this experiment, I DS was constant at 1.0 µA, and this means that the number of electrons was almost the same for each V BS . Increasing V BS caused channel percolation [46][47][48][49], making the channel thickness narrow and percolated and increasing electron energy [50]. The probability is increased by channel percolation [46,47], and the varying electron energy modulates the time constants. In MOSFETs with RTN, the amplitude does not increase with increasing V BS because the number of electrons is the same for each V BS . This means that channel percolation increases the probability of RTN generation. lute value of VBS in (a). In this experiment, IDS was constant at 1.0 μA, and this means that the number of electrons was almost the same for each VBS. Increasing VBS caused channel percolation [46][47][48][49], making the channel thickness narrow and percolated and increasing electron energy [50]. The probability is increased by channel percolation [46,47], and the varying electron energy modulates the time constants. In MOSFETs with RTN, the amplitude does not increase with increasing VBS because the number of electrons is the same for each VBS. This means that channel percolation increases the probability of RTN generation.  Figure 9 shows the Gumbel plot of the RTN amplitude for MOSFETs with varying channel doping [51]. The channel percolation is accelerated by increasing channel doping concentration [46][47][48]. This figure shows that the probability of the number of MOSFETs with large amplitude increases with doping concentration. RTN is increased by channel  Figure 9 shows the Gumbel plot of the RTN amplitude for MOSFETs with varying channel doping [51]. The channel percolation is accelerated by increasing channel doping concentration [46][47][48]. This figure shows that the probability of the number of MOSFETs with large amplitude increases with doping concentration. RTN is increased by channel doping as well as doping the concentration near the source and drain regions. Figure 10 shows the Gumbel plot of V RMS for various Halo implantation concentrations [52]. The number of MOSFETs with large RTN increases with an increase in Halo implantation concentration. This indicates that the high dose in the channel region or near the source/drain region results in high RTN because of channel percolation enhancement.  Figure 9 shows the Gumbel plot of the RTN amplitude for MOSFETs with varying channel doping [51]. The channel percolation is accelerated by increasing channel doping concentration [46][47][48]. This figure shows that the probability of the number of MOSFETs with large amplitude increases with doping concentration. RTN is increased by channel doping as well as doping the concentration near the source and drain regions. Figure 10 shows the Gumbel plot of VRMS for various Halo implantation concentrations [52]. The number of MOSFETs with large RTN increases with an increase in Halo implantation concentration. This indicates that the high dose in the channel region or near the source/drain region results in high RTN because of channel percolation enhancement.   Figure 11 shows the energy band diagrams and energy distribution of traps causing RTN for Vgs of 0.57, 0.53, and 0.46 V, respectively [41,42]. The difference between ET and EF for electrons is calculated using Equation (11). The blue shading and red solid bars in Figure 11 show the energy distribution of traps causing RTN in each measurement condition and common traps in all conditions, respectively. Although the shape of the distribution of each Vgs is almost the same, and the energy of common traps in all Vgs increases with decreasing Vgs. The conduction band edge (EC), the bottom sub-band energy (Esub), and 2nd sub-band energy (E2nd) in the inversion layer and EF are indicated in Figure 11 [50]. The energy levels of sub-bands were calculated using Equation (14) [50].
where Es is the electric field, h and mx represent Planck's constant and effective mass of electrons, respectively. Ej is jth sub-band energy, and Esub and E2nd represent E0 and E1, respectively. The main energy distribution for each Vgs locates higher energy than the conduction band edge. It is considered that the energy level of traps is widely distributed, and the energy of the detected traps is determined by the electron energy in Esub and E2nd. Conversely, the energy of common traps in all Vgs increases with decreasing Vgs because  Figure 11 shows the energy band diagrams and energy distribution of traps causing RTN for V gs of 0.57, 0.53, and 0.46 V, respectively [41,42]. The difference between E T and E F for electrons is calculated using Equation (11). The blue shading and red solid bars in Figure 11 show the energy distribution of traps causing RTN in each measurement condition and common traps in all conditions, respectively. Although the shape of the distribution of each V gs is almost the same, and the energy of common traps in all V gs increases with decreasing V gs . The conduction band edge (E C ), the bottom sub-band energy (E sub ), and 2nd sub-band energy (E 2nd ) in the inversion layer and E F are indicated in Figure 11 [50]. The energy levels of sub-bands were calculated using Equation (14) [50].
respectively. The main energy distribution for each V gs locates higher energy than the conduction band edge. It is considered that the energy level of traps is widely distributed, and the energy of the detected traps is determined by the electron energy in E sub and E 2nd . Conversely, the energy of common traps in all V gs increases with decreasing V gs because the influence of trap energy on V gs is larger than that of electron energy in the channel.
with decreasing Vgs. The conduction band edge (EC), the bottom sub-band energy (Esub), and 2nd sub-band energy (E2nd) in the inversion layer and EF are indicated in Figure 11 [50]. The energy levels of sub-bands were calculated using Equation (14) [50].
where Es is the electric field, h and mx represent Planck's constant and effective mass of electrons, respectively. Ej is jth sub-band energy, and Esub and E2nd represent E0 and E1, respectively. The main energy distribution for each Vgs locates higher energy than the conduction band edge. It is considered that the energy level of traps is widely distributed, and the energy of the detected traps is determined by the electron energy in Esub and E2nd. Conversely, the energy of common traps in all Vgs increases with decreasing Vgs because the influence of trap energy on Vgs is larger than that of electron energy in the channel.

Multi-State RTN
Large V RMS RTN includes both two-state and multi-state RTN [34,[53][54][55][56], which is considered to be generated by multi-traps. The analysis of trap characteristics, such as time constants and amplitude, in multi-state RTN is more difficult than that of two-state. Figure 12 shows the appearance probability of RTN with two, three, four, and more than four states. A large RTN (V RMS > 680 µV) was obtained by a frame measurement mode of the sampling period of 0.7 s/frame in I DS = 1 µA. 131,072 MOSFETs (L/W = 0.22/0.28 µm) were measured, and 2575 MOSFETs with large V RMS can be extracted. Then, we selected MOSFETs with large RTN and measured them by a specific measurement mode of a sampling period of 1 µs and a long sampling time of 10 min (sampling points = 6 × 10 8 ) for the same bias condition [57,58]. Figures 13-15 show the (a) waveform, (b) time lag plot (TLP), and (c) histogram for typical three-, four-, and six-state RTN. The number of peaks and the transition of each state can be understood via TLP [53,54,56].

Multi-State RTN
Large VRMS RTN includes both two-state and multi-state RTN [34,[53][54][55][56], which is considered to be generated by multi-traps. The analysis of trap characteristics, such as time constants and amplitude, in multi-state RTN is more difficult than that of two-state. Figure 12 shows the appearance probability of RTN with two, three, four, and more than four states. A large RTN (VRMS > 680 μV) was obtained by a frame measurement mode of the sampling period of 0.7 s/frame in IDS = 1 μA. 131,072 MOSFETs (L/W = 0.22/0.28 μm) were measured, and 2575 MOSFETs with large VRMS can be extracted. Then, we selected MOSFETs with large RTN and measured them by a specific measurement mode of a sampling period of 1 μs and a long sampling time of 10 min (sampling points = 6 × 10 8 ) for the same bias condition [57,58]. Figures 13-15 show the (a) waveform, (b) time lag plot (TLP), and (c) histogram for typical three-, four-, and six-state RTN. The number of peaks and the transition of each state can be understood via TLP [53,54,56].   [53,54,56]. Figures 13-15b show the relationship of ith and (i + 10)th Vgs for the constant IDS. As shown in Figure 13b, transitions occur not from the lowest state to the highest state, but only via the medium state. When the trapping probability of some traps is even, the number of states should be even, and the transition from one position to the next can occur. To begin with, an odd number of states implies that the trapping probability for each trap is not independent of each other. A similar that the trapping probability for each trap is not independent of each other. A similar transition phenomenon occurs even in a four-state case. As shown in Figure 14b, transitions did not occur from the lowest state to the highest state or from the second-lowest state to the second-highest state. This also means that there are more than two traps, and the probability of trapping for each trap is not independent of each other. The characteristics of multi-trap RTN can be understood via TLP and waveforms [56]; however, these analyses become more difficult as the number of states increases.

Time Constants in Individual RTN
As the extraction of multi-trap phenomena is difficult, as discussed in Section 3.2, we discuss the time constants and amplitude only in two-state RTN [59]. Figure 16 shows (a) τc and (b) τe as a function of IDS, respectively. These data are measured at IDS of 0.1, 0.3, 1.0, 3.0, and 5.0 μA. The data in Figure 16 show how parameters from all two-level RTN can be extracted in common under four or five IDS, and thus, the number of selected data points was 22.

Time Constants in Individual RTN
As the extraction of multi-trap phenomena is difficult, as discussed in Section 3.2, we discuss the time constants and amplitude only in two-state RTN [59]. Figure 16 shows (a) τc and (b) τe as a function of IDS, respectively. These data are measured at IDS of 0.1, 0.3, 1.0, 3.0, and 5.0 μA. The data in Figure 16 show how parameters from all two-level RTN can be extracted in common under four or five IDS, and thus, the number of selected data points was 22.   [53,54,56]. Figures 13, 14 and 15b show the relationship of ith and (i + 10)th V gs for the constant IDS. As shown in Figure 13b, transitions occur not from the lowest state to the highest state, but only via the medium state. When the trapping probability of some traps is even, the number of states should be even, and the transition from one position to the next can occur. To begin with, an odd number of states implies that the trapping probability for each trap is not independent of each other. A similar transition phenomenon occurs even in a four-state case. As shown in Figure 14b, transitions did not occur from the lowest state to the highest state or from the second-lowest state to the second-highest state. This also means that there are more than two traps, and the probability of trapping for each trap is not independent of each other. The characteristics of multi-trap RTN can be understood via TLP and waveforms [56]; however, these analyses become more difficult as the number of states increases.

Time Constants in Individual RTN
As the extraction of multi-trap phenomena is difficult, as discussed in Section 3.2, we discuss the time constants and amplitude only in two-state RTN [59]. Figure 16 shows (a) τ c and (b) τ e as a function of I DS , respectively. These data are measured at I DS of 0.1, 0.3, 1.0, 3.0, and 5.0 µA. The data in Figure 16 show how parameters from all two-level RTN can be extracted in common under four or five I DS , and thus, the number of selected data points was 22.

Time Constants in Individual RTN
As the extraction of multi-trap phenomena is difficult, as discussed in Section 3.2, we discuss the time constants and amplitude only in two-state RTN [59]. Figure 16 shows (a) τc and (b) τe as a function of IDS, respectively. These data are measured at IDS of 0.1, 0.3, 1.0, 3.0, and 5.0 μA. The data in Figure 16 show how parameters from all two-level RTN can be extracted in common under four or five IDS, and thus, the number of selected data points was 22.    (I DS ). τ c /τ e and E T -E F are calculated from the data in Figure 16 and Equation (12), respectively. τ c and τ e decrease and increase with an increase in I DS (V GS ), and the absolute slope of τ c is significantly larger than that of τ e . Large trap energy (E T ) decreases with an increase in V GS than that of channel electron (E C : bottom energy of conduction band). Then, with increasing V GS (I DS ), the energy barrier from the channel electron to the trap decreases and that from the trapped electron to the channel increases. As a result, the time to capture and time to emission decreases and increases, respectively, with increasing V GS (I DS ). The transition probability depends on the energy barrier height between a trap and channel. τ e depends only on the energy barrier because only one electron is captured in a trap. Meanwhile, τ c depends not only on the energy barrier, but also on the number of electrons in a channel because the number of channel electrons increases as V GS (I DS ) increases. Then, the dependency of τ c on I DS is more significant than that of τ e . E T -E F in Figure 17 changed by approximately 175 mV during I DS (V GS ) from 0.1 (0.53V) to 5.0 µA (0.75V). Based on these values, E T -E F changes by 0.18 V, whereas V GS changes by 0.22 V. The distance between the traps and the channel was 4.6 nm due to the gate oxide thickness of 5.7 nm. However, τ c depends not only on the trap energy, but also on the number of channel electrons; thus, E T -E F values cannot be calculated using Equation (12). The distance is considered to be shorter than the calculated value. τ e values for almost all samples monotonically increased with increasing I DS . This suggests that the distance from the trap to the channel is shorter than that to the gate electrode. The distance between the trap and channel is shorter than 2.85 nm, which is the center of the gate oxide thickness. Figure 18a,b show the amplitude and transition frequency as a function of I DS for the same samples as those in Figures 16 and 17, respectively. For a sufficiently long measuring period, the transition frequency (TF) was calculated using the following equation.
The amplitude decreases and the TF increases with an increase in IDS for almost all samples. This is caused by the increase in the number of channel electrons as IDS increases. However, the amplitude and TF of some samples did not exhibit monotony, which is due to the percolation channel effect [46][47][48][49]. The distance between the channel and trap changes as IDS (VGS) changes because of the formation of the percolation channel.  Figure 16 and Equation (12), respectively. . τ c /τ e and E T -E F are calculated from the data in Figure 16 and Equation (12), respectively.  Figure 19 shows the Gumbel plot of the VRMS for 18,048 MOSFETs. IDS varied from 0.1 to 20 μA. The floor noise in this experiment was smaller than the others and was approximately 35 μVRMS [60]. In Figure 7, VRMS decreases with an increase in IDS for all VRMS. In Figure 19, larger VRMS can also be observed in small IDS in relatively large VRMS regions. However, the higher appearance probability in large IDS than that in small IDS for the small VRMS region of less than 500 μV could not be observed in Figure 7 because the floor noise was approximately 1 mV in that experiment. The amplitude characteristics are the same as the VRMS characteristics, and the distribution of the time constants is the same for all conditions [60]. Figure 20 shows the frequency of RTN with two, three, and more than three states in 18,048 MOSFETs. The frequency of all states increases with IDS.

Effect of Drain Current on Appearance Probability and Amplitude
It is assumed that the probability that electrons and percolation paths are close to each other increases as IDS increases, increasing the number of electrons in the channel and the number of percolation paths. Figure 21 shows the Gumbel plot for the amplitude of two-state RTN. Notably, frequency sometimes increases with an increase in IDS even though the effect of trapped electrons on the channel decreases with an increase in the electron density in the channel. The amplitude decreases and the TF increases with an increase in I DS for almost all samples. This is caused by the increase in the number of channel electrons as I DS increases. However, the amplitude and TF of some samples did not exhibit monotony, which is due to the percolation channel effect [46][47][48][49]. The distance between the channel and trap changes as I DS (V GS ) changes because of the formation of the percolation channel. Figure 19 shows the Gumbel plot of the V RMS for 18,048 MOSFETs. I DS varied from 0.1 to 20 µA. The floor noise in this experiment was smaller than the others and was approximately 35 µV RMS [60]. In Figure 7, V RMS decreases with an increase in I DS for all V RMS . In Figure 19, larger V RMS can also be observed in small I DS in relatively large V RMS regions. However, the higher appearance probability in large I DS than that in small I DS for the small V RMS region of less than 500 µV could not be observed in Figure 7 because the floor noise was approximately 1 mV in that experiment. The amplitude characteristics are the same as the V RMS characteristics, and the distribution of the time constants is the same for all conditions [60]. Figure 20 shows the frequency of RTN with two, three, and more than three states in 18,048 MOSFETs. The frequency of all states increases with I DS .

Effect of Drain Current on Appearance Probability and Amplitude
three states in 18,048 MOSFETs. The frequency of all states increases with IDS.
It is assumed that the probability that electrons and percolation paths are close to each other increases as IDS increases, increasing the number of electrons in the channel and the number of percolation paths. Figure 21 shows the Gumbel plot for the amplitude of two-state RTN. Notably, frequency sometimes increases with an increase in IDS even though the effect of trapped electrons on the channel decreases with an increase in the electron density in the channel.

Modulation of Time Constants
In Section 3.3, the time constants were measured under constant conditions. The differences between time constants and VRMS in continuous on-state and periodically switched conditions are discussed in this section [61]. As shown in Figure 16, VGS dependance on τc is larger than that of τe, and this suggests that the cycle period (τc + τe) in onstate is longer than that in off-state because the VGS of off-state is smaller than that of onstate. Figure 21a  It is assumed that the probability that electrons and percolation paths are close to each other increases as I DS increases, increasing the number of electrons in the channel and the number of percolation paths. Figure 21 shows the Gumbel plot for the amplitude of two-state RTN. Notably, frequency sometimes increases with an increase in I DS even though the effect of trapped electrons on the channel decreases with an increase in the electron density in the channel.

Modulation of Time Constants
In Section 3.3, the time constants were measured under constant conditions. The differences between time constants and VRMS in continuous on-state and periodically switched conditions are discussed in this section [61]. As shown in Figure 16, VGS depend-

Modulation of Time Constants
In Section 3.3, the time constants were measured under constant conditions. The differences between time constants and VRMS in continuous on-state and periodically switched conditions are discussed in this section [61]. As shown in Figure 16, V GS dependance on τ c is larger than that of τ e , and this suggests that the cycle period (τ c + τ e ) in on-state is longer than that in off-state because the V GS of off-state is smaller than that of on-state. Figure 21a,b show the time constant relationship between continuous on-state and periodically switched conditions. In the periodically switched condition, MOSFETs cycled for 10.6 msec in 700 ms, which was a measurement cycle. Although τ e of almost all samples are the same in both conditions, τ c of some samples in the periodically switched condition is larger than that in continuous on-state. Figure 22 shows (a) histogram of the V RMS difference between continuous on-state and periodically off-state (∆V RMS ) and (b) schematic waveform of RTN in continuous on-state and periodically off-state, respectively. Though V RMS of 5% samples was increased, that of 95% was not changed or decreased in the periodically switched condition. As a result, V RMS decreased in the periodically switched condition, with a few exceptions. This suggests that V RMS can be reduced by the modulation of operation conditions, even in the same MOSFET.

Device Structure Dependence of RTN
In the above results and discussions in Sections 3.1-3.5, the dependance of RTN characteristics on operation conditions is mainly described. In Section 3.6, the dependance of RTN characteristics on the structure of MOSFETs, such as buried channel MOSFETs and asymmetric source-drain structure MOSFETs, are described [57,[62][63][64][65]. Figure 23 shows the structure of buried channel MOSFETs studied in this work. To discuss the effects of n-Si layer widths and the distance between the channel and SiO2/Si interface, n-Si layer width was varied to be 0, 10, 25, and 60 nm for standard, narrow, middle, and deep samples formed by arsenic ion implantation, respectively, and the highenergy ion implantation created not only a deep channel, but also a wide channel in the vertical direction to the SiO2/Si interface. Figures 24 and 25 show the Gumbel plots of VRMS for the standard, narrow, middle, and deep samples and the VBS dependance of VRMS for the narrow, middle, and deep samples, respectively [57,65].

Device Structure Dependence of RTN
In the above results and discussions in Sections 3.1-3.5, the dependance of RTN characteristics on operation conditions is mainly described. In Section 3.6, the dependance of RTN characteristics on the structure of MOSFETs, such as buried channel MOSFETs and asymmetric source-drain structure MOSFETs, are described [57,[62][63][64][65]. Figure 23 shows the structure of buried channel MOSFETs studied in this work. To discuss the effects of n-Si layer widths and the distance between the channel and SiO 2 /Si interface, n-Si layer width was varied to be 0, 10, 25, and 60 nm for standard, narrow, middle, and deep samples formed by arsenic ion implantation, respectively, and the highenergy ion implantation created not only a deep channel, but also a wide channel in the vertical direction to the SiO 2 /Si interface. Figures 24 and 25 show the Gumbel plots of V RMS for the standard, narrow, middle, and deep samples and the V BS dependance of V RMS for the narrow, middle, and deep samples, respectively [57,65]. discuss the effects of n-Si layer widths and the distance between the channel and SiO2/Si interface, n-Si layer width was varied to be 0, 10, 25, and 60 nm for standard, narrow, middle, and deep samples formed by arsenic ion implantation, respectively, and the highenergy ion implantation created not only a deep channel, but also a wide channel in the vertical direction to the SiO2/Si interface. Figures 24 and 25 show the Gumbel plots of VRMS for the standard, narrow, middle, and deep samples and the VBS dependance of VRMS for the narrow, middle, and deep samples, respectively [57,65].    The channel length and width were 0.22 and 0.28 μm, respectively, IDS was 100 nA, and VBS in Figure 24 was −1.5 V and varied from −1.0 V to −2.0 V in Figure 25, respectively. The VRMS values for the standard and Narrow samples are the same, and the frequency of large VRMS decreases with an increase in n-Si width and/or depth. This means that RTN cannot be decreased by the 20 nm buried channel, but can be decreased by forming a buried channel of 40 nm and more. By increasing the back bias, VRMS increases for all samples, and the effect of VBS remarkably appeared for the wide sample. By applying the back bias, the channel pushes onto the SiO2/Si interface, and the channel thickness decreases. The buried channel is extremely effective for decreasing RTN because the channel is separated from SiO2/Si interface and the wide channel becomes difficult to form the percolation path. Furthermore, the buried channel MOSFET in the isolated well was employed to evaluate VBS dependance [64], and VBS   The channel length and width were 0.22 and 0.28 μm, respectively, IDS was 100 nA, and VBS in Figure 24 was −1.5 V and varied from −1.0 V to −2.0 V in Figure 25, respectively. The VRMS values for the standard and Narrow samples are the same, and the frequency of large VRMS decreases with an increase in n-Si width and/or depth. This means that RTN cannot be decreased by the 20 nm buried channel, but can be decreased by forming a buried channel of 40 nm and more. By increasing the back bias, VRMS increases for all samples, and the effect of VBS remarkably appeared for the wide sample. By applying the back bias, the channel pushes onto the SiO2/Si interface, and the channel thickness decreases. The buried channel is extremely effective for decreasing RTN because the channel is separated from SiO2/Si interface and the wide channel becomes difficult to form the percolation path. Furthermore, the buried channel MOSFET in the isolated well was employed to evaluate VBS dependance [64], and VBS The channel length and width were 0.22 and 0.28 µm, respectively, I DS was 100 nA, and V BS in Figure 24 was −1.5 V and varied from −1.0 V to −2.0 V in Figure 25, respectively. The V RMS values for the standard and Narrow samples are the same, and the frequency of large V RMS decreases with an increase in n-Si width and/or depth. This means that RTN cannot be decreased by the 20 nm buried channel, but can be decreased by forming a buried channel of 40 nm and more. By increasing the back bias, V RMS increases for all samples, and the effect of V BS remarkably appeared for the wide sample. By applying the back bias, the channel pushes onto the SiO 2 /Si interface, and the channel thickness decreases. The buried channel is extremely effective for decreasing RTN because the channel is separated from SiO 2 /Si interface and the wide channel becomes difficult to form the percolation path. Furthermore, the buried channel MOSFET in the isolated well was employed to evaluate V BS dependance [64], and V BS can be varied from 0 V in this structure because the well voltage can be changed freely. The gate length and gate width of the MOSFETs are 0.32 and 0.32 µm, respectively, I DS was 1 µA, vs. was 1.5 V, and V well of the normal well and isolated well were 0 and 1.5 V, respectively; thus, V BS was set at −1.5 and 0 V for the normal well and isolated well, respectively. Figure 26 shows the Gumbel plot of the V RMS for the buried channel and surface channel MOSFETs with the back bias conditions of 0 and −1.5 V. V RMS of the buried channel MOSFETs at V BS = −1.5 V is significantly less than those of surface channel; however, that at V BS = 0 V is larger than those of the surface channel even though those of the surface channel do not depend on V BS . Figure 27 shows the normal probability plot of the subthreshold swing for the same sample of Figure 26. The subthreshold swing of buried channel MOSFETs with V BS = 0 is much smaller than the others. A strong relationship between the subthreshold swing and V RMS has been reported [64]. The result strongly suggests that the increase in V RMS is enlarged by the physical origin, which increases the subthreshold swing, and the origin is an enhancement of the percolation path formation [64]. Note that RTN has to be enhanced by a minimal small gate control effect on the channel. Furthermore, the variability of the threshold voltage is increased using the buried channel MOSFETs; thus, we cannot introduce buried channel MOSFETs when the fixed pattern noise is critical for device performance. the increase in VRMS is enlarged by the physical origin, which increases the subthreshold swing, and the origin is an enhancement of the percolation path formation [64]. Note that RTN has to be enhanced by a minimal small gate control effect on the channel. Furthermore, the variability of the threshold voltage is increased using the buried channel MOSFETs; thus, we cannot introduce buried channel MOSFETs when the fixed pattern noise is critical for device performance.   Figure 28 shows the layout structure of rectangular and trapezoidal shape MOSFETs used in this experiment [62,63]. In the trapezoidal MOSFETs, when current flows from the left to right direction, the source has a wide gate width, and when current flows from the the increase in VRMS is enlarged by the physical origin, which increases the subthreshold swing, and the origin is an enhancement of the percolation path formation [64]. Note that RTN has to be enhanced by a minimal small gate control effect on the channel. Furthermore, the variability of the threshold voltage is increased using the buried channel MOSFETs; thus, we cannot introduce buried channel MOSFETs when the fixed pattern noise is critical for device performance.  3.6.2. Asymmetry Source and Drain Width MOSFETs Figure 28 shows the layout structure of rectangular and trapezoidal shape MOSFETs used in this experiment [62,63]. In the trapezoidal MOSFETs, when current flows from the  Figure 28 shows the layout structure of rectangular and trapezoidal shape MOSFETs used in this experiment [62,63]. In the trapezoidal MOSFETs, when current flows from the left to right direction, the source has a wide gate width, and when current flows from the right to left direction, the source has a shallow gate width. The Gumbel plots of V RMS for trapezoidal ((a)W D < W S and (b) W S < W D ) and (c) rectangular MOSFETs are shown in Figure 29 [62]. The gate width of rectangular MOSFETs was set as the average of the gate width of trapezoidal MOSFETs. I DS was varied from 0.1 to 11 µA for constant V BS of −1.9 V and V DS of 1.4 V. In (c) rectangular MOSFETs, similar phenomena, as shown in Figure 19, are obtained. In contrast, in the trapezoidal MOSFETs, V RMS increases with an increase in I DS (V GS ), and those of W D < W S are larger than those of W S < W D . V DS is larger than V GS in this experiment. MOSFETs were operated in the saturation region, and the channel formed near the source. Increasing I DS increases electron density in the channel, and the electron density at the source of MOSFETs with W D < W S is less than that with W S < W D . These characteristics indicate that the influence of a charged trap reduces at a high carrier density condition [39,60,62]. This means that the electron density and the location in the channel are important factors affecting RTN characteristics. RTN characteristics were evaluated for various V DS using rectangular and trapezoidal MOSFETs. density condition [39,60,62]. This means that the electron density and the location in the channel are important factors affecting RTN characteristics. RTN characteristics were evaluated for various VDS using rectangular and trapezoidal MOSFETs.  trapezoidal with WS < WD MOSFETs is the same, and VRMS increases as VDS increases, monotonically. The dependance of (b) trapezoidal with WS < WD on VDS is larger than that of rectangular MOSFETs. In contrast, VRMS increases with an increase in VDS at less than 0.3 V; however, VRMS decreases with an increase in VDS at >0.3V for trapezoidal MOSFETs with WS > WD. When VDS is smaller than the pinch-off voltage (VGS-VTH = 0.3 V in this experiment), the channel is uniformly formed under the gate oxide, and the channel vanishes at the drain edge at the pinch-off voltage. The vanished region expands with increasing VDS. On the other hand, IDS was set at a constant of 10 μA, and this means that VGS decreases as VDS increases at less than a pinch-off voltage of 0.3V. In rectangular MOSFETs, VRMS increases with a decrease in VGS, which is the same effect as shown in Figure 7. In trapezoidal MOSFETs with WS < WD, VDS dependance was enhanced by reducing the channel width. In trapezoidal MOSFETs with WD < WS, VDS dependance is the same as others at less VDS than a pinch-off voltage of 0.3 V. However, the opposite dependency is obtained at larger VDS than the pinch-off voltage. It is considered that the apparent gate width of MOSFETs (WD < WS) increases when the pinch-off point reaches the source, and then, the size effect of VRMS shown in Figure 6 is obtained. These data imply that the noise strength depends heavily on operation conditions, which means that the location and electron density in a channel are critical for RTN generation. density condition [39,60,62]. This means that the electron density and the location in the channel are important factors affecting RTN characteristics. RTN characteristics were evaluated for various VDS using rectangular and trapezoidal MOSFETs.  trapezoidal with WS < WD MOSFETs is the same, and VRMS increases as VDS increases, monotonically. The dependance of (b) trapezoidal with WS < WD on VDS is larger than that of rectangular MOSFETs. In contrast, VRMS increases with an increase in VDS at less than 0.3 V; however, VRMS decreases with an increase in VDS at >0.3V for trapezoidal MOSFETs with WS > WD. When VDS is smaller than the pinch-off voltage (VGS-VTH = 0.3 V in this experiment), the channel is uniformly formed under the gate oxide, and the channel vanishes at the drain edge at the pinch-off voltage. The vanished region expands with increasing VDS. On the other hand, IDS was set at a constant of 10 μA, and this means that VGS decreases as VDS increases at less than a pinch-off voltage of 0.3V. In rectangular MOSFETs, VRMS increases with a decrease in VGS, which is the same effect as shown in Figure 7. In trapezoidal MOSFETs with WS < WD, VDS dependance was enhanced by reducing the channel width. In trapezoidal MOSFETs with WD < WS, VDS dependance is the same as others at less VDS than a pinch-off voltage of 0.3 V. However, the opposite dependency is obtained at larger VDS than the pinch-off voltage. It is considered that the apparent gate width of MOSFETs (WD < WS) increases when the pinch-off point reaches the source, and then, the size effect of VRMS shown in Figure 6 is obtained. These data imply that the noise strength depends heavily on operation conditions, which means that the location and electron density in a channel are critical for RTN generation.    . The V DS dependance of V RMS for the (c) rectangular and (b) trapezoidal with W S < W D MOSFETs is the same, and V RMS increases as V DS increases, monotonically. The dependance of (b) trapezoidal with W S < W D on V DS is larger than that of rectangular MOSFETs. In contrast, V RMS increases with an increase in V DS at less than 0.3 V; however, V RMS decreases with an increase in V DS at >0.3V for trapezoidal MOSFETs with W S > W D . When V DS is smaller than the pinch-off voltage (V GS -V TH = 0.3 V in this experiment), the channel is uniformly formed under the gate oxide, and the channel vanishes at the drain edge at the pinch-off voltage. The vanished region expands with increasing V DS . On the other hand, I DS was set at a constant of 10 µA, and this means that V GS decreases as V DS increases at less than a pinch-off voltage of 0.3V. In rectangular MOSFETs, V RMS increases with a decrease in V GS, which is the same effect as shown in Figure 7. In trapezoidal MOSFETs with W S < W D , V DS dependance was enhanced by reducing the channel width. In trapezoidal MOSFETs with W D < W S , V DS dependance is the same as others at less V DS than a pinch-off voltage of 0.3 V. However, the opposite dependency is obtained at larger V DS than the pinch-off voltage. It is considered that the apparent gate width of MOSFETs (W D < W S ) increases when the pinch-off point reaches the source, and then, the size effect of V RMS shown in Figure 6 is obtained. These data imply that the noise strength depends heavily on operation conditions, which means that the location and electron density in a channel are critical for RTN generation. Although using trapezoidal MOSFETs in real electronic devices is difficult, changing the shape of MOSFETs is very useful to obtain much information about RTN characteristics. For example, the effect of trap at the isolation edge can be evaluated using octagonal MOSFETs, which have only a gate edge and no shallow trench isolation edge [62]. The roughness of the interface between the gate insulator and Si is essential for MOSFETs. The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87]. Figure 31 shows images of an atomically flat surface and as-received Si(100) measured by atomic force microscopy (AFM). The atomically flat surface was formed in the active region with shallow trench isolation and was measured after the gate oxide formation and following oxide stripping [84]. The average roughness (Ra) of the conventional surface is 0.12 nm, which is the same as the initial surface of Si(100). In an atomically flat surface, a step and terrace structure can be obtained, and the step height is the same as the monoatomic step length of Si(100) of 0.135 nm. The terrace width (L) is defined by the following equation using the off-angle (θ) to the just (100) orientation. The average roughness in the trace of the atomically flat interface was less than 0.04 nm, which is the detection limit of our AFM system. L = 0.135 tan θ nm (16) Figure 32 shows the Gumbel plot of VRMS for the atomically flat and conventional SiO2/Si interface [84]. The noise of the atomically flat interface is less than that of the conventional interface. This means that introducing the atomically flat interface is extremely effective for reducing RTN as well as 1/f noise [86][87][88]. The atomically flat surface was formed before gate oxidation in this experiment [84]. Although using trapezoidal MOSFETs in real electronic devices is difficult, changing the shape of MOSFETs is very useful to obtain much information about RTN characteristics. For example, the effect of trap at the isolation edge can be evaluated using octagonal MOSFETs, which have only a gate edge and no shallow trench isolation edge [62].

MOSFETs with Atomically Flat Gate Insulator/Si Interface
The roughness of the interface between the gate insulator and Si is essential for MOSFETs. The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87]. Figure 31 shows images of an atomically flat surface and as-received Si(100) measured by atomic force microscopy (AFM). The atomically flat surface was formed in the active region with shallow trench isolation and was measured after the gate oxide formation and following oxide stripping [84]. The average roughness (Ra) of the conventional surface is 0.12 nm, which is the same as the initial surface of Si(100). In an atomically flat surface, a step and terrace structure can be obtained, and the step height is the same as the monoatomic step length of Si(100) of 0.135 nm. The terrace width (L) is defined by the following equation using the off-angle (θ) to the just (100) orientation. The average roughness in the trace of the atomically flat interface was less than 0.04 nm, which is the detection limit of our AFM system. L = 0.135 tan θ (nm) (16)    To implement the surface flattening process, a low temperature of less than 900 °C and low oxidation species, such as O2 and H2O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88]. Other problems exist, such as STI edge shape and dopant segregation, and the solutions to these problems may affect not only MOSFET characteristics, but also noise [84]. The flattening process just before the gate oxidation is superior to the flattening process in the first step for introducing interface flattening between SiO2 and Si, and this can be obtained by low temperature Ar annealing by reducing oxidation species.

Conclusions
The importance of low-frequency noise in LSI, and various effects on RTN, such as MOSFETs' size, bias and operation conditions, and device structures, are described. The measurement technique using the array test circuit and the extraction of important parameters (time constants and amplitude) in RTN characteristics are also described. Time constants can be extracted essentially using classical equations; however, it is not as simple when downsizing MOSFETs and reducing the number of channel electrons, and the percolation path is formed. Variability of low-frequency noise increases with shrinkage of MOSFETs. In this paper, we evaluated relatively large planer MOSFETs (L = 0.22~0.4 μm), unfortunately. The size of MOSFETs has been downscaled to less than l0 nm and the structure has changed the planer to FinFET, recently. We have to continue the evaluation of such miniaturized and new structure devices. To assess the effect of this noise on  Figure 32 shows the Gumbel plot of V RMS for the atomically flat and conventional SiO 2 /Si interface [84]. The noise of the atomically flat interface is less than that of the conventional interface. This means that introducing the atomically flat interface is extremely effective for reducing RTN as well as 1/f noise [86][87][88]. The atomically flat surface was formed before gate oxidation in this experiment [84].  To implement the surface flattening process, a low temperature of less than 900 °C and low oxidation species, such as O2 and H2O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88]. Other problems exist, such as STI edge shape and dopant segregation, and the solutions to these problems may affect not only MOSFET characteristics, but also noise [84]. The flattening process just before the gate oxidation is superior to the flattening process in the first step for introducing interface flattening between SiO2 and Si, and this can be obtained by low temperature Ar annealing by reducing oxidation species.

Conclusions
The importance of low-frequency noise in LSI, and various effects on RTN, such as MOSFETs' size, bias and operation conditions, and device structures, are described. The measurement technique using the array test circuit and the extraction of important parameters (time constants and amplitude) in RTN characteristics are also described. Time constants can be extracted essentially using classical equations; however, it is not as simple when downsizing MOSFETs and reducing the number of channel electrons, and the percolation path is formed. Variability of low-frequency noise increases with shrinkage of MOSFETs. In this paper, we evaluated relatively large planer MOSFETs (L = 0.22~0.4 μm), unfortunately. The size of MOSFETs has been downscaled to less than l0 nm and the structure has changed the planer to FinFET, recently. We have to continue the evaluation of To implement the surface flattening process, a low temperature of less than 900 • C and low oxidation species, such as O 2 and H 2 O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88]. Other problems exist, such as STI edge shape and dopant segregation, and the solutions to these problems may affect not only MOSFET characteristics, but also noise [84]. The flattening process just before the gate oxidation is superior to the flattening process in the first step for introducing interface flattening between SiO 2 and Si, and this can be obtained by low temperature Ar annealing by reducing oxidation species.

Conclusions
The importance of low-frequency noise in LSI, and various effects on RTN, such as MOSFETs' size, bias and operation conditions, and device structures, are described. The measurement technique using the array test circuit and the extraction of important parameters (time constants and amplitude) in RTN characteristics are also described. Time constants can be extracted essentially using classical equations; however, it is not as simple when downsizing MOSFETs and reducing the number of channel electrons, and the percolation path is formed. Variability of low-frequency noise increases with shrinkage of MOSFETs. In this paper, we evaluated relatively large planer MOSFETs (L = 0.22~0.4 µm), unfortunately. The size of MOSFETs has been downscaled to less than l0 nm and the structure has changed the planer to FinFET, recently. We have to continue the evaluation of such miniaturized and new structure devices. To assess the effect of this noise on MOSFETs, we have to understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period.
Funding: This research received no external funding.