A New Simulated Inductor with Reduced Series Resistor Using a Single VCII ±

: This paper presents a new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII ± ) as an active building block, two resistors and one grounded capacitor. The main characteristic of the proposed circuit is that the value of the series resistor can be signiﬁcantly reduced. Thus, it has the property of improved low-frequency performance. Another feature is the use of a grounded capacitor that makes the proposed circuit attractive for integrated circuit (IC) realization. A simple CMOS implementation of the required VCII ± is used. However, a single passive component-matching condition is required for the proposed structure. As an application example, a standard ﬁfth-order high-pass ladder ﬁlter is also given. SPICE simulations using 0.18 µ m CMOS technology parameters and a supply voltage of ± 0.9 V as well as experimental veriﬁcations, are carried out to support the theory.

Here, we aim to design a VCII-based grounded SI with improved performance that uses only one ABB. The proposed circuit is based on one dual-output VCII (VCII±) as ABB, two resistors and one grounded capacitor. The most important feature of the new implementation is that the value of series impedance is considerably reduced by adjusting resistor values. Hence, it has the property of improved low-frequency performance. It employs only a grounded capacitor that results in easy integration in the IC process. In addition, the frequency range is extended to 10 MHz. Additionally, complete circuit analysis and SPICE simulation results are reported. As an application example, a fifthorder high-pass (HP) ladder filter is presented. Nevertheless, there is a simple matching condition which can be easily satisfied. Fortunately, this matching condition is also useful in setting the value of parasitic series resistance to the desired value. The promising results through the SPICE simulation program and experimental verifications show that VCIIs are highly suitable in the SI applications. Compared to the grounded SI based on the negativeimpedance converters (NICs) of [49] which employ two active elements, two resistors and one grounded capacitor, the realized inductor value is four times lower than the one extracted from the proposed circuit for the same values of the capacitor and resistors.
The organization of this paper is as follows. In Section 2, VCII± and the proposed SI are introduced and analyzed. The non-ideal analysis is performed in Section 3. Simulation results are reported in Section 4. Experimental verifications are presented in Section 5. Finally, Section 6 concludes the paper. Figure 1 shows the symbolic presentation and internal structure of the VCII± without a Z− port. It has a low-impedance current input Y terminal, two high-impedance current output X+ and X− terminals and one low impedance voltage output terminal, Z+. It simply consists of a current buffer (CB) and a voltage buffer (VB). The input current is transferred from the Y terminal to the X+ terminal in the same direction and the X− terminal in the opposite direction. The voltage at the X+ terminal is transferred to the Z+ terminal. The VCII± demonstrated in Figure 1 is described as: The proposed VCII±-based SI is shown in Figure 2. Simple analysis shows that, in the case of ideal VCII (negligible contribution of parasitic impedances), the input impedance of the proposed SI is evaluated by

The Proposed Circuit
In above equation, if R2 = R1 = R is chosen, the following input impedance is obtained: One observes from Equation (3) that a positive lossless grounded SI is obtained. If non-ideal gains are considered, Equation (2) turns to: From Equation (4), quality factor (Q) for equivalent inductance is found as In Equation (1), β and η, being current gains, are ideally equal to one and two, respectively. Additionally, α, being voltage gain, is ideally equal to unity.
The proposed VCII±-based SI is shown in Figure 2. Simple analysis shows that, in the case of ideal VCII (negligible contribution of parasitic impedances), the input impedance of the proposed SI is evaluated by The proposed VCII±-based SI is shown in Figure 2. Simple analysis shows case of ideal VCII (negligible contribution of parasitic impedances), the input i of the proposed SI is evaluated by  In above equation, if R 2 = R 1 = R is chosen, the following input impedance is obtained: One observes from Equation (3) that a positive lossless grounded SI is obtained. If non-ideal gains are considered, Equation (2) turns to: From Equation (4), quality factor (Q) for equivalent inductance is found as From Equation (5) it can be realized that for the ideal case, where R 1 = R 2 and η = 2, the Q value of the inductance is infinity.

Parasitic Impedance Effects
Figures 3 and 4 show the VCII± with its parasitic impedances and the equivalent model of the proposed SI, respectively. Thus, the VCII± denoted in Figure 3 is described as

Parasitic Impedance Effects
By a simple analysis, including only parasitic impedances of the VCII converts to: Here, Leq, req, Req and Ceq are, respectively, calculated as  It is seen from Equations (7) and (8) that the proposed SI has restrictions at high frequencies due to parasitic elements RX+ and CX+ and at low frequencies due to req. Fortunately, req can be set to zero by choosing R2 as follows: If RX− is too high (RX-> ∞), the Equation (12) is reduced to R2 = R1 + RY − RZ+, which is easily satisfied in practice.

Simulation Results
The performance of the proposed circuit of Figure 2 is tested through SPICE simulations using 0.18 μm CMOS technology parameters and a supply voltage of ±0.9 V. The resulted performance parameters for the VCII±, derived from one in Figure 5 [58], are reported in Table 1   By a simple analysis, including only parasitic impedances of the VCII±, Equation (2) converts to: Z in (s) = R eq // 1 sC eq // sL eq + r eq (7) Here, L eq , r eq , R eq and C eq are, respectively, calculated as It is seen from Equations (7) and (8) that the proposed SI has restrictions at high frequencies due to parasitic elements R X+ and C X+ and at low frequencies due to req. Fortunately, req can be set to zero by choosing R2 as follows: If R X− is too high (R X− > ∞), the Equation (12) is reduced to R 2 = R 1 + R Y − R Z+ , which is easily satisfied in practice.

Simulation Results
The performance of the proposed circuit of Figure 2 is tested through SPICE simulations using 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V. The resulted performance parameters for the VCII±, derived from one in Figure 5 [58], are reported in Table 1 Figure 6. From the simulation results, the operation frequency range of the proposed SI is 1 kHz-10 MHz. The value of series impedance is also obtained as a negligible value of 237 mΩ. To test the time-domain performance of the proposed inductor simulator, a sinusoidal input current with peak amplitude of 25 µA and frequency of 1 MHz is used.     Figure 7 shows the produced output signals along with applied input signal. Additionally, the value of total harmonic distortion (THD) is 1.8%. The value of the phase shift between input current and output voltage is approximately 90°. There is an offset voltage at the simulation output voltage whose value is approximately −12 mV. Figure 8 shows the THD variations for various amplitudes of the peak-input currents at a frequency of 1 MHz. Favorably, the maximum value of THD remains below 3.7%. To test the frequency-      Figure 7 shows the produced output signals along with applied input signal. Additionally, the value of total harmonic distortion (THD) is 1.8%. The value of the phase shift between input current and output voltage is approximately 90°. There is an offset voltage at the simulation output voltage whose value is approximately −12 mV. Figure 8 shows the THD variations for various amplitudes of the peak-input currents at a frequency of 1 MHz. Favorably, the maximum value of THD remains below 3.7%. To test the frequencydomain applicability of the proposed SI, it is used in a standard fifth-order HP ladder filter shown in Figure 9 with Leq1 = Leq2 = 200 μH, RS = RL = 5 kΩ and C1 = C2 = C3 = 50 pF. Frequency-domain analysis for the filer is given in Figure 10. A time-domain analysis for the filter example is depicted in Figure 11, in which a sinusoidal input voltage with a 250 mV peak and a frequency of 2.5 MHz is applied. Figure 12 demonstrates the THD variations  Figure 7 shows the produced output signals along with applied input signal. Additionally, the value of total harmonic distortion (THD) is 1.8%. The value of the phase shift between input current and output voltage is approximately 90 • . There is an offset voltage at the simulation output voltage whose value is approximately −12 mV. Figure 8 shows the THD variations for various amplitudes of the peak-input currents at a frequency of 1 MHz. Favorably, the maximum value of THD remains below 3.7%. To test the frequency-domain applicability of the proposed SI, it is used in a standard fifth-order HP ladder filter shown in Figure 9 with L eq1 = L eq2 = 200 µH, R S = R L = 5 kΩ and C 1 = C 2 = C 3 = 50 pF. Frequencydomain analysis for the filer is given in Figure 10. A time-domain analysis for the filter example is depicted in Figure 11, in which a sinusoidal input voltage with a 250 mV peak and a frequency of 2.5 MHz is applied. Figure 12 demonstrates the THD variations for  Figure 13, are changed by 1%. Furthermore, threshold voltages of all the MOS transistors in Figure 5 are varied by 1% and the result for the filter example is given in Figure 14. Power supplies are varied and the result for the filter example is depicted in Figure 15.  Figure 5 are varied by 1% and the result for the filter example is given in Figure 14. Power supplies are varied and the result for the filter example is depicted in Figure 15.     Figure 5 are varied by 1% and the result for the filter example is given in Figure 14. Power supplies are varied and the result for the filter example is depicted in Figure 15.     Figure 5 are varied by 1% and the result for the filter example is given in Figure 14. Power supplies are varied and the result for the filter example is depicted in Figure 15.                      A comparison among the proposed grounded SI with other reported similar works, such as CFOA [4][5][6][7], CCII [8][9][10][11] and VCII-based ones [47,48], is drawn in Table 2, which considers important parameters such as technology, power dissipation, supply voltage, frequency range and the number of grounded and floating passive components, etc. The work reported in [4] suffers from a high supply voltage of ±5V. Although the frequency range of the circuit reported in [7] is limited to 1 kHz, it consumes larger power consumption compared to the proposed circuit because it employs two CFOA as active building blocks. In fact, compared to VCII, which consists of one CB and one VB, the internal structure of each CFOA is formed by one CB and two VBs. Therefore, even in equal conditions, the circuit reported in [7] consumes larger power if compared to the proposed one. The circuit reported in [10], which employs three CCII as active building blocks, is applicable at frequencies larger than 100 kHz while the proposed circuit low-frequency range is 1 kHz. This is attributed to the reduced parasitic series resistance as well as its simplicity, which employs only one active building block; therefore, the number of parasitic elements, which are the frequency-performance limiting factor, is reduced. Although, compared to the previously reported VCII-based SI circuit of [48], the power consumption of the proposed circuit is increased approximately 3 times, but the frequency range is extended from 2.5 MHz to 10 MHz. The work reported in [48] also shows a lossy inductor. In addition, the series resistance is decreased from 191 Ω to 0.23 Ω. Moreover, by setting the values of R 1 and R 2 , the value of a parasitic series resistor can be set as required in the specific application.

Experimental Verifications
Implementation of the VCII± by utilizing AD844s [59] is demonstrated in Figure 16 where supply voltages of AD844s are chosen as ±12 V. Additionally, passive elements R a = R b = 2.2 kΩ; R c = 1.1 kΩ for realizing VCII; R 1 = R 2 = 2.2 kΩ; and C = 2.2 nF for realizing L, are selected to obtain L eq ∼ = 10.65 mH. Figure 17 shows a picture of the fabricated board, highlighting its main features. The experimental setup used to evaluate the equivalent inductance is depicted in Figure 18 where R' = 1 kΩ is chosen. Thus, a time-domain analysis of the measured grounded SI is given in Figure 19, where a sinusoidal input voltage signal (V in ) with 0.5 V peak at 25 kHz is applied to the input and output voltage taken from V out . The measured phase shift between them is approximately 86 • . A second-order voltage-mode band-pass (BP) filter application is analyzed as well: in Figure 20 the schematic that is used for this experiment is reported. Transfer function of the BP filter in Figure 20 is evaluated as: Electronics 2021, 10, 1693 11 of 15 1.9 kΩ (given in order to improve low-frequency performance); R2 = 2.2 kΩ and C = 2.2 nF, yielding L ≅ 9.2 mH. Additionally, Cf = 30 nF is chosen to obtain f0 ≅ 9.58 kHz. In Figure 21, there is good agreement between ideal, simulated and measurement results above 1kHz. Any discrepancy between these results occurs at frequencies below 1 KHz which is not in the operation frequency range of the proposed circuit and is due to the combined non idealities from AD844s. A time-domain analysis for the BP filter is given in Figure 22 in which a sinusoidal input voltage with 1 V peak-to-peak at f = f0 is applied.

AD844
- Figure 16. Implementation of the VCII± by utilizing AD844s. Figure 16. Implementation of the VCII± by utilizing AD844s.           The measured transfer function is reported in Figure 21 and compared to the simulated and the ideal ones. For this analysis the following values are chosen: R ∼ = 1 kΩ, R 1 ∼ = 1.9 kΩ (given in order to improve low-frequency performance); R 2 = 2.2 kΩ and C = 2.2 nF, yielding L ∼ = 9.2 mH. Additionally, C f = 30 nF is chosen to obtain f 0 ∼ = 9.58 kHz. In Figure 21, there is good agreement between ideal, simulated and measurement results above 1kHz. Any discrepancy between these results occurs at frequencies below 1 KHz which is not in the operation frequency range of the proposed circuit and is due to the combined non idealities from AD844s. A time-domain analysis for the BP filter is given in Figure 22 in which a sinusoidal input voltage with 1 V peak-to-peak at f = f 0 is applied.

Conclusions
A new implementation for the SI based on a single VCII± is proposed. It is composed of one VCII± ABB, two resistors and one grounded capacitor that is attractive for IC fabrication. The prominent feature of the presented work is its low series impedance. As a result, it has the property of improved low-frequency performances. However, it is restricted with a single resistive matching condition. To test the functionality of the proposed circuit, it is used in the realization of a standard fifth-order HP ladder filter and a second-order BP filter. Simulation and experimental results approach to ideal ones but an unimportant difference arises from non-idealities of the VCII±.

Conclusions
A new implementation for the SI based on a single VCII± is proposed. It is composed of one VCII± ABB, two resistors and one grounded capacitor that is attractive for IC fabrication. The prominent feature of the presented work is its low series impedance. As a result, it has the property of improved low-frequency performances. However, it is restricted with a single resistive matching condition. To test the functionality of the proposed circuit, it is used in the realization of a standard fifth-order HP ladder filter and a second-order BP filter. Simulation and experimental results approach to ideal ones but an unimportant difference arises from non-idealities of the VCII±.