Temperature Dependent Analytical Model for the Threshold Voltage of the SiC VJFET with a Lateral Asymmetric Channel

: The wide-bandgap (WBG) semiconductor devices for modern power electronics require intensive efforts for the analysis of the critical aspects of their operation. In recent years, silicon carbide (SiC) based ﬁeld effect transistor have been extensively investigated. Motivated by the signiﬁcant employment of the SiC Vertical Junction Field Effect transistors with lateral channel (LC-VJFET) in the development of high-voltage and high temperature applications, the properties of the LC-VJFET device are investigated in this work. The most important normally-ON LC-VJFET parameter is their threshold voltage (V Th ), which is deﬁned as the gate-to-source voltage necessary to block the device. The higher complexity of the blocking operation of the normally-ON device makes the accurate knowledge of the V Th as a fundamental issue. In this paper, a temperature dependent analytical model for the threshold voltage of the normally-ON LC-VJFET is developed. This analytical model is derived based on a numerical analysis of the electrical potential distribution along the asymmetrical lateral channel in the blocking operation. To validate our model, the analytical results are compared to 2D numerical simulations and experimental results for a wide temperature range.


Introduction
The threshold voltage (V Th ) and its dependence on temperature is an important parameter of any FET structure for device evaluation and circuit design. Several works took place in the literature on its modeling for MOSFETs [1][2][3][4][5][6]. However, there is a lack of similar work for power JFETs structure. During the last decade, wide bandgap devices such as those made of silicon carbide (SiC), have emerged as promising power switching devices for a wide field of advanced electronic applications, especially at high temperature and high voltage. Some of them have been fabricated and tested in various research laboratories, and others are on the market [7][8][9][10][11][12][13][14][15]. Compared with the SiC MOSFET, SiC VJFET received a lot of attention because of its threshold voltage (V th ) stability for different temperature values, since no reliability issues appear with gate oxide on contrary to SiC MOSFETs [5][6][7]. Different structures of the SiC VJFET device have been developed and studied [16][17][18][19][20][21][22][23][24][25]. Among of them, in this paper, the SiC LC-VJFET of Figure 1 [16,20] is investigated under a physical model of the threshold voltage. The SiC LC-VJFET has a normally-on behavior. In other words, it conducts current even if no gate-source voltage is applied. To turn this JFET off, a negative gate-to-source voltage bias should be applied. The main parameter that controls the blockage of the device is the gate-to-source threshold voltage. The blocking condition of the device corresponds to a pinch-off operation where the saturation current reaches zero. Although this condition is very important for the analysis and the modeling of the device, few studies in this context have been published, generally leading to a complex or non-analytical expression of the threshold voltage [26,27]. the analysis and the modeling of the device, few studies in this context have been published, generally leading to a complex or non-analytical expression of the threshold voltage [26,27]. In a previous work [26], the modeling of the asymmetrical double gate channel of the SiC LC-VJFET structure was investigated. A numerical method has been used to define the blocking conditions of the JFET device. These conditions have been presented by complex functions that are not easy to implement in software to simulate the physical model of the JFET. Therefore, for such complicated SiC LC-VJFET structure, it is a great interest to elaborate an analytical expression of the threshold voltage and its dependence with the temperature. Figure 1 represents the schematic of the investigated device LC-VJFET.
In the present study, an analytical model of threshold voltage for the SiC LC-VJFET is derived. We demonstrate that this model is far from being a classic threshold voltage expression [28]. We will show that the analytical expression of the threshold voltage is simple and easy to use. The proposed model can be used as an efficient tool for design, fabrication and modeling for the SiC VJFET device. The validity of the developed analytical model is investigated by comparing the model results with the experimental and the numerical simulation results within a wide temperature range.

Analysis and Modeling of the Asymmetric Lateral Channel of the VJFET
This section concerns the analysis and the modeling of the behavior of the SiC LC-VJFET at blocking operation, which is controlled by the P + NP + lateral channel. Figure 2 shows the lateral channel structure of Figure 1. This lateral channel controls asymmetrically the current in the device that is maintained by the difference in potentials between the two P + layers, which are connected to the gate and source terminals, respectively. The asymmetry of the lateral channel does not concern the geometry, which is symmetric, but concerns the control of the channel. So, a model of the current distribution in the asymmetric lateral channel is needed. In a previous work [26], the modeling of the asymmetrical double gate channel of the SiC LC-VJFET structure was investigated. A numerical method has been used to define the blocking conditions of the JFET device. These conditions have been presented by complex functions that are not easy to implement in software to simulate the physical model of the JFET. Therefore, for such complicated SiC LC-VJFET structure, it is a great interest to elaborate an analytical expression of the threshold voltage and its dependence with the temperature. Figure 1 represents the schematic of the investigated device LC-VJFET.
In the present study, an analytical model of threshold voltage for the SiC LC-VJFET is derived. We demonstrate that this model is far from being a classic threshold voltage expression [28]. We will show that the analytical expression of the threshold voltage is simple and easy to use. The proposed model can be used as an efficient tool for design, fabrication and modeling for the SiC VJFET device. The validity of the developed analytical model is investigated by comparing the model results with the experimental and the numerical simulation results within a wide temperature range.

Analysis and Modeling of the Asymmetric Lateral Channel of the VJFET
This section concerns the analysis and the modeling of the behavior of the SiC LC-VJFET at blocking operation, which is controlled by the P + NP + lateral channel. Figure 2 shows the lateral channel structure of Figure 1. This lateral channel controls asymmetrically the current in the device that is maintained by the difference in potentials between the two P + layers, which are connected to the gate and source terminals, respectively. The asymmetry of the lateral channel does not concern the geometry, which is symmetric, but concerns the control of the channel. So, a model of the current distribution in the asymmetric lateral channel is needed. In [26] the gradual channel approximation is used to derive the current flow in the asymmetrical lateral channel of the JFET. This approximation yields reasonably good results if the channel has a small width and large length and if the carrier mobility can be  In [26] the gradual channel approximation is used to derive the current flow in the asymmetrical lateral channel of the JFET. This approximation yields reasonably good results if the channel has a small width and large length and if the carrier mobility can be assumed to be constant and independent of the electric field [28].
Under this approximation, the channel current of the LC-VJFET can be derived analytically and may be expressed as: where a is the half of the channel width, Z is the equivalent width of the channel in the perpendicular direction, N D is the doping density of channel, W 1 and W 2 are the depletion layer widths under Gate 1 and Gate 2, respectively as clearly shown in Figure 2.
The drain current in the linear region is obtained by the integration of Equation (1) along the channel: where V bi is the built-in voltage and is given by [29]: The intrinsic carrier concentration n i is expressed according to: where N v and N c are the density of states in the valence and conduction bands, respectively, T the absolute temperature, k the constant of Boltzmann and E G (T) is the energy gap. The pinch-off voltage V P and channel resistance R CH are defined as: They have the same expression than in the symmetric channel model. So, for: We can find the channel current in the symmetric case which is given by [28]: Since the channel voltage V CH is less than the saturation voltage V CHSAT the SiC JFET works in linear region. Beyond this value of saturation, the channel current will be saturated and the SiC JFET works in the saturation region. So, the saturation value is an important parameter, which represents the boundary between linear and saturation regions. This saturation region corresponds to the pinch-off operation which is reached when Equation (9) is valid: Electronics 2021, 10, 1494 4 of 12 From Equation (9) the saturation voltage can be determined by taking into account the expressions of depletion layer widths W 1 and W 2 in the case of a uniformly doped channel with doping level N D : Assuming that the pinch-off condition is reached for x = L. Using (10) and (11), Equation (9) allows to define the saturation voltage: At this point the saturated drain current I CHSAT can be obtained from Equation (2) by using the standardized voltage values of the saturation voltage, the "Gate 1" to source voltage and the "Gate 2" to source voltage: The saturated drain current can be calculated from this equation by substituting the drain voltage at pinch-off with Equation (12): with: In the symmetric case, δ 1 = δ 2 = δ and Equation (17) becomes: which is the classical saturation current for the symmetric JFET channel. In the blocking region: the channel current is zero, in particular for δ = 1. Therefore, in the symmetric case, the classical condition of the blocking operation is expressed in the form of: where V Th is the classical threshold voltage. It is defined as the gate-to-source voltage value at which the saturation current becomes zero, (I Sy CHSAT (V Th ) = 0). However, it is much more complicated to find a simple threshold voltage model for asymmetric JFET channel. So, a numerical method can be adopted for solving the Equation (17). Figure 3 shows the plot of the Γ(δ 1 , δ 2 ) function.
the channel current is zero, in particular for 1   . Therefore, in the symmetric case, the classical condition of the blocking operation is expressed in the form of: where VTh is the classical threshold voltage. It is defined as the gate-to-source voltage value at which the saturation current becomes zero, ( Sy Th CHSAT I (V ) 0  ). However, it is much more complicated to find a simple threshold voltage model for asymmetric JFET channel. So, a numerical method can be adopted for solving the Equation (17). Figure 3 shows the plot of the 1 2 ( , )    function.  , which is extracted from Figure 3 shows the curve 0  which correspond to the pinch-off operation where the saturation current becomes null and satisfies this condition: 1 2 ( , )    reaches to: Where: In addition: Therefore, from the graphical representation of Figure 5 a relation between 0 1  and 0 2  can be implicitly given by:   Figure 3 shows the curve Γ 0 which correspond to the pinch-off operation where the saturation current becomes null and satisfies this condition: Γ(δ 1 , δ 2 ) reaches to: where: and Equation (23) may be rewritten as: which gives an implicitly expression of the threshold voltage: This expression is based on a graphical representation which making it difficult to introduce in the circuit simulator, so an analytical threshold voltage model is needed.  In addition: Therefore, from the graphical representation of Figure 5 a relation between δ 0 1 and δ 0 2 can be implicitly given by: Electronics 2021, 10, 1494 6 of 12 which correspond to a blocking operation where the gate-to-source voltage reaches the threshold voltage value. At the blocking threshold V GS = V Th and Equation (23) may be rewritten as: which gives an implicitly expression of the threshold voltage:   This expression is based on a graphical representation which making it difficult to introduce in the circuit simulator, so an analytical threshold voltage model is needed.

Threshold Voltage Model and Validation
In this section we proceed to develop the threshold voltage model based on the analysis of the potential distribution, ϕ, inside the lateral channel. To simplify the analysis, the gradual channel approximation is used to obtain a simple electric potential expression by solving the 1-D Poisson's equation along the y-direction from the top gate "Gate 1" to the bottom gate "Gate 1".
The 1-D Poisson equation can be written as [30]: using the following boundary conditions: and assuming that at y = y m which is the maximum value of y when: In addition: in the case of a uniformly doped channel with doping level N D , an expression for the electrical potential is obtained: using (29) and (30) conditions we would acquire: In addition: substituting ϕ m in (34) we obtain the expression for the depletion width value as function of the applied voltage V GS : using (36), Equation (35) can be rewritten in the form of: By substituting Equations (36) and (37) in Equation (33), the expression for the electric potential is obtained as follows: which represents the variation of the electric potential as function of the applied voltage V GS . The electrical potential evolution in the lateral channel under the blocking condition is analyzed by using a 2D TCAD physical simulator [31]. This analysis is based on many simulations by changing the parameters of the lateral channel (half width of the lateral channel "a" and the doping level "N D "). By considering the gradual channel approximation, the length L of the lateral channel was taken bigger than its width. The other typical parameters were taken from [25]. Referring to Figure 1, Table 1 summarizes the values of the doping concentrations and geometrical parameters used in this numerical simulation. The numerical simulation results are presented in Figures 5 and 6, which show that the electrical potential reaches its maximum ϕ m at the point y m where the two space charge regions coincide. The first space charge region (SCR1) corresponds to the spreading of depletion layer under the top gate to achieve the width y m when the applied gate-source voltage becomes equal to the threshold gate voltage, which is given by: where ω 0 is the depletion-layer width of the second space charge region (SCR2) caused by the built-in potential (V bi ) when no voltage is applied to the bottom gate abrupt junction. Therefore, substituting (39) in (35), we obtain: which corresponds well to the built-in potential (V bi ) producing the depletion layer given by [30]: Electronics 2021, 10, x FOR PEER REVIEW 9 of 13 Furthermore, as illustrated in Figure 6 when Vgs reaches VTh, the electrical potential φm reaches Vbi and Equation (37) can be rewritten in the form of: which yields to the following expression:  Figure 7. We obtained a good agreement between analytical expression given in Equation (44) and the numerical solution of 0  function given in Figure 4. A vertical cut from "Gate 1" to "Gate 2" has been accomplished on Figure 5 and from this cut we obtained the electric potential distribution along the channel of the SiC LC-VJFET structure and is illustrated in Figure 6.
Furthermore, as illustrated in Figure 6 when Vgs reaches V Th , the electrical potential ϕ m reaches V bi and Equation (37) can be rewritten in the form of: which yields to the following expression: This result is validated and shown in Figure 7. We obtained a good agreement between analytical expression given in Equation (44) and the numerical solution of Γ 0 function given in Figure 4.  It is seen from the figure an excellent agreement between the model and experimental results is observed. This confirms the validity of the suggested threshold voltage model. It is also clear that there is a big difference between the standard model of threshold voltage (given by Equation (45)) and the analytical model results, thus cannot describe well enough the behavior of threshold voltage of the studied device. It is seen from the figure an excellent agreement between the model and experimental results is observed. This confirms the validity of the suggested threshold voltage model. It is also clear that there is a big difference between the standard model of threshold voltage (given by Equation (45)) and the analytical model results, thus cannot describe well enough the behavior of threshold voltage of the studied device. Figure 9 depicts the dependence of threshold voltage versus the Pinch-off voltage using the proposed model for two different built-in voltages. Since it is too difficult to determine the Vp value directly from the analytical model which is presented as an implicit expression, Figure 9 serves as a chart tool for parameter extraction. Knowing its threshold voltage experimentally, one can easily extract the pinchoff voltage value and then estimate geometric and doping parameters of the device.

Conclusions
This paper focuses essentially on the physical analysis of the behavior of the SiC LC-VJFET with lateral channel in the blocking mode. The difficulty posed by this device is that the blockage is controlled asymmetrically by the lateral channel. The asymmetry concerns the difference of the applied gate voltages between the two P + layers and not the geometry of the channel structure which is symmetric. The blocking condition of the power device has not been previously solved correctly. To address this problem, this work was investigated to accurately propose an analytical model of the gate to source threshold voltage which is a main parameter that controls the blockage of the device.
So, a temperature dependent analytical model for the threshold voltage of the power device SiC LC-VJFET has been derived under two steps: Firstly, numerical method has been adopted to solve the saturation current which allows to a graphical solution of the blocking condition. Secondly, a physical analysis of the electric potential distribution in the asymmetric side-channel blocking condition leads to an analytical solution which was validated regarding the graphical solution and numerical simulation. The model is compared with experimental data for a wide temperature range. Good agreement has been observed demonstrating the accuracy of the proposed model.  Since it is too difficult to determine the V p value directly from the analytical model which is presented as an implicit expression, Figure 9 serves as a chart tool for parameter extraction. Knowing its threshold voltage experimentally, one can easily extract the pinchoff voltage value and then estimate geometric and doping parameters of the device.

Conclusions
This paper focuses essentially on the physical analysis of the behavior of the SiC LC-VJFET with lateral channel in the blocking mode. The difficulty posed by this device is that the blockage is controlled asymmetrically by the lateral channel. The asymmetry concerns the difference of the applied gate voltages between the two P + layers and not the geometry of the channel structure which is symmetric. The blocking condition of the power device has not been previously solved correctly. To address this problem, this work was investigated to accurately propose an analytical model of the gate to source threshold voltage which is a main parameter that controls the blockage of the device.
So, a temperature dependent analytical model for the threshold voltage of the power device SiC LC-VJFET has been derived under two steps: Firstly, numerical method has been adopted to solve the saturation current which allows to a graphical solution of the blocking condition. Secondly, a physical analysis of the electric potential distribution in the asymmetric side-channel blocking condition leads to an analytical solution which was validated regarding the graphical solution and numerical simulation. The model is compared with experimental data for a wide temperature range. Good agreement has been observed demonstrating the accuracy of the proposed model. Author Contributions: Modelling and simulation, S.G. and A.F.; writing-original draft preparation, S.G.; writing-review and analysis, S.G. and A.F.; review and editing, S.G. and K.B. All authors have read and agreed to the published version of the manuscript.