Topological Review of Quasi-Switched Boost Inverters

: This paper presents a comprehensive review based on the features and drawbacks of the quasi-switched boost inverter (qSBI) topologies. The qSBI derived conﬁgurations are well suitable for low power applications due to their reduced number of components. This work focuses on the topological review of qSBI derived topologies and serves as a reference for further derivation and research on the selection of suitable topology for the speciﬁc renewable energy applications, particularly based on the photovoltaic (PV) converters. with double frequency carrier signal. The interleaved topologies perform better using qSM technique compared to the modiﬁed MBC modulation technique. The IqSBI has the advantage of reduced passive components and better performance compared to IqZSI for lower power applications. of and components imbalance distributed and zero vectors. In this technique, the reference vectors are generated using medium and zero vectors.


Introduction
Renewable energy source-based power generation plays an important role in satisfying global energy demand. The renewable energy sources (RES), like wind and photovoltaics, have changed the current scenario of the global energy structure. The selection of suitable inverter topology is an important factor to be considered in the renewable energy system design to improve the efficiency of the system and to maximize the energy extraction. Two basic topologies for DC-AC power conversion are voltage source inverter (VSI) and current source inverter (CSI). The VSI has the limitations of the output voltage which cannot exceed source voltage and the output voltage of CSI cannot be lower than the input voltage. Additionally, the power switches of the same leg cannot be turned on simultaneously in VSI and cannot be turned off at the same time in CSI. The impedance source (Z-source) converter introduced in 2002 outperforms the traditional VSI with buck-boost abilities in a single-stage power conversion and overcomes the shoot-through problems [1].
Z-source converters have emerged as one of the most promising and competitive converter topologies suitable for applications based on RES or alternative energy sources due to their capability of the extended input voltage regulation range. Z-source inverters (ZSI) was first proposed for the DC-AC conversion applications and then widened to DC-DC, AC-DC, AC-AC conversion applications [2][3][4][5][6][7][8][9]. ZSI consists of an LC pair in X-configuration network and transfers the temporary energy within the network during the shoot-through and non-shoot-through stages. The outstanding features of ZSI has attracted a lot of research and resulted in the development of several derived topologies like quasi-Z-source inverter (qZSI), magnetically coupled impedance network, embedded Z-source, Trans-Z-source, Γ-Z-source derived network, LCCT Z-source and qZSI, Y-source impedance network derived topologies, L-Z-source converter, Sigma Z-source converter, ∆-source impedance network derived topologies, A-source impedance network derived topologies, coupled-inductor, switched-inductor derived Z-source and quasi-Z-source topologies, and extended boost topologies. The extended boost ZSI and qZSI topologies are capable of producing infinite boost.
The qZSI topology derived from the ZSI inherits all the merits such as single-stage power conversion along with the benefits of reduced capacitor voltage stress with improved input current profile and reliability [10]. These unique merits of the qZSI topology have attracted a wide range of research for different applications [11][12][13][14][15] and resulted in several derived topologies of qZSI over the years.
The literature [16][17][18][19][20] presents a good overview of the various impedance source converter topologies. However, the practical implementation of extended boost topologies is not popular due to their use of large number of components and additional power losses [21][22][23][24]. Only few attempts of industrial design can be found [25,26].
In [27], two switched boost inverter (SBI) topologies are presented as simpler alternative solution to the ZSI with only half of the passive components. Figure 1a,b shows the SBI topologies derived from the inverse Watkins-Johnson topology and are well suited for low power applications. The SBI topology comprises a switched impedance network with a capacitor, inductor and a pair of diodes with an active switch. In SBI Type 1, the capacitor is connected to the negative DC bus, and in SBI Type 2 the capacitor is connected to the positive side of the DC bus. The operation of the SBI topology is similar to the ZSI in the shoot-through state and can replace the ZSI in low power application due to the presence of one less LC pair. The drawbacks of the SBI are high voltage stress on the capacitor, lower boot factor than impedance source converter, and discontinuous input current. In [28], two Trans-SBI topologies are presented with a two-winding transformer in place of the inductor in the traditional SBI. In Trans-SBI Type 1, the capacitor is connected to the negative side of the H-bridge inverter. In Trans-SBI Type 2, the capacitor is connected to the positive side of the H-bridge inverter. Figure 1c,d presents the Trans-switched boost inverter topologies Type 1 and Type 2.
Electronics 2021, 10, x FOR PEER REVIEW 2 of 29 source impedance network derived topologies, L-Z-source converter, Sigma Z-source converter, Δ-source impedance network derived topologies, A-source impedance network derived topologies, coupled-inductor, switched-inductor derived Z-source and quasi-Z-source topologies, and extended boost topologies. The extended boost ZSI and qZSI topologies are capable of producing infinite boost. The qZSI topology derived from the ZSI inherits all the merits such as single-stage power conversion along with the benefits of reduced capacitor voltage stress with improved input current profile and reliability [10]. These unique merits of the qZSI topology have attracted a wide range of research for different applications [11][12][13][14][15] and resulted in several derived topologies of qZSI over the years.
The literature [16][17][18][19][20] presents a good overview of the various impedance source converter topologies. However, the practical implementation of extended boost topologies is not popular due to their use of large number of components and additional power losses [21][22][23][24]. Only few attempts of industrial design can be found [25,26].
In [27], two switched boost inverter (SBI) topologies are presented as simpler alternative solution to the ZSI with only half of the passive components. Figure 1a,b shows the SBI topologies derived from the inverse Watkins-Johnson topology and are well suited for low power applications. The SBI topology comprises a switched impedance network with a capacitor, inductor and a pair of diodes with an active switch. In SBI Type 1, the capacitor is connected to the negative DC bus, and in SBI Type 2 the capacitor is connected to the positive side of the DC bus. The operation of the SBI topology is similar to the ZSI in the shoot-through state and can replace the ZSI in low power application due to the presence of one less LC pair. The drawbacks of the SBI are high voltage stress on the capacitor, lower boot factor than impedance source converter, and discontinuous input current. In [28], two Trans-SBI topologies are presented with a two-winding transformer in place of the inductor in the traditional SBI. In Trans-SBI Type 1, the capacitor is connected to the negative side of the H-bridge inverter. In Trans-SBI Type 2, the capacitor is connected to the positive side of the H-bridge inverter. Figure 1c,d presents the Transswitched boost inverter topologies Type 1 and Type 2. In [29], switched inductor derived SBIs (SL-SBI) are presented with high step-up DClink voltage. They are derived from the SBI by adding one inductor and three diodes. The SL-SBI and Trans-SBI have better efficiency and fewer components compared to the SL-ZSI and Trans-ZSI topologies. Several topologies can be derived from the basic SLBI by changing the place of the input DC source. By placing the input source in the place of DC source 1, two SLBI topologies can be derived as SLBI Type 1 and Type 2. In SLBI Type 1, the capacitor is connected to the negative side of the H-bridge inverter. In SLBI Type 2, the capacitor is connected to the positive side of the H-bridge inverter. Several topologies can be derived from the basic SLBI by changing the place of the input DC source. The continuous input current SLBI is derived by placing the input source in the place of the DC Source 4. The discontinuous input current SLBI can be derived by placing the input DC voltage source in the place of the DC Source 2. In discontinuous input current SLBI, the DC source is in series connection with the diode, resulting in discontinuous input current. A ripple input current SLBI can be obtained by placing the input source in the place of DC Source 3. In this configuration, the source current flows to the SL cell, resulting in input current ripples. Figure 2a

Overview of Original Quasi-Switched Boost Topologies (qSBI)
In [30], a class of quasi-switched boost inverter (qSBI) topologies is presented as an alternative solution to the quasi-Z-source inverter. An overview comparison of qZSI and qSBI is presented in [31]. The qSBI topology originally derived from the SBI topology utilizes the same number of components and offers reduced voltage stress on the capacitor, increased boost factor with improved input current profile. Figure 3a,b shows the embedded qSBI Type 1 and Type 2 configurations. In E-qSBI type 1, the input ground is not shared with the inverter bridge ground. In E-qSBI type 2, the input ground and inverter bridge share the same ground.

Overview of Original Quasi-Switched Boost Topologies (qSBI)
In [30], a class of quasi-switched boost inverter (qSBI) topologies is presented as an alternative solution to the quasi-Z-source inverter. An overview comparison of qZSI and qSBI is presented in [31]. The qSBI topology originally derived from the SBI topology utilizes the same number of components and offers reduced voltage stress on the capacitor, increased boost factor with improved input current profile. Figure 3a,b shows the embedded qSBI Type 1 and Type 2 configurations. In E-qSBI type 1, the input ground is not shared with the inverter bridge ground. In E-qSBI type 2, the input ground and inverter bridge share the same ground.

Overview of Original Quasi-Switched Boost Topologies (qSBI)
In [30], a class of quasi-switched boost inverter (qSBI) topologies is presented as an alternative solution to the quasi-Z-source inverter. An overview comparison of qZSI and qSBI is presented in [31]. The qSBI topology originally derived from the SBI topology utilizes the same number of components and offers reduced voltage stress on the capacitor, increased boost factor with improved input current profile. Figure 3a,b shows the embedded qSBI Type 1 and Type 2 configurations. In E-qSBI type 1, the input ground is not shared with the inverter bridge ground. In E-qSBI type 2, the input ground and inverter bridge share the same ground.  Several modulation techniques were proposed in [32][33][34][35][36][37] for qSBI to improve the voltage gain. In [30], the simple boost control (SBC) method was presented for the qSBI topologies. Figure 4 presents the PWM SBC strategy for the qSBI. In the SBC method, the control signals are generated by comparing a constant voltage to the triangular waveform. The control signal for Switch S is generated by comparing a constant voltage signal with another double frequency triangular waveform of half the amplitude and then inserted into the control signal of switches S1-S4 as shoot-through (ST) signal. In the SBC method, the maximum duty ratio of ST state is limited by (1-M) and reduced modulation index resulting in lower DC-AC conversion gain and higher THD. To overcome this drawback, an improved PWM control method with a higher modulation index was presented in [32]. The control signals for the switches S1-S4 are generated by comparing two reference voltages with a high frequency triangular waveform T1. The control signal for the Switch S is generated by comparing a constant voltage signal with a high frequency sawtooth waveform. The ST signal is generated by comparing the constant voltage signal with another triangular waveform T2 and then inserted into the H-bridge switch control signals using logic gates OR. The improved PWM technique offers high boost conversion, reduced voltage stress on the passive components, improved efficiency and reduced ST current. This PWM technique has the drawback of the high peak value of LF capacitor voltage and inductor current. In [33], the maximum boost PWM control method is presented for single-phase qSBI topology with improved modulation index. In MBC method, the control signals for H-bridge switches are generated by comparing two sinusoidal waveforms with amplitude value M to a triangular waveform. The control signal of Switch S is generated by comparing a double line frequency sinusoidal waveform to a triangular waveform of double frequency with half of the amplitude. This control signal is inserted into the H-bridge switch control signal as ST states. In this method, a variable ST time intervals are generated by inserting low frequency voltage into the constant voltage signal. Several modulation techniques were proposed in [32][33][34][35][36][37] for qSBI to improve the voltage gain. In [30], the simple boost control (SBC) method was presented for the qSBI topologies. Figure 4 presents the PWM SBC strategy for the qSBI. In the SBC method, the control signals are generated by comparing a constant voltage to the triangular waveform. The control signal for Switch S is generated by comparing a constant voltage signal with another double frequency triangular waveform of half the amplitude and then inserted into the control signal of switches S1-S4 as shoot-through (ST) signal. In the SBC method, the maximum duty ratio of ST state is limited by (1-M) and reduced modulation index resulting in lower DC-AC conversion gain and higher THD. To overcome this drawback, an improved PWM control method with a higher modulation index was presented in [32]. The control signals for the switches S1-S4 are generated by comparing two reference voltages with a high frequency triangular waveform T1. The control signal for the Switch S is generated by comparing a constant voltage signal with a high frequency sawtooth waveform. The ST signal is generated by comparing the constant voltage signal with another triangular waveform T2 and then inserted into the H-bridge switch control signals using logic gates OR. The improved PWM technique offers high boost conversion, reduced voltage stress on the passive components, improved efficiency and reduced ST current. This PWM technique has the drawback of the high peak value of LF capacitor voltage and inductor current. In [33], the maximum boost PWM control method is presented for single-phase qSBI topology with improved modulation index. In MBC method, the control signals for Hbridge switches are generated by comparing two sinusoidal waveforms with amplitude value M to a triangular waveform. The control signal of Switch S is generated by comparing a double line frequency sinusoidal waveform to a triangular waveform of double frequency with half of the amplitude. This control signal is inserted into the H-bridge switch control signal as ST states. In this method, a variable ST time intervals are generated by inserting low frequency voltage into the constant voltage signal. A family of PWM strategies was presented for the qSBI topologies in [34] with high reliability and reduced voltage stress on the semiconductor devices. The presented PWM techniques have reduced HF inductor current ripples. In PWM2 method, the ST signals for the H-bridge switches are generated by comparing two fixed signals with a triangular waveform of twice the frequency. The control signal for Switch S is generated by comparing a constant voltage signal with another triangular waveform. In PWM3 method, the control signal for switch S is generated by comparing two constant voltages with triangular waveform of three times frequency and 2/3 peak-to-peak value. The ST signal is inserted into the control signal of Switch S using the logic gate XOR. This PWM technique can be extended to n times by varying the triangular waveform frequency and peak-to- A family of PWM strategies was presented for the qSBI topologies in [34] with high reliability and reduced voltage stress on the semiconductor devices. The presented PWM techniques have reduced HF inductor current ripples. In PWM2 method, the ST signals for the H-bridge switches are generated by comparing two fixed signals with a triangular waveform of twice the frequency. The control signal for Switch S is generated by comparing a constant voltage signal with another triangular waveform. In PWM3 method, the control signal for switch S is generated by comparing two constant voltages with triangular waveform of three times frequency and 2/3 peak-to-peak value. The ST signal is inserted into the control signal of Switch S using the logic gate XOR. This PWM technique can be extended to n times by varying the triangular waveform frequency and peak-to-peak values. In the presented PWM technique, the high frequency inductor current ripple is reduced to n times. The major drawbacks of the presented techniques are complex PWM generation and higher switching losses. In [35], space vector modulation (SVM) strategy was presented for three-phase qSBI topology with high modulation index, reduced voltage stress on the components and inductor current ripple. Figure 5 presents the four DC-Link qSBI topologies in positive and negative buses. The four DC-Link qSBI topologies have the same number of components and identical characteristics. In DC-Link qSBI negative bus type 1 and 2, the input source is inserted between the SB cell with the negative terminal of the DC bus where the input ground is shared with the bridge inverter ground. In DC-Link qSBI positive bus type 1 and 2, the input source is inserted between the SB cell with the positive terminal of the DC bus where the input ground is not shared with the bridge inverter ground. The DC-Link qSBI topology introduced alongside the E-qSBI is less favored mainly because of their low voltage gain. In [36], a modified PWM control strategy based on the maximum constant boost control (MCBC) with third harmonic injection is presented for the DC-Link qSBI. The presented control strategy improves the power conversion efficiency with enhanced voltage gain and reduced the conduction losses. A three-phase DC-Link qSBI topology is presented in [37] with improved PWM strategy by maintaining the duty cycle of the active switch as constant and the ST duty cycle as control variable. In improved PWM strategy, the switch S is triggered outside the ST time interval by comparing a reference signal with the triangular waveform. The ST states are generated by comparing another reference signal with carrier frequency triangular waveform. The DC-Link qSBI with improved PWM control strategy is suitable for applications where a minimal boost is required. Compared to the qZSI topology, the E-qSBI and DC-qSBI have better efficiency with less passive components.
Electronics 2021, 10, x FOR PEER REVIEW 5 of 29 peak values. In the presented PWM technique, the high frequency inductor current ripple is reduced to n times. The major drawbacks of the presented techniques are complex PWM generation and higher switching losses. In [35], space vector modulation (SVM) strategy was presented for three-phase qSBI topology with high modulation index, reduced voltage stress on the components and inductor current ripple. Figure 5 presents the four DC-Link qSBI topologies in positive and negative buses. The four DC-Link qSBI topologies have the same number of components and identical characteristics. In DC-Link qSBI negative bus type 1 and 2, the input source is inserted between the SB cell with the negative terminal of the DC bus where the input ground is shared with the bridge inverter ground. In DC-Link qSBI positive bus type 1 and 2, the input source is inserted between the SB cell with the positive terminal of the DC bus where the input ground is not shared with the bridge inverter ground. The DC-Link qSBI topology introduced alongside the E-qSBI is less favored mainly because of their low voltage gain. In [36], a modified PWM control strategy based on the maximum constant boost control (MCBC) with third harmonic injection is presented for the DC-Link qSBI. The presented control strategy improves the power conversion efficiency with enhanced voltage gain and reduced the conduction losses. A three-phase DC-Link qSBI topology is presented in [37] with improved PWM strategy by maintaining the duty cycle of the active switch as constant and the ST duty cycle as control variable. In improved PWM strategy, the switch S is triggered outside the ST time interval by comparing a reference signal with the triangular waveform. The ST states are generated by comparing another reference signal with carrier frequency triangular waveform. The DC-Link qSBI with improved PWM control strategy is suitable for applications where a minimal boost is required. Compared to the qZSI topology, the E-qSBI and DC-qSBI have better efficiency with less passive components.

QSB Derived Topologies
For maximum energy extraction, RES requires high-voltage gain inverters. To improve the moderate voltage gain of the qSBI topology several derived topologies like switched-inductor qSBI, cascaded switched-inductor qSBI, half-bridge qSBI, four-switch qSBI, capacitor-switched qSBI, high-gain qSBI, and derived configurations like voltage multiplier cell qSBI (VMC-qSBI), cascaded qSBI configurations, interleaved qSBI, qSB T-Type inverter topologies were developed over the years. Figure 6 presents the various derived topologies and configurations of qSBI.

QSB Derived Topologies
For maximum energy extraction, RES requires high-voltage gain inverters. To improve the moderate voltage gain of the qSBI topology several derived topologies like switched-inductor qSBI, cascaded switched-inductor qSBI, half-bridge qSBI, four-switch qSBI, capacitor-switched qSBI, high-gain qSBI, and derived configurations like voltage multiplier cell qSBI (VMC-qSBI), cascaded qSBI configurations, interleaved qSBI, qSB T-Type Electronics 2021, 10, 1485 6 of 29 inverter topologies were developed over the years. Figure 6 presents the various derived topologies and configurations of qSBI. A switched-inductor derived qSBI topology (SL-qSBI) is presented in [38], with a switched-inductor cell added to the qSBI topology to increase the DC voltage gain. The SL cell is one of the most extensively used techniques to improve the voltage gain. Compared to the SL-ZSI topologies, the SL-qSBI has reduced losses due to reduction in the passive components size and offers high boost inversion ability. The SL-qSBI has the drawback of higher input current ripple compared to the traditional qSBI. In [39], an improved switched inductor qSBI topology (cSL-qSBI) is proposed with a modified switched inductor structure. The SL-qSBI and cSL-qSBI topologies are shown in Figure 7a,b. The cSL-qSBI has the benefit of reduced input current ripples compared to the SL-qSBI topology. The cSL-qSBI is derived from the SL-qSBI by connecting one inductor of the switchedinductor cell in series with the input source and has the same number of components as SL-qSBI. The presented topology features a simpler structure with high voltage DC gain and enhanced power density. The cSL-qSBI operated in DCM when the diode D5 current drops to zero in the second active state. In order to avoid this DCM for operation with low A switched-inductor derived qSBI topology (SL-qSBI) is presented in [38], with a switched-inductor cell added to the qSBI topology to increase the DC voltage gain. The SL cell is one of the most extensively used techniques to improve the voltage gain. Compared to the SL-ZSI topologies, the SL-qSBI has reduced losses due to reduction in the passive components size and offers high boost inversion ability. The SL-qSBI has the drawback of higher input current ripple compared to the traditional qSBI. In [39], an improved switched inductor qSBI topology (cSL-qSBI) is proposed with a modified switched inductor structure. The SL-qSBI and cSL-qSBI topologies are shown in Figure 7a,b. The cSL-qSBI has the benefit of reduced input current ripples compared to the SL-qSBI topology. The cSL-qSBI is derived from the SL-qSBI by connecting one inductor of the switched-inductor cell in series with the input source and has the same number of components as SL-qSBI. The presented topology features a simpler structure with high voltage DC gain and enhanced power density. The cSL-qSBI operated in DCM when the diode D5 current drops to zero in the second active state. In order to avoid this DCM for operation with low inductance or low power factor, a modified cSL-qSBI is presented with an additional switch Sb connected in parallel to the diode D5. This additional switch configuration is used to avoid the undesirable voltage stress in the components and also avoids the DCM operation when the switch Sb is turned on during the second active state. Figure 7c presents the modified cSL-qSBI topology.
Electronics 2021, 10, x FOR PEER REVIEW 7 of 29 inductance or low power factor, a modified cSL-qSBI is presented with an additional switch Sb connected in parallel to the diode D5. This additional switch configuration is used to avoid the undesirable voltage stress in the components and also avoids the DCM operation when the switch Sb is turned on during the second active state. Figure 7c presents the modified cSL-qSBI topology. A half-bridge qSBI [40] is presented in Figure 8 with two switched cells. Each switched cell consists of a capacitor, inductor, switch, and two diodes. This configuration is free from the start-up inrush current due to the absence of the X-shaped capacitor configuration and offers stable operation in undesirable ST states. The half-bridge qSBI utilize simple switching pattern based on PWM technique. The benefits of the half-bridge qSBI configuration are high voltage gain, low capacitor voltage stress, ST immunity, and generates zero voltage at the output. Compared to the conventional full-bridge and halfbridge ZSI, the half-bridge qSBI has lower weight, volume, and cost. The four-switch qSBI topology (FS-qSBI) [41] is obtained by the re-arrangement of second leg in the place of Switch S. The presented topology has one additional capacitor A half-bridge qSBI [40] is presented in Figure 8 with two switched cells. Each switched cell consists of a capacitor, inductor, switch, and two diodes. This configuration is free from the start-up inrush current due to the absence of the X-shaped capacitor configuration and offers stable operation in undesirable ST states. The half-bridge qSBI utilize simple switching pattern based on PWM technique. The benefits of the half-bridge qSBI configuration are high voltage gain, low capacitor voltage stress, ST immunity, and generates zero voltage at the output. Compared to the conventional full-bridge and half-bridge ZSI, the half-bridge qSBI has lower weight, volume, and cost. inductance or low power factor, a modified cSL-qSBI is presented with an additional switch Sb connected in parallel to the diode D5. This additional switch configuration is used to avoid the undesirable voltage stress in the components and also avoids the DCM operation when the switch Sb is turned on during the second active state. Figure 7c presents the modified cSL-qSBI topology. A half-bridge qSBI [40] is presented in Figure 8 with two switched cells. Each switched cell consists of a capacitor, inductor, switch, and two diodes. This configuration is free from the start-up inrush current due to the absence of the X-shaped capacitor configuration and offers stable operation in undesirable ST states. The half-bridge qSBI utilize simple switching pattern based on PWM technique. The benefits of the half-bridge qSBI configuration are high voltage gain, low capacitor voltage stress, ST immunity, and generates zero voltage at the output. Compared to the conventional full-bridge and halfbridge ZSI, the half-bridge qSBI has lower weight, volume, and cost. The four-switch qSBI topology (FS-qSBI) [41] is obtained by the re-arrangement of second leg in the place of Switch S. The presented topology has one additional capacitor The four-switch qSBI topology (FS-qSBI) [41] is obtained by the re-arrangement of second leg in the place of Switch S. The presented topology has one additional capacitor Cd and one less switch compared to the qSBI. The capacitor filter Cd is added to the output leg to removes DC offset component. The four-switch qSBI utilize modified PWM control strategy obtained by comparing one control signal with two high frequency triangular waveforms with a phase shift of 90 • . The ST signals are generated by comparing two constant voltages and then inserted into the control signals of the switches. A qSBI topology with four switches is shown in Figure 9a,b.
Electronics 2021, 10, x FOR PEER REVIEW 8 o Cd and one less switch compared to the qSBI. The capacitor filter Cd is added to the o put leg to removes DC offset component. The four-switch qSBI utilize modified PW control strategy obtained by comparing one control signal with two high frequency tri gular waveforms with a phase shift of 90°. The ST signals are generated by comparing t constant voltages and then inserted into the control signals of the switches. A qSBI top ogy with four switches is shown in Figure 9a,b. The FS-qSBI has the benefits of reduced switches than traditional qSBI. One of major drawbacks of the FS-qSBI topology is the low-frequency ripple issue. This impa the system stability and increases voltage stress. It can be suppressed by the utilization large passive elements. The additional passive components result in increased si weight, and cost of the system. To avoid this, a damping scheme is presented for the fo switch qSBI in [42] to overcome the low frequency ripple issue. In this control scheme, low-frequency ripple portion is extracted and added to the ST duty ratio D. This damp scheme improves the stability of the system and has reduced voltage stress on the co ponents. In [43], active power decoupling (APD) integrated FS-qSBI is presented to m gate low frequency ripple problem. Figure 10 presents the four-switch qSBI topology w APD. A dependent buck-type APD network is added to the FS-qSBI with auxiliary ind tor Ls and capacitor Cs. The operation of the APD topology is coupled to the switches of A and depends on the operation of the inverter. The ripple energy is deviated from the D link capacitor C and redirected to the capacitor Cs by the auxiliary inductor Ls. The auxili inductor also filters the output current and decouples the ripple current and load curre Compared to the FS-qSBI, the APD FS-qSBI has reduced ripples and improved load volta Additionally, the size of the passive components is reduced.  The FS-qSBI has the benefits of reduced switches than traditional qSBI. One of the major drawbacks of the FS-qSBI topology is the low-frequency ripple issue. This impacts the system stability and increases voltage stress. It can be suppressed by the utilization of large passive elements. The additional passive components result in increased size, weight, and cost of the system. To avoid this, a damping scheme is presented for the four switch qSBI in [42] to overcome the low frequency ripple issue. In this control scheme, the low-frequency ripple portion is extracted and added to the ST duty ratio D. This damping scheme improves the stability of the system and has reduced voltage stress on the components. In [43], active power decoupling (APD) integrated FS-qSBI is presented to mitigate low frequency ripple problem. Figure 10 presents the four-switch qSBI topology with APD. A dependent buck-type APD network is added to the FS-qSBI with auxiliary inductor Ls and capacitor Cs. The operation of the APD topology is coupled to the switches of leg A and depends on the operation of the inverter. The ripple energy is deviated from the DC-link capacitor C and redirected to the capacitor Cs by the auxiliary inductor Ls. The auxiliary inductor also filters the output current and decouples the ripple current and load current. Compared to the FS-qSBI, the APD FS-qSBI has reduced ripples and improved load voltage. Additionally, the size of the passive components is reduced. Cd and one less switch compared to the qSBI. The capacitor filter Cd is added to the output leg to removes DC offset component. The four-switch qSBI utilize modified PWM control strategy obtained by comparing one control signal with two high frequency triangular waveforms with a phase shift of 90°. The ST signals are generated by comparing two constant voltages and then inserted into the control signals of the switches. A qSBI topology with four switches is shown in Figure 9a,b. The FS-qSBI has the benefits of reduced switches than traditional qSBI. One of the major drawbacks of the FS-qSBI topology is the low-frequency ripple issue. This impacts the system stability and increases voltage stress. It can be suppressed by the utilization of large passive elements. The additional passive components result in increased size, weight, and cost of the system. To avoid this, a damping scheme is presented for the four switch qSBI in [42] to overcome the low frequency ripple issue. In this control scheme, the low-frequency ripple portion is extracted and added to the ST duty ratio D. This damping scheme improves the stability of the system and has reduced voltage stress on the components. In [43], active power decoupling (APD) integrated FS-qSBI is presented to mitigate low frequency ripple problem. Figure 10 presents the four-switch qSBI topology with APD. A dependent buck-type APD network is added to the FS-qSBI with auxiliary inductor Ls and capacitor Cs. The operation of the APD topology is coupled to the switches of leg A and depends on the operation of the inverter. The ripple energy is deviated from the DClink capacitor C and redirected to the capacitor Cs by the auxiliary inductor Ls. The auxiliary inductor also filters the output current and decouples the ripple current and load current. Compared to the FS-qSBI, the APD FS-qSBI has reduced ripples and improved load voltage. Additionally, the size of the passive components is reduced.  In [44], two qSBI topologies with an active impedance-source network are presented as high gain qSBI with a novel PWM technique to achieve high voltage gain. Figure 11b presents the switched capacitor qSBI topologies derived from the embedded qSBI by adding a capacitor and diode. This configuration offers high voltage gain and reduced voltage stress on the devices. The inverter structure can be further extendable to N-Cell to increase the voltage gain. The N-Cell can be obtained by connecting a capacitor and diode in cascade to the qSBI structure. This configuration reduced the ST voltage and current stress on the components. Therefore, it enables the utilization of low voltage rating components and results in improved efficiency, reduced size, and power losses. In [44], two qSBI topologies with an active impedance-source network are presented as high gain qSBI with a novel PWM technique to achieve high voltage gain. Figure 11b presents the switched capacitor qSBI topologies derived from the embedded qSBI by adding a capacitor and diode. This configuration offers high voltage gain and reduced voltage stress on the devices. The inverter structure can be further extendable to N-Cell to increase the voltage gain. The N-Cell can be obtained by connecting a capacitor and diode in cascade to the qSBI structure. This configuration reduced the ST voltage and current stress on the components. Therefore, it enables the utilization of low voltage rating components and results in improved efficiency, reduced size, and power losses. The coupled-inductor based impedance source topologies are attracting lot of research interests and variety of applications [15] due to their benefits of high gain with reduced passive components and low cost. Two coupled-inductor derived qSBI topologies with control strategy based on space vector pulse width modulation (SVPWM) technique are presented in [45]. The benefits of CI-qSBI topologies are high boost ability and low voltage stress on the components. High voltage gain can be achieved by varying the duty cycle and turns ratio of the coupled inductor. The voltage gain of the presented topologies can be further improved by adding a boost unit. The coupled-inductor qSBI topologies are derived by adding a coupled-inductor, capacitor, and diode to the qSB network. Figure 12a,b presents two coupled-inductor qSBI topologies. In the coupled-inductor qSBI Type 1, the input ground node is directly connected to the negative node of the inverter bridge and in Type 2, the ground is not directly connected to the negative node.  The coupled-inductor based impedance source topologies are attracting lot of research interests and variety of applications [15] due to their benefits of high gain with reduced passive components and low cost. Two coupled-inductor derived qSBI topologies with control strategy based on space vector pulse width modulation (SVPWM) technique are presented in [45]. The benefits of CI-qSBI topologies are high boost ability and low voltage stress on the components. High voltage gain can be achieved by varying the duty cycle and turns ratio of the coupled inductor. The voltage gain of the presented topologies can be further improved by adding a boost unit. The coupled-inductor qSBI topologies are derived by adding a coupled-inductor, capacitor, and diode to the qSB network. Figure 12a,b presents two coupled-inductor qSBI topologies. In the coupled-inductor qSBI Type 1, the input ground node is directly connected to the negative node of the inverter bridge and in Type 2, the ground is not directly connected to the negative node. In [44], two qSBI topologies with an active impedance-source network are presented as high gain qSBI with a novel PWM technique to achieve high voltage gain. Figure 11b presents the switched capacitor qSBI topologies derived from the embedded qSBI by adding a capacitor and diode. This configuration offers high voltage gain and reduced voltage stress on the devices. The inverter structure can be further extendable to N-Cell to increase the voltage gain. The N-Cell can be obtained by connecting a capacitor and diode in cascade to the qSBI structure. This configuration reduced the ST voltage and current stress on the components. Therefore, it enables the utilization of low voltage rating components and results in improved efficiency, reduced size, and power losses. The coupled-inductor based impedance source topologies are attracting lot of research interests and variety of applications [15] due to their benefits of high gain with reduced passive components and low cost. Two coupled-inductor derived qSBI topologies with control strategy based on space vector pulse width modulation (SVPWM) technique are presented in [45]. The benefits of CI-qSBI topologies are high boost ability and low voltage stress on the components. High voltage gain can be achieved by varying the duty cycle and turns ratio of the coupled inductor. The voltage gain of the presented topologies can be further improved by adding a boost unit. The coupled-inductor qSBI topologies are derived by adding a coupled-inductor, capacitor, and diode to the qSB network. Figure 12a,b presents two coupled-inductor qSBI topologies. In the coupled-inductor qSBI Type 1, the input ground node is directly connected to the negative node of the inverter bridge and in Type 2, the ground is not directly connected to the negative node.   The presented topologies can be extended by cascading cells to improve the voltage gain. Each cell consists of a pair of capacitor and diodes with a winding N. Figure 13 presents the extended coupled-inductor qSBI.
Electronics 2021, 10, x FOR PEER REVIEW 10 of 29 The presented topologies can be extended by cascading cells to improve the voltage gain. Each cell consists of a pair of capacitor and diodes with a winding N. Figure 13 presents the extended coupled-inductor qSBI. A three-phase qSBI topology with fault-tolerant solution is shown in Figure 14a. The fault-tolerant qSBI [46] is derived by adding three TRIACS between the source and output terminals. During an open circuit failure, the output power of the converter decreases and leads to high distortion in the AC current. To mitigate this problem, the three additional TRIACS will reconfigure the circuit and allows the continuous operation. For example, if there is an open-circuit failure in the Switch S6, then the TRIAC 3 turns ON and disconnect the control over the third-leg. The reconfigured circuit behaves like a four-switch threephase qSBI, as shown in Figure 14b, and the inverter will operate with two-legs. The TRIAC 3 connects the third phase to the input source. During fault-tolerant mode, the qSBI operates in the boost mode. This reconfiguration minimizes the impacts of the open-circuit failure.  A three-phase qSBI topology with fault-tolerant solution is shown in Figure 14a. The fault-tolerant qSBI [46] is derived by adding three TRIACS between the source and output terminals. During an open circuit failure, the output power of the converter decreases and leads to high distortion in the AC current. To mitigate this problem, the three additional TRIACS will reconfigure the circuit and allows the continuous operation. For example, if there is an open-circuit failure in the Switch S6, then the TRIAC 3 turns ON and disconnect the control over the third-leg. The reconfigured circuit behaves like a four-switch threephase qSBI, as shown in Figure 14b, and the inverter will operate with two-legs. The TRIAC 3 connects the third phase to the input source. During fault-tolerant mode, the qSBI operates in the boost mode. This reconfiguration minimizes the impacts of the open-circuit failure. The presented topologies can be extended by cascading cells to improve the voltage gain. Each cell consists of a pair of capacitor and diodes with a winding N. Figure 13 presents the extended coupled-inductor qSBI. A three-phase qSBI topology with fault-tolerant solution is shown in Figure 14a. The fault-tolerant qSBI [46] is derived by adding three TRIACS between the source and output terminals. During an open circuit failure, the output power of the converter decreases and leads to high distortion in the AC current. To mitigate this problem, the three additional TRIACS will reconfigure the circuit and allows the continuous operation. For example, if there is an open-circuit failure in the Switch S6, then the TRIAC 3 turns ON and disconnect the control over the third-leg. The reconfigured circuit behaves like a four-switch threephase qSBI, as shown in Figure 14b, and the inverter will operate with two-legs. The TRIAC 3 connects the third phase to the input source. During fault-tolerant mode, the qSBI operates in the boost mode. This reconfiguration minimizes the impacts of the open-circuit failure.  The isolated DC-DC converters are widely used for high step-up applications because of their capability to provide high voltage gain and galvanic isolation between the source side and the output side. The boost type isolated DC-DC converters are based on two stage power conversion and require a transformer and voltage lift techniques to achieve high voltage gain. The impedance source based isolated DC-DC converters were presented in [47][48][49][50][51][52] with single-stage power conversion ability and high voltage gain with the cost of increased passive components size and count. In order to overcome this drawback, an isolated high step-up DC-DC converter is presented in [53] with a qSB network, transformer and voltage double rectifier. The qSB based isolated DC-DC converter provides galvanic isolation and converts low voltage DC input to stabilized DC voltage. Figure 15  The isolated DC-DC converters are widely used for high step-up applications be cause of their capability to provide high voltage gain and galvanic isolation between the source side and the output side. The boost type isolated DC-DC converters are based on two stage power conversion and require a transformer and voltage lift techniques to achieve high voltage gain. The impedance source based isolated DC-DC converters were presented in [47][48][49][50][51][52] with single-stage power conversion ability and high voltage gain with the cost of increased passive components size and count. In order to overcome thi drawback, an isolated high step-up DC-DC converter is presented in [53] with a qSB net work, transformer and voltage double rectifier. The qSB based isolated DC-DC converte provides galvanic isolation and converts low voltage DC input to stabilized DC voltage Figure 15 presents the isolated qSB (IqSB) DC-DC converter. The switching pattern of the IqSB DC-DC converter is obtained by comparing two reference signals Vref and (1-Vref with a high frequency triangular waveform. The ST signal is generated by comparing a constant reference voltage of the range (Vref,1) with a triangular waveform of 180-degree phase-shift and then inserted into the control signals of the switches using logic gates OR The presented topology can operate either in the open-circuit or short-circuit mode with out any damage to the converter. The benefits of the IqSB DC-DC are continuous inpu current and reduced turns ratio of the isolated transformer. In comparison to the qZS de rived isolated topologies, the IqSB DC-DC converter has few passive components, resulting in reduced size and cost of the converter. Additionally, the primary and secondary voltage waveforms of the transformer remain unchanged for variable ST duty cycle and the zero time interval is independent on the ST time interval. The IqSB converter is well suitable fo applications like distributed power generation where the high stabilized DC output voltage and galvanic isolation requirements take place. In general, the grid-connected inverters can be classified into two categories as gal vanic isolation system and transformerless system. The galvanic isolation systems require either a low-frequency transformer in the AC side or a high frequency transformer in the DC side to provide isolation between the PV system and grid. This isolation limits the common mode current and ensures that no direct current is injected into the grid and thu provides safety. However, the presence of the transformer reduces the system efficiency and also increases the size and cost of the system. The transformerless system overcome the abovementioned drawback by elimination of the transformer. Among the two, the transformerless based solutions have received more attention due to their high efficiency reduced size, lightweight, and cost effectiveness. One of the major drawbacks of the trans formerless PV inverter is the generation of common-mode voltage (CMV) during opera tion. The CMV with high frequency and magnitude leads to leakage current on the stray capacitors. This leakage current increases the power losses and fastens the PV panel deg radation. The leakage current can be reduced by utilizing CMV reduction techniques like modifying the PWM strategy and system topology reconfiguration. The system reconfig uration involves the structural modification of the active and passive components or by the utilization of a CMV passive filter. The CMV passive filter blocks the leakage curren In general, the grid-connected inverters can be classified into two categories as galvanic isolation system and transformerless system. The galvanic isolation systems require either a low-frequency transformer in the AC side or a high frequency transformer in the DC side to provide isolation between the PV system and grid. This isolation limits the common mode current and ensures that no direct current is injected into the grid and thus provides safety. However, the presence of the transformer reduces the system efficiency and also increases the size and cost of the system. The transformerless system overcomes the abovementioned drawback by elimination of the transformer. Among the two, the transformerless based solutions have received more attention due to their high efficiency, reduced size, lightweight, and cost effectiveness. One of the major drawbacks of the transformerless PV inverter is the generation of common-mode voltage (CMV) during operation. The CMV with high frequency and magnitude leads to leakage current on the stray capacitors. This leakage current increases the power losses and fastens the PV panel degradation. The leakage current can be reduced by utilizing CMV reduction techniques like modifying the PWM strategy and system topology reconfiguration. The system reconfiguration involves the structural modification of the active and passive components or by the utilization of a CMV passive filter. The CMV passive filter blocks the leakage current without changing the CMV level. The drawbacks of the system reconfiguration method include complex control, increased power losses and cost. Several modified carrier-based and PWM strategies were developed over the years without changing the hardware and components. The modified carrier solutions reduce the high frequency harmonics of CMV and common-mode current (CMC). However, they have the drawbacks of high output voltage THD value and software complications. Some of the popular modulation-based CMV reduction techniques are remote state space vector PWM (RS-SVPWM), active zero state space vector PWM (AZS-SVPEM), and near state space vector PWM (NS-SVPWM) method [54][55][56][57]. The qSBI topology has the drawback of high amplitude common-mode voltage due to ST state insertion. Because of this CMV generation, the qSBI topologies are not favored for transformerless PV system applications. To overcome the effects of leakage current, a modified two-switched qSBI topology is presented with two active zero state SV-PWM (AZSTPVM) in [58]. The 2S-qSBI derived from the embedded qSBI by replacing the diode D A with an additional Switch S2 is presented in [33] with stable DC-link voltage during NST state. Figure 16a,b shows the 2S-qSBI Type 1 and Type 2 configurations. In 2S-qSBI Type 1 configuration, the switches S1 and S2 have common drain and in 2S-qSBI Type 2, the switches S1 and S2 have common source. Similar to the qSBI, the 2S-qSBI has two operating modes as ST state and NST state. In the ST state, at least one leg of the H-bridge is turned ON and in the NST state, the 2S-qSBI works like conventional VSI. The 2S-qSBI has the benefits of continuous input current, wide range of input voltage regulation and reduced system size.
Electronics 2021, 10, x FOR PEER REVIEW 12 of 29 without changing the CMV level. The drawbacks of the system reconfiguration method include complex control, increased power losses and cost. Several modified carrier-based and PWM strategies were developed over the years without changing the hardware and components. The modified carrier solutions reduce the high frequency harmonics of CMV and common-mode current (CMC). However, they have the drawbacks of high output voltage THD value and software complications. Some of the popular modulation-based CMV reduction techniques are remote state space vector PWM (RS-SVPWM), active zero state space vector PWM (AZS-SVPEM), and near state space vector PWM (NS-SVPWM) method [54][55][56][57]. The qSBI topology has the drawback of high amplitude common-mode voltage due to ST state insertion. Because of this CMV generation, the qSBI topologies are not favored for transformerless PV system applications. To overcome the effects of leakage current, a modified two-switched qSBI topology is presented with two active zero state SV-PWM (AZSTPVM) in [58]. The 2S-qSBI derived from the embedded qSBI by replacing the diode DA with an additional Switch S2 is presented in [33] with stable DC-link voltage during NST state. Figure 16a,b shows the 2S-qSBI Type 1 and Type 2 configurations. In 2S-qSBI Type 1 configuration, the switches S1 and S2 have common drain and in 2S-qSBI Type 2, the switches S1 and S2 have common source. Similar to the qSBI, the 2S-qSBI has two operating modes as ST state and NST state. In the ST state, at least one leg of the H-bridge is turned ON and in the NST state, the 2S-qSBI works like conventional VSI. The 2S-qSBI has the benefits of continuous input current, wide range of input voltage regulation and reduced system size. In the modified 2S-qSBI, an additional inductor is inserted into the negative input of the source side as shown in Figure 17a. The modified 2S-qSBI has two operation states as ST and NST state. In the ST state, switch S2 is turned ON and the ST pulses are provided to the Switch S2 along with the H-bridge inverter switches(S1-S4). In NST state, switch S2 is turned OFF and the switch S1 is turned ON. The modified 2S-qSBI is presented with two modulation techniques namely, AZSI-SVM2 and AZSI-SVM4 based on the AZ-SVM technique. In the AZSI-SVM2 method, the total ST state is divided into two parts per one control cycle with time interval as TST/2 and in AZSI-SVM4, the ST state is divided into four parts per one control cycle with time interval as TST/4. Among the two AZST-SVM methods, the AZST-SVM2 has better efficiency with reduced switching losses and AZST-SVM4 has lower input current ripples. The RMS leakage current of the M2S-qSBI with AZST-SVM2 and AZST-SVM4 technique falls in the range of the permissible range according to the standard VDE 0126-1-1 [59]. The equivalent and simplified common mode model of the modified 2S-qSBI is shown in Figure 17b,c. In the modified 2S-qSBI, an additional inductor is inserted into the negative input of the source side as shown in Figure 17a. The modified 2S-qSBI has two operation states as ST and NST state. In the ST state, switch S2 is turned ON and the ST pulses are provided to the Switch S2 along with the H-bridge inverter switches(S1-S4). In NST state, switch S2 is turned OFF and the switch S1 is turned ON. The modified 2S-qSBI is presented with two modulation techniques namely, AZSI-SVM2 and AZSI-SVM4 based on the AZ-SVM technique. In the AZSI-SVM2 method, the total ST state is divided into two parts per one control cycle with time interval as T ST /2 and in AZSI-SVM4, the ST state is divided into four parts per one control cycle with time interval as T ST /4. Among the two AZST-SVM methods, the AZST-SVM2 has better efficiency with reduced switching losses and AZST-SVM4 has lower input current ripples. The RMS leakage current of the M2S-qSBI with AZST-SVM2 and AZST-SVM4 technique falls in the range of the permissible range according to the standard VDE 0126-1-1 [59]. The equivalent and simplified common mode model of the modified 2S-qSBI is shown in Figure 17b,c. In [60], two high gain qSBI (HG-qSBI) topologies are presented with improved voltage gain obtained by inserting a capacitor and inductor to the traditional qSBI. The HG-qSBI has the benefits of high voltage gain and low voltage stress on the components. Compared to the SL-qSBI and HB-qSBI, the HG-qSBI has the lowest power losses. However, the weight and cost of the HG-qSBI are higher compared to the similar qSBI topologies and also suffers from hard switching. The HG-qSBI topologies are presented in Figure 18. To overcome the aforementioned drawbacks, a modified modulation technique based on the combination of PWM technique and phase shift was proposed for the HG-qSBI in [61]. The soft switching is achieved by the phase difference of α radian between the gating signals. The gating signals of the switched S3 and S4 are phase-shifted by a α radian compared to the gating signals of switches S1 and S2. This modified switching algorithm provides soft switching and better voltage gain with low voltage stress on the capacitors. The voltage multiplier cells are widely used in the power conversion process to produce higher voltage gain and to reduce stress on the components. A voltage multiplier In [60], two high gain qSBI (HG-qSBI) topologies are presented with improved voltage gain obtained by inserting a capacitor and inductor to the traditional qSBI. The HG-qSBI has the benefits of high voltage gain and low voltage stress on the components. Compared to the SL-qSBI and HB-qSBI, the HG-qSBI has the lowest power losses. However, the weight and cost of the HG-qSBI are higher compared to the similar qSBI topologies and also suffers from hard switching. The HG-qSBI topologies are presented in Figure 18. To overcome the aforementioned drawbacks, a modified modulation technique based on the combination of PWM technique and phase shift was proposed for the HG-qSBI in [61]. The soft switching is achieved by the phase difference of α radian between the gating signals. The gating signals of the switched S3 and S4 are phase-shifted by a α radian compared to the gating signals of switches S1 and S2. This modified switching algorithm provides soft switching and better voltage gain with low voltage stress on the capacitors. In [60], two high gain qSBI (HG-qSBI) topologies are presented with improved voltage gain obtained by inserting a capacitor and inductor to the traditional qSBI. The HG-qSBI has the benefits of high voltage gain and low voltage stress on the components. Compared to the SL-qSBI and HB-qSBI, the HG-qSBI has the lowest power losses. However, the weight and cost of the HG-qSBI are higher compared to the similar qSBI topologies and also suffers from hard switching. The HG-qSBI topologies are presented in Figure 18. To overcome the aforementioned drawbacks, a modified modulation technique based on the combination of PWM technique and phase shift was proposed for the HG-qSBI in [61]. The soft switching is achieved by the phase difference of α radian between the gating signals. The gating signals of the switched S3 and S4 are phase-shifted by a α radian compared to the gating signals of switches S1 and S2. This modified switching algorithm provides soft switching and better voltage gain with low voltage stress on the capacitors. The voltage multiplier cells are widely used in the power conversion process to produce higher voltage gain and to reduce stress on the components. A voltage multiplier  The voltage multiplier cells are widely used in the power conversion process to produce higher voltage gain and to reduce stress on the components. A voltage multiplier cell based qSBI (VMC-qSBI) was presented in [62] with a new PWM technique to achieve high voltage gain and reliability with high modulation index. Figure 19 shows the VMC-qSBI. A very high voltage gain conversion can be achieved by utilizing multi-voltage multiplier cells. The control signal for the active impedance network switch is obtained by comparing a fixed voltage signal with a double frequency triangular waveform. The ST signal is produced by comparing another fixed voltage signal with the double frequency triangular waveform and then inserted into the inverter switched using OR logic gates. cell based qSBI (VMC-qSBI) was presented in [62] with a new PWM technique to achieve high voltage gain and reliability with high modulation index. Figure 19 shows the VMC-qSBI. A very high voltage gain conversion can be achieved by utilizing multi-voltage multiplier cells. The control signal for the active impedance network switch is obtained by comparing a fixed voltage signal with a double frequency triangular waveform. The ST signal is produced by comparing another fixed voltage signal with the double frequency triangular waveform and then inserted into the inverter switched using OR logic gates. This configuration can be extended to N-number of cells by adding VMC as shown in Figure 20. Compared to other active impedance source inverters, the VMC-qSBI has continuous input current with low input ripple and ST immunity. Low THD can be achieved by using high modulation index. The drawbacks of the VMC-qSBI are high voltage stress on the components and increased component count. The VMC-qSBI topologies are well suitable for applications like the PV generator and wind power.  Table 1 presents the comparison of various qSBI derived topologies based on the most important parameters. Figures 21 and 22 give the visual representations of the boost factor and voltage gain dependencies for the enlisted topologies. The components quantity required for each topology could be evaluated from the Figure 23.  This configuration can be extended to N-number of cells by adding VMC as shown in Figure 20. Compared to other active impedance source inverters, the VMC-qSBI has continuous input current with low input ripple and ST immunity. Low THD can be achieved by using high modulation index. The drawbacks of the VMC-qSBI are high voltage stress on the components and increased component count. The VMC-qSBI topologies are well suitable for applications like the PV generator and wind power. cell based qSBI (VMC-qSBI) was presented in [62] with a new PWM technique to achieve high voltage gain and reliability with high modulation index. Figure 19 shows the VMC-qSBI. A very high voltage gain conversion can be achieved by utilizing multi-voltage multiplier cells. The control signal for the active impedance network switch is obtained by comparing a fixed voltage signal with a double frequency triangular waveform. The ST signal is produced by comparing another fixed voltage signal with the double frequency triangular waveform and then inserted into the inverter switched using OR logic gates. This configuration can be extended to N-number of cells by adding VMC as shown in Figure 20. Compared to other active impedance source inverters, the VMC-qSBI has continuous input current with low input ripple and ST immunity. Low THD can be achieved by using high modulation index. The drawbacks of the VMC-qSBI are high voltage stress on the components and increased component count. The VMC-qSBI topologies are well suitable for applications like the PV generator and wind power.  Table 1 presents the comparison of various qSBI derived topologies based on the most important parameters. Figures 21 and 22 give the visual representations of the boost factor and voltage gain dependencies for the enlisted topologies. The components quantity required for each topology could be evaluated from the Figure 23.   Table 1 presents the comparison of various qSBI derived topologies based on the most important parameters. Figures 21 and 22 give the visual representations of the boost factor and voltage gain dependencies for the enlisted topologies. The components quantity required for each topology could be evaluated from the Figure 23.    Table 1. ronics 2021, 10, x FOR PEER REVIEW 16 o Figure 22. Voltage gain as a function of the modulation index for the topologies enlisted in Table 1. Figure 23. The components required for the topologies enlisted in Table 1.
The interleaving techniques are gaining a lot of popularity in recent years due to th high efficiency in wide power range applications and reduced conduction losses achiev by splitting the current paths. The multiphase interleaving techniques provide enhanc power density, high voltage gain, reduced current ripples, and passive components. [63], an interleaved topology based on the qZSI (IqZSI) is presented with a control tec nique based on the combination of phase-shifted PWM and SBC Technique. The present topology combines the benefits of qZSI topology and VSI with interleaved parallel le The IqZSI topology has higher power density, smaller output filter, and reduced outp THD. The drawbacks of this approach are reduced boost factor and poor DC-Link utili tion. To overcome these drawbacks, IqZSI is presented with a modified modulation tec nique based on the MBC technique. In a single-phase system, the direct application of t MBC technique generates high voltage distortions and DC-Link voltage ripples due to t    Table 1.
The interleaving techniques are gaining a lot of popularity in recent years due to their high efficiency in wide power range applications and reduced conduction losses achieved by splitting the current paths. The multiphase interleaving techniques provide enhanced power density, high voltage gain, reduced current ripples, and passive components. In [63], an interleaved topology based on the qZSI (IqZSI) is presented with a control technique based on the combination of phase-shifted PWM and SBC Technique. The presented topology combines the benefits of qZSI topology and VSI with interleaved parallel legs. The IqZSI topology has higher power density, smaller output filter, and reduced output THD. The drawbacks of this approach are reduced boost factor and poor DC-Link utilization. To overcome these drawbacks, IqZSI is presented with a modified modulation technique based on the MBC technique. In a single-phase system, the direct application of the MBC technique generates high voltage distortions and DC-Link voltage ripples due to the variable width of the ST states. Due to this, a modified MBC technique with smooth vari-  Table 1.
The interleaving techniques are gaining a lot of popularity in recent years due to their high efficiency in wide power range applications and reduced conduction losses achieved by splitting the current paths. The multiphase interleaving techniques provide enhanced power density, high voltage gain, reduced current ripples, and passive components. In [63], an interleaved topology based on the qZSI (IqZSI) is presented with a control technique based on the combination of phase-shifted PWM and SBC Technique. The presented topology combines the benefits of qZSI topology and VSI with interleaved parallel legs. The IqZSI topology has higher power density, smaller output filter, and reduced output THD. The drawbacks of this approach are reduced boost factor and poor DC-Link utilization. To overcome these drawbacks, IqZSI is presented with a modified modulation technique based on the MBC technique. In a single-phase system, the direct application of the MBC technique generates high voltage distortions and DC-Link voltage ripples due to the variable width of the ST states. Due to this, a modified MBC technique with smooth variable D S is presented in [64]. The modified MBC based IqZSI topology has better DC-Link voltage stabilization and higher boost factor. The presented technique has the drawbacks of worse THD compared to the SBC technique. In [65], IqZSI is presented with APD configuration resulting in reduction in the passive components. The IqZSI is extended to PV application with different control approaches and modulation techniques in [66][67][68]. Figure 24a shows the interleaved qSBI for single-phase application (IqSBI). In [69], the IqSBI topology is presented with a modified MBC technique and quasi-sinusoidal modulation (qSM) technique. The IqSBI and AqZSI configurations are obtained by replacing the qZSI topology in [64]. In modified MBC technique, the control states for the switches in the top and bottom inverter are generated by comparing two sinusoidal reference signals of 180 • phase-shift with two carrier signals of 90 • phase-shift. The top and bottom envelopes are generated by the maximum and minimum of the two sinusoidal reference signals and smoothen by the next auxiliary signals. The ST states are generated based on the auxiliary signals. They are inserted into the control signal of the top and bottom inverter switches by using logic gate function OR. The control signals for the switch SA and SB are generated by comparing a constant voltage signal with a double frequency carrier signal. To improve the boosting ability, a qSM technique is presented for the interleaved topologies in [69]. In [70], qSM technique is presented for the single-phase qZSI. In qSM strategy, the control signal for the top and bottom inverter can be generated by comparing two reference signals with two carrier signals of 90 • phase-shift. The reference signals are triggered by minimum of the reference signal with a constant voltage signal, as shown in Figure 24b. The control signal for the Switch SA and SB are generated by comparing a constant voltage signal with double frequency carrier signal. The interleaved topologies perform better using qSM technique compared to the modified MBC modulation technique. The IqSBI has the advantage of reduced passive components and better performance compared to IqZSI for lower power applications. application with different control approaches and modulation techniques in [66][67][68]. Figure 24a shows the interleaved qSBI for single-phase application (IqSBI). In [69], the IqSBI topology is presented with a modified MBC technique and quasi-sinusoidal modulation (qSM) technique. The IqSBI and AqZSI configurations are obtained by replacing the qZSI topology in [64]. In modified MBC technique, the control states for the switches in the top and bottom inverter are generated by comparing two sinusoidal reference signals of 180° phase-shift with two carrier signals of 90° phase-shift. The top and bottom envelopes are generated by the maximum and minimum of the two sinusoidal reference signals and smoothen by the next auxiliary signals. The ST states are generated based on the auxiliary signals. They are inserted into the control signal of the top and bottom inverter switches by using logic gate function OR. The control signals for the switch SA and SB are generated by comparing a constant voltage signal with a double frequency carrier signal. To improve the boosting ability, a qSM technique is presented for the interleaved topologies in [69]. In [70], qSM technique is presented for the single-phase qZSI. In qSM strategy, the control signal for the top and bottom inverter can be generated by comparing two reference signals with two carrier signals of 90° phase-shift. The reference signals are triggered by minimum of the reference signal with a constant voltage signal, as shown in Figure 24b. The control signal for the Switch SA and SB are generated by comparing a constant voltage signal with double frequency carrier signal. The interleaved topologies perform better using qSM technique compared to the modified MBC modulation technique. The IqSBI has the advantage of reduced passive components and better performance compared to IqZSI for lower power applications. The multilevel inverters are gaining a lot of research interests due to the increasing power-scale demands. The major benefits of multilevel inverters include lower electromagnetic interference, improved output waveforms, allows use of smaller size filter, and lower THD. Among the multilevel inverter structures, the cascaded H-bridge inverters has the benefits of high reliability, reduced filter size, and higher output voltage compared to the neutral point clamped (NPC) and flying capacitor (FC) type topologies. The cas- The multilevel inverters are gaining a lot of research interests due to the increasing power-scale demands. The major benefits of multilevel inverters include lower electro-magnetic interference, improved output waveforms, allows use of smaller size filter, and lower THD. Among the multilevel inverter structures, the cascaded H-bridge inverters has the benefits of high reliability, reduced filter size, and higher output voltage compared to the neutral point clamped (NPC) and flying capacitor (FC) type topologies. The cascaded H-bridge (CHB) inverter utilize separate sources and cascade multiple H-bridge modules to generate the total output voltage. The CHB inverter has the advantage of high reliability due to its modular structure and reduced output filter size. However, the CHB inverter has the drawback of limited DC-AC power conversion and short-circuit issues. Several qZSI derived CHB inverter topologies were presented [71][72][73][74] to overcome the problems of the CHB-VSI and provide single-stage power conversion. The CHB-qZSI utilize multiple qZSI network with large number of passive components and results in increased size and cost of system.
A quasi-CHB five-level boost inverter (qCHB-FLBI) is presented in [75] with a phaseshifted PWM (PS-SPWM) technique. Compared to the CHB-qZSI, the qCHB-FLBI topology have the benefits of reduced inductor current ripples, lower output current THD, and passive components. The qCHB-FLBI utilize two quasi-boost modules with separate DC sources and an inductor filter to produce five-level output voltage. Each quasi-boost module consist of one inductor, capacitor, two diodes and four switches. Figure 25 presents the quasi-cascaded H-bridge five-level boost inverter. Several qZSI derived CHB inverter topologies were presented [71][72][73][74] to overcome the problems of the CHB-VSI and provide single-stage power conversion. The CHB-qZSI utilize multiple qZSI network with large number of passive components and results in increased size and cost of system. A quasi-CHB five-level boost inverter (qCHB-FLBI) is presented in [75] with a phaseshifted PWM (PS-SPWM) technique. Compared to the CHB-qZSI, the qCHB-FLBI topology have the benefits of reduced inductor current ripples, lower output current THD, and passive components. The qCHB-FLBI utilize two quasi-boost modules with separate DC sources and an inductor filter to produce five-level output voltage. Each quasi-boost module consist of one inductor, capacitor, two diodes and four switches. Figure 25 presents the quasi-cascaded H-bridge five-level boost inverter. A single-phase CHB based on the qSBI topology is presented in [76,77] with an improved phase-shifted sinusoidal PWM control strategy to generate the DC-link voltage. The single phase cascaded qSBI utilize two qSBI networks connected to separate DC sources with two H-bridge modules and an inductive filter. The output voltage of the cascaded qSBI can be extended by cascading multiple qSBI networks. The control signals for the switches in each H-bridge are generated separately using two triangular waveforms of phase shifted in 90-degree. The control signal for the qSB network switch is generated by comparing a constant voltage signal with triangular waveform of half amplitude and double frequency of another triangular waveform. This control signal is then inserted into the control signals of H-bridge switches using logic gates OR to generate the ST states. Each H-bridge module has three output voltage level and the output of the cascaded qSBI system is the total sum of the H-bridge module outputs. The CHB-qSBI utilize reduced number of passive components than the CHB-qZSI and offers compact system well suitable for low power applications. Figure 26 shows the single-phase cascaded H-Bridge qSBI presented in with two DC sources and two qSBI modules. A single-phase CHB based on the qSBI topology is presented in [76,77] with an improved phase-shifted sinusoidal PWM control strategy to generate the DC-link voltage. The single phase cascaded qSBI utilize two qSBI networks connected to separate DC sources with two H-bridge modules and an inductive filter. The output voltage of the cascaded qSBI can be extended by cascading multiple qSBI networks. The control signals for the switches in each H-bridge are generated separately using two triangular waveforms of phase shifted in 90-degree. The control signal for the qSB network switch is generated by comparing a constant voltage signal with triangular waveform of half amplitude and double frequency of another triangular waveform. This control signal is then inserted into the control signals of H-bridge switches using logic gates OR to generate the ST states. Each H-bridge module has three output voltage level and the output of the cascaded qSBI system is the total sum of the H-bridge module outputs. The CHB-qSBI utilize reduced number of passive components than the CHB-qZSI and offers compact system well suitable for low power applications. Figure 26 shows the single-phase cascaded H-Bridge qSBI presented in with two DC sources and two qSBI modules. In [78], a three-phase cascaded H-bridge qSBI is presented as an alternative solution to the impedance source based cascaded H-bridge inverter. The three-phase CHB-qSBI utilizes six qSBI modules with six separate DC sources and produces five-level output phase voltage. Compared to the three-phase CHB-qZSI, the presented configuration has fewer passive components resulting in reduced size and power losses. The CHB-qSBI has drawbacks of higher voltage stress across the passive components and limitations of using a small modulation value to achieve high voltage gain because of the conventional PWM technique. Figure 27 presents the three-phase CHB-qSBI topology.  In [78], a three-phase cascaded H-bridge qSBI is presented as an alternative solution to the impedance source based cascaded H-bridge inverter. The three-phase CHB-qSBI utilizes six qSBI modules with six separate DC sources and produces five-level output phase voltage. Compared to the three-phase CHB-qZSI, the presented configuration has fewer passive components resulting in reduced size and power losses. The CHB-qSBI has drawbacks of higher voltage stress across the passive components and limitations of using a small modulation value to achieve high voltage gain because of the conventional PWM technique. Figure 27 presents the three-phase CHB-qSBI topology. In [78], a three-phase cascaded H-bridge qSBI is presented as an alternative solution to the impedance source based cascaded H-bridge inverter. The three-phase CHB-qSBI utilizes six qSBI modules with six separate DC sources and produces five-level output phase voltage. Compared to the three-phase CHB-qZSI, the presented configuration has fewer passive components resulting in reduced size and power losses. The CHB-qSBI has drawbacks of higher voltage stress across the passive components and limitations of using a small modulation value to achieve high voltage gain because of the conventional PWM technique. Figure 27 presents the three-phase CHB-qSBI topology.  A cascaded three-phase five-level inverter is presented in [79] with a PWM technique to improve the modulation index. The CHB-qSBI overcomes the voltage imbalance problems of the traditional CHB inverter by the implementation of an improved phase-shifted sinusoidal PWM strategy. This improved phase-shifted SPWM strategy overcomes the voltage imbalance problems by utilization of the indirect DC-Link voltage control method by controlling and stabilizing the capacitor voltage. Compared to the CHB qZSI, the presented topology has the advantage of reduced size and cost. Additionally, the CHB qSBI has lower output voltage THD and stable operation in both balanced and unbalanced input voltage modes. In [80], a DC-Link quasi-switched boost cascaded multilevel inverter (DqSB-CMI) is presented for grid-tied applications. It utilizes three DC sources connected separately to three DqSB modules with an inductor filter. Figure 28 presents the mentioned DqSB-CMI. It utilizes a modified PWM method presented in [37]. The DqSB-CMI has the benefits of active and reactive power control capability, reduced voltage stress on the components and overcomes DC-Link voltage imbalance problems. The DqSB-CMI based distributed generation systems have reduced volume and weight compared to ZSI/qZSI based systems.
Electronics 2021, 10, x FOR PEER REVIEW 20 of 2 A cascaded three-phase five-level inverter is presented in [79] with a PWM techniqu to improve the modulation index. The CHB-qSBI overcomes the voltage imbalance prob lems of the traditional CHB inverter by the implementation of an improved phase-shifte sinusoidal PWM strategy. This improved phase-shifted SPWM strategy overcomes th voltage imbalance problems by utilization of the indirect DC-Link voltage control metho by controlling and stabilizing the capacitor voltage. Compared to the CHB qZSI, the pre sented topology has the advantage of reduced size and cost. Additionally, the CHB qSBI ha lower output voltage THD and stable operation in both balanced and unbalanced inpu voltage modes. In [80], a DC-Link quasi-switched boost cascaded multilevel inverter (DqSB CMI) is presented for grid-tied applications. It utilizes three DC sources connected sepa rately to three DqSB modules with an inductor filter. Figure 28 presents the mentione DqSB-CMI. It utilizes a modified PWM method presented in [37]. The DqSB-CMI has th benefits of active and reactive power control capability, reduced voltage stress on the com ponents and overcomes DC-Link voltage imbalance problems. The DqSB-CMI based dis tributed generation systems have reduced volume and weight compared to ZSI/qZSI base systems. The VSIs are widely used in the distributed power systems for DC-AC power con version. To achieve higher AC output voltage conversion, the VSI requires an additiona two-level and three-level DC-DC converter to boost the low input DC voltage. To over come the two-stage power conversion and ST issues of three-level boost inverters, imped ance-source network integrated multilevel inverters were presented with single-stag power conversion and ST immunity [81]. The 3L-ZSI [82] utilize two ZS networks, tw isolated DC sources and a three-level NPC inverter. The presence of two LC network increases the volume and cost of the inverter. Three phase 3L-NPC inverter with single Z source network was reported in [83] derived by connecting the midpoint of the DC source with the neutral point of the NPC inverter. The ZSI based 3L-NPC has the drawbacks o high component stress, discontinuous input current and low voltage gain. To overcom aforementioned drawbacks, quasi-Z-source based 3L-NPC multilevel inverter is presente in [84] with continuous input current. In [85], a three-level LC-switching based voltage boos NPC inverter is presented. The 3L LC-switching based voltage boost NPC inherits the ad The VSIs are widely used in the distributed power systems for DC-AC power conversion. To achieve higher AC output voltage conversion, the VSI requires an additional two-level and three-level DC-DC converter to boost the low input DC voltage. To overcome the two-stage power conversion and ST issues of three-level boost inverters, impedancesource network integrated multilevel inverters were presented with single-stage power conversion and ST immunity [81]. The 3L-ZSI [82] utilize two ZS networks, two isolated DC sources and a three-level NPC inverter. The presence of two LC networks increases the volume and cost of the inverter. Three phase 3L-NPC inverter with single Z-source network was reported in [83] derived by connecting the midpoint of the DC sources with the neutral point of the NPC inverter. The ZSI based 3L-NPC has the drawbacks of high component stress, discontinuous input current and low voltage gain. To overcome aforementioned drawbacks, quasi-Z-source based 3L-NPC multilevel inverter is presented in [84] with continuous input current. In [85], a three-level LC-switching based voltage boost NPC inverter is presented. The 3L LC-switching based voltage boost NPC inherits the advantages of quasi-Z-source based 3L-NPC multilevel inverter with reduced passive components. The gating signals for the switches are generated using unipolar PWM technique. Figure 29 presents the 3L LC-switching voltage boost NPC inverter. vantages of quasi-Z-source based 3L-NPC multilevel inverter with reduced passive components. The gating signals for the switches are generated using unipolar PWM technique. Figure 29 presents the 3L LC-switching voltage boost NPC inverter. In [86], a switched-capacitor qSB based NPC multilevel inverter is presented with multi-carrier level-shifted PWM technique. The SC-qSB NPC multilevel inverter can be further extended by adding multi-cell switched-capacitor cell arrangement to achieve high voltage gain. The control signals for the switches are generated by comparing three modulating signals of 120° phase shift with two triangular signals and two ST reference signals. The gating signals of the switches SP and SN are generated by comparing the ST signals and two triangular signals. The gating signals of the inverter leg switches are generated by comparing the modulating waveforms with triangular waveforms and then the ST signals are inserted using logic gate OR. Figure 30 presents switched-capacitor qSB based NPC multilevel inverter topology.  In [86], a switched-capacitor qSB based NPC multilevel inverter is presented with multi-carrier level-shifted PWM technique. The SC-qSB NPC multilevel inverter can be further extended by adding multi-cell switched-capacitor cell arrangement to achieve high voltage gain. The control signals for the switches are generated by comparing three modulating signals of 120 • phase shift with two triangular signals and two ST reference signals. The gating signals of the switches SP and SN are generated by comparing the ST signals and two triangular signals. The gating signals of the inverter leg switches are generated by comparing the modulating waveforms with triangular waveforms and then the ST signals are inserted using logic gate OR. Figure 30 presents switched-capacitor qSB based NPC multilevel inverter topology. vantages of quasi-Z-source based 3L-NPC multilevel inverter with reduced passive components. The gating signals for the switches are generated using unipolar PWM technique. Figure 29 presents the 3L LC-switching voltage boost NPC inverter. In [86], a switched-capacitor qSB based NPC multilevel inverter is presented with multi-carrier level-shifted PWM technique. The SC-qSB NPC multilevel inverter can be further extended by adding multi-cell switched-capacitor cell arrangement to achieve high voltage gain. The control signals for the switches are generated by comparing three modulating signals of 120° phase shift with two triangular signals and two ST reference signals. The gating signals of the switches SP and SN are generated by comparing the ST signals and two triangular signals. The gating signals of the inverter leg switches are generated by comparing the modulating waveforms with triangular waveforms and then the ST signals are inserted using logic gate OR. Figure 30 presents switched-capacitor qSB based NPC multilevel inverter topology.  A three-phase 3L qZSI is presented in [87] with improved current profile and reduced component size. The three-phase 3L qZSI comprises of a 3L T-Type inverter and two symmetrical qZS network. However, the large passive components in the impedance source based 3L inverters results in increased size, weight and cost of the inverter. The qSBI derived topologies are gaining a lot of interest in the distributed generation applications because of their reduced size and cost.
In [88], a three-level quasi-switched boost T-type inverter (3L-qSBT2I) is presented with anti-series switches configuration. Figure 31 shows the three-level qSB T-type inverter. The 3L-qSBT2I with anti-series configuration is derived by incorporating qSB network to the conventional 3L T-Type inverter front structure. The neutral point is connected to the load using three bidirectional switches. Each bidirectional switch consists of two switches connected in series configuration. The advantage of 3L-qSBT2I include improved voltage gain, very low input current ripple, and ST immunity. A three-phase 3L qZSI is presented in [87] with improved current profile and reduced component size. The three-phase 3L qZSI comprises of a 3L T-Type inverter and two symmetrical qZS network. However, the large passive components in the impedance source based 3L inverters results in increased size, weight and cost of the inverter. The qSBI derived topologies are gaining a lot of interest in the distributed generation applications because of their reduced size and cost.
In [88], a three-level quasi-switched boost T-type inverter (3L-qSBT2I) is presented with anti-series switches configuration. Figure 31 shows the three-level qSB T-type inverter. The 3L-qSBT2I with anti-series configuration is derived by incorporating qSB network to the conventional 3L T-Type inverter front structure. The neutral point is connected to the load using three bidirectional switches. Each bidirectional switch consists of two switches connected in series configuration. The advantage of 3L-qSBT2I include improved voltage gain, very low input current ripple, and ST immunity. In [89], a controlled diode bridge clamped qSB three-level inverter is presented. Figure 32 shows the three-level qSB T-Type inverter with controlled diode bridge clamp (CDBC) switch configurations. The conventional T-Type three-phase inverter utilizes three bidirectional switches with six IGBTs, made with an anti-series configuration of two IGBTs per phase leg. In the CDBC three-level inverter, the DC bus midpoint of each phase leg is connected by a bidirectional switch constructed by the combination of one IGBT and four diodes. The CDBC qSB-3L has the drawbacks of IGBT switch operating at the double frequency of the switches in phase legs. Additionally, the presence of one more diode in the conduction path results in power loss. In [90], a SVPWM scheme with reduced inductor current is presented for 3L-qSBT2I. This modulation scheme utilizes high value of modulation index by maintaining constant ST duty cycle. The presented technique has the advantage of improved voltage gain achieved by controlling the duty cycle of the two switches. A fault-tolerant 3L-qSBT2I is presented in [91] with ability to operate in normal and fault modes. In [87], a fault tolerant Z-source inverter is presented with a PWM technique controlled by ST duty cycle and modulation index M. During the fault mode, the inverter is operated with low modulation index and high ST duty cycle. This operation reduces the output quality of the inverter and result in high ST currents, increased voltage stress and power losses. To overcome the mentioned drawbacks, a fault-tolerant PWM control technique based on low ST duty-cycle and high modulation index is presented in [92]. The fault tolerant 3L-qSBT2I has the benefits of reduced input current ripple and voltage stress on the switches and capacitors. In [93,94], SVM technique with CMV reduction is presented for 3L-qSBT2I with the features of reduced CMV, low inductor current ripple, ST immunity, and allows use of high modulation index. In the conventional SVM CMV reduction technique [95], the reference vector is generated using the large, medium and zero vectors. In this technique, the reference vectors are generated using medium and zero vectors. In [89], a controlled diode bridge clamped qSB three-level inverter is presented. Figure 32 shows the three-level qSB T-Type inverter with controlled diode bridge clamp (CDBC) switch configurations. The conventional T-Type three-phase inverter utilizes three bidirectional switches with six IGBTs, made with an anti-series configuration of two IGBTs per phase leg. In the CDBC three-level inverter, the DC bus midpoint of each phase leg is connected by a bidirectional switch constructed by the combination of one IGBT and four diodes. The CDBC qSB-3L has the drawbacks of IGBT switch operating at the double frequency of the switches in phase legs. Additionally, the presence of one more diode in the conduction path results in power loss. In [90], a SVPWM scheme with reduced inductor current is presented for 3L-qSBT2I. This modulation scheme utilizes high value of modulation index by maintaining constant ST duty cycle. The presented technique has the advantage of improved voltage gain achieved by controlling the duty cycle of the two switches. A fault-tolerant 3L-qSBT2I is presented in [91] with ability to operate in normal and fault modes. In [87], a fault tolerant Z-source inverter is presented with a PWM technique controlled by ST duty cycle and modulation index M. During the fault mode, the inverter is operated with low modulation index and high ST duty cycle. This operation reduces the output quality of the inverter and result in high ST currents, increased voltage stress and power losses. To overcome the mentioned drawbacks, a fault-tolerant PWM control technique based on low ST duty-cycle and high modulation index is presented in [92]. The fault tolerant 3L-qSBT2I has the benefits of reduced input current ripple and voltage stress on the switches and capacitors. In [93,94], SVM technique with CMV reduction is presented for 3L-qSBT2I with the features of reduced CMV, low inductor current ripple, ST immunity, and allows use of high modulation index. In the conventional SVM CMV reduction technique [95], the reference vector is generated using the large, medium and zero vectors. In this technique, the reference vectors are generated using medium and zero vectors. In [96], a three level DC-Link qSB T-Type inverter is presented. The 3L-DqSBTI incorporates a DC-Link qSBI topology with 3L T-Type inverter. The 3L-DqSBTI utilize the SVPWM technique with enhanced modulation index. The 3L-DqSBT2I has a better voltage gain and boost factor compared to the conventional 3qSB T-Type inverter. The 3L-DqSBT2I has reduced voltage stress on the components and reduced CMV magnitude. The CDBC configuration has the advantage of three less IGBT switches and its associated gate driver and circuit elements compared to the conventional T-Type. Figure 33 presents the three-level DC-Link qSB T-Type inverter. Table 2 presents the comparison of qSB derived configurations based on the most important parameters. The components quantity required for each configuration could be evaluated from the Figure 34.   In [96], a three level DC-Link qSB T-Type inverter is presented. The 3L-DqSBTI incorporates a DC-Link qSBI topology with 3L T-Type inverter. The 3L-DqSBTI utilize the SVPWM technique with enhanced modulation index. The 3L-DqSBT2I has a better voltage gain and boost factor compared to the conventional 3qSB T-Type inverter. The 3L-DqSBT2I has reduced voltage stress on the components and reduced CMV magnitude. The CDBC configuration has the advantage of three less IGBT switches and its associated gate driver and circuit elements compared to the conventional T-Type. Figure 33 presents the three-level DC-Link qSB T-Type inverter. Table 2 presents the comparison of qSB derived configurations based on the most important parameters. The components quantity required for each configuration could be evaluated from the Figure 34. In [96], a three level DC-Link qSB T-Type inverter is presented. The 3L-DqSBTI incorporates a DC-Link qSBI topology with 3L T-Type inverter. The 3L-DqSBTI utilize the SVPWM technique with enhanced modulation index. The 3L-DqSBT2I has a better voltage gain and boost factor compared to the conventional 3qSB T-Type inverter. The 3L-DqSBT2I has reduced voltage stress on the components and reduced CMV magnitude. The CDBC configuration has the advantage of three less IGBT switches and its associated gate driver and circuit elements compared to the conventional T-Type. Figure 33 presents the three-level DC-Link qSB T-Type inverter. Table 2 presents the comparison of qSB derived configurations based on the most important parameters. The components quantity required for each configuration could be evaluated from the Figure 34.      Table 2.

Discussion
Efficiency is an important factor to be considered in the selection of the power converter. The total losses in the converter have direct impact on the efficiency of the system. The major contributors of the total power losses in converters are switches, inductors, and diodes. Compared to the qZSI topology, the basic qSBI topologies has reduced passive components resulting in lower inductor loss and power switch loss. Therefore, the qSBI topology has lower power loss than the qZSI. Additionally, the parasitic system effect in qZSI is higher than qSBI. The qSBI has the same features of the qZSI with better efficiency in low and medium power applications. The drawback of the qSBI is high voltage stress in capacitor and the low frequency ripple issue. The qSBI is not preferred for high voltage gain applications where high boost voltage is required because of the high voltage stress on the components and switches. The SL-qSBI has high power loss and input ripples. The cSL-qSBI offers high power density and better efficiency than the switched inductor based ZSI and qZSI topologies at low realization cost and reduced components. The SC-qSBI has higher efficiency compared to the SL-qSBI. However, the voltage stress in the qSB network switch is high and also the voltage gain is not up to the desired level. A 500W prototype of SC-qSBI in grid-connected and stand-alone mode operation is presented in [44] with efficiency of 91.5%. The FS-qSBI derived by combining the ST and conventional inverter operation by removing the extra switch has improved efficiency. Similar to the qSBI, the FS-qSBI also suffers from low frequency ripple issue. To mitigate the low frequency ripple issue in FS-qSBI, low frequency ripple damping scheme and APD configuration could be used. The CI-qSBI has high voltage gain and reduced stress on the components. In addition, the voltage gain can be improved by adjusting the duty cycle and turns ratio without operating the circuit in higher duty cycle. A 200W prototype of the CI-qSBI is presented  Table 2.

Discussion
Efficiency is an important factor to be considered in the selection of the power converter. The total losses in the converter have direct impact on the efficiency of the system. The major contributors of the total power losses in converters are switches, inductors, and diodes. Compared to the qZSI topology, the basic qSBI topologies has reduced passive components resulting in lower inductor loss and power switch loss. Therefore, the qSBI topology has lower power loss than the qZSI. Additionally, the parasitic system effect in qZSI is higher than qSBI. The qSBI has the same features of the qZSI with better efficiency in low and medium power applications. The drawback of the qSBI is high voltage stress in capacitor and the low frequency ripple issue. The qSBI is not preferred for high voltage gain applications where high boost voltage is required because of the high voltage stress on the components and switches. The SL-qSBI has high power loss and input ripples. The cSL-qSBI offers high power density and better efficiency than the switched inductor based ZSI and qZSI topologies at low realization cost and reduced components. The SC-qSBI has higher efficiency compared to the SL-qSBI. However, the voltage stress in the qSB network switch is high and also the voltage gain is not up to the desired level. A 500W prototype of SC-qSBI in grid-connected and stand-alone mode operation is presented in [44] with efficiency of 91.5%. The FS-qSBI derived by combining the ST and conventional inverter operation by removing the extra switch has improved efficiency. Similar to the qSBI, the FS-qSBI also suffers from low frequency ripple issue. To mitigate the low frequency ripple issue in FS-qSBI, low frequency ripple damping scheme and APD configuration could be used. The CI-qSBI has high voltage gain and reduced stress on the components. In addi-tion, the voltage gain can be improved by adjusting the duty cycle and turns ratio without operating the circuit in higher duty cycle. A 200W prototype of the CI-qSBI is presented in [45] with efficiency of 93.1%. The qSBI derived configurations have reduced components and enhanced efficiency compared to the impedance source derived configurations. The qSBI derived configurations are preferable for low and medium power applications due to their reduced size, weight and cost. The voltage multiplier cell based qSBI topologies are suitable for renewable energy related applications such as wind power. The T-Type qSBI topologies are suitable for applications like UPS, motor drives, and photovoltaic systems. The cascaded qSBI topologies are well suitable for distributed generation systems. Several fault-tolerant techniques and common-mode-voltage regulation methods are introduced for the qSBI family to improve the efficiency and reliability. The efficiency of the converter can be further enhanced by the utilization of high performance MOSFET switches. Future research could be directed towards bidirectional operation, utilization of new semiconductor devices, and implementations in emerging applications related to renewable energy-based systems, particularly autonomous power supply PV-based systems.

Conclusions
A review of qSBI and their topological variations has been presented with comparison and analysis based on the most important parameters. Several derived topologies were developed to improve the moderate voltage gain of the qSBI. The benefits and drawbacks of each configuration are presented and an overview comparison of the qSB derived topologies is summarized. The qSBI derived topologies have the benefit of enhanced voltage gain with reduced voltage stresses on the components and replace the impedance source converter in low power applications. The efficiency of the converter can be further enhanced by the utilization of high performance MOSFET switches. Future research could be directed towards bidirectional operation, utilization of new semiconductor devices and implementations in emerging applications related to renewable energy-based systems including autonomous power supply photovoltaic based systems.