Hybrid Multicarrier Random Space Vector PWM for the Mitigation of Acoustic Noise

: The pulse width modulation (PWM) inverter is an obvious choice for any industrial and power sector application. Particularly, industrial drives beneﬁt from the higher DC-link utilization, acoustic noise, and vibration industrial standards. Many PWM techniques have been proposed to meet the drives’ demand for higher DC-link utilization and lower harmonics suppression and noise reductions. Still, random PWM (RPWM) is the best candidate for reducing the acoustic noises. Few RPWM (RPWM) methods have been developed and investigated for the AC drive’s PWM inverter. However, due to the lower randomness of the multiple frequency harmonics spectrum, reducing the drive noise is still challenging. These PWMs dealt with the spreading harmonics, thereby decreasing the harmonic effects on the system. However, these techniques are unsuccessful at maintaining the higher DC-link utilizations. Existing RPWM methods have less randomness and need complex digital circuitry. Therefore, this paper mainly deals with a combined RPWM principle in space vector PWM (SVPWM) to generate random PWM generation using an asymmetric frequency multicarrier called multicarrier random space vector PWM (MCRSVPWM). he SVPWM switching vectors with different frequency carrier are chosen with the aid of a random bi-nary bit generator. The proposed MCRSVPWM generates the pulses with a randomized triangular carrier (1 to 4 kHz), while the conventional RPWM method contains a random pulse position with a triangular carrier. The proposed PWM is capable of eradicating the high-frequency unpleasant acoustic noise more effectually than conventional RPWM with a shorter random frequency range. The simulation study is performed through MATLAB/Simulink for a 2 kW asynchronous induction motor drive. Experimental validation of the proposed MCRSVPWM is tested with a 2 kW six-switch (Power MOSFET–SCH2080KE) inverter power module-fed induction motor drive.


Introduction
Pulse width modulated-based voltage source inverters (VSIs) are an unavoidable segment of industrial drive systems. These VSIs are needed in order to provide several advantages such as harmonics elimination, DC link utilization, common mode voltage present influences the amount of repetition. The sinusoidal reference is compared with the winning triangle carrier cycle in order to get the gating pulses. Still, various random PWM methods have been developed and investigated for the PWM inverter-fed drive noise reductions; still, the shortcomings of these method items include their lower randomness and complex digital circuitry.
Some of the PWM methods dealt with the spreading harmonics by decreasing the harmonic effects on the system. However, these techniques overlook the effect of acoustic noise and inverter DC-link utilizations. Therefore, this paper mainly deals with a combined RPWM principle in space vector PWM to generate random PWM generation. The SVPWM agreements with the multicarrier (different fixed frequencies as carrier waves) are chosen with the aid of a random binary bit generator. The proposed RSVM generated pulses with a randomized triangular carrier (1 kHz to 4 kHz), while the conventional RPWM method contains a random pulse position with a fixed frequency triangular carrier. The proposed PWM is capable of eradicating the high-frequency unpleasant acoustic noise more effectually than conventional RPWM with a shorter random frequency range.
The Field Programmable Gate Array (FPGA)-based two PRBS bit (8 bit and 16 bit) generators are used to generate the random binary. The SVPWM was developed using the same FPGA controller, and it is getting random carriers from a PRBS binary selector block. The simulation study is performed through MATLAB/Simulink software tool (2016.b) for a three-phase VSI connected 2 kW, 400 V, 2.5 A asynchronous induction motor drive. The experimental validation of the proposed RSVM is tested with a 2 kW six switch (Power MOSFET-SCH2080KE) inverter power module-fed induction motor drive. The simulation and hardware results show that the VSI and motor had comparable performance to the conventional MCRSVPWM; nevertheless, the noise power spectra of the current, voltage, dominant harmonic components, and acoustic noise spectra were reduced as compared with the reported RPWM methods. This paper is structured as fellows: Section 2 reviews the random pulse width modulation operating principles. In Section 3, the proposed Multicarrier Random Space Vector PWM is presented and analyzed. Sections 4 and 5 present the simulation and experimental results, respectively. Section 6 concludes the paper.

Review of Random Pulse Width Modulation
The important variance between standard PWM and random PWM methods is that the pulse width signal is no longer restricted to a few fundamental frequencies. The control relies on switching frequency (carrier frequency) and the modulated signal.
The following section explains the RPWM generation for six switch voltage source inverters. The VSI is shown is Figure 1, where three legs and six switches are used to synthesize three-phase AC power. The VSI should generate the symmetry-less THD voltage and current. The reduction of THD is possible for spreading the harmonics spectra. Figure 2 shows the RPWM pulse arrangement. Here, the random carrier is achieved through a digital binary assignment process PRBS. In general, the RPWM processes triangular carrier waves (fixed frequency carrier), and multiplexer and shift register are used in the random carrier. Figure 2 shows the conventional pseudorandom binary sequence RPWM.  Here, the 'C-' is the opposite phase of 'C' derived using 'NOT' gate. The 'C' and 'Care randomly chosen, and the triangular carrier waves with fixed frequency "C-" with a opposite phase of "C" are given by the selected signal (P) of the multiplexer. The multi plexer is a combinational logic circuit designed to switch one of several input line through to a single common output line by the application of a control signal. The MUX obtains the selected signal through the pseudorandom binary sequence shift register. Th PRBS shift register is normally an 8/16 bit register, including the Exclusive OR (XOR) gate Based on the values of the particular bit, the PRBS gives random binary logic.
In Figure 3, the '2 × 1' multiplexer selects 'C', where 'P' is '1'. Similarly, when 'P' i '1', then 'C-' is selected. The reported pseudorandom frequency used two triangula waveforms with the same frequency to synthesize the proposed random carrier. There fore, the randomness is limited. Hence, the proposed random carrier technique uses th multiple randomness by using different frequency carriers.  Figure 2 shows that the fixed frequency triangular carrier 'C' is given through multiplexer (MUX) in 'C' and 'C-' sequence.   Here, the 'C-' is the opposite phase of 'C' derived using 'NOT' gate. The 'C' and 'C-' are randomly chosen, and the triangular carrier waves with fixed frequency "C-" with an opposite phase of "C" are given by the selected signal (P) of the multiplexer. The multiplexer is a combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control signal. The MUX obtains the selected signal through the pseudorandom binary sequence shift register. The PRBS shift register is normally an 8/16 bit register, including the Exclusive OR (XOR) gate. Based on the values of the particular bit, the PRBS gives random binary logic.
In Figure 3, the '2 × 1' multiplexer selects 'C', where 'P' is '1'. Similarly, when 'P' is '1', then 'C-' is selected. The reported pseudorandom frequency used two triangular waveforms with the same frequency to synthesize the proposed random carrier. Therefore, the randomness is limited. Hence, the proposed random carrier technique uses the multiple randomness by using different frequency carriers. Here, the 'C-' is the opposite phase of 'C' derived using 'NOT' gate. The 'C' and 'C-' are randomly chosen, and the triangular carrier waves with fixed frequency "C-" with an opposite phase of "C" are given by the selected signal (P) of the multiplexer. The multiplexer is a combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control signal. The MUX obtains the selected signal through the pseudorandom binary sequence shift register. The PRBS shift register is normally an 8/16 bit register, including the Exclusive OR (XOR) gate. Based on the values of the particular bit, the PRBS gives random binary logic.
In Figure 3, the '2 × 1' multiplexer selects 'C', where 'P' is '1'. Similarly, when 'P' is '1', then 'C-' is selected. The reported pseudorandom frequency used two triangular waveforms with the same frequency to synthesize the proposed random carrier. Therefore, the randomness is limited. Hence, the proposed random carrier technique uses the multiple randomness by using different frequency carriers.

Proposed Multicarrier Random Space Vector PWM
The RCPWM practice is basically related to conventional SPWM, the only variance being the usage of two different triangular carriers, which are the prerequisite frequency and 180-degree phase shifting on the carrier. RPWM targets the way of overwhelming the voltage and a current harmonic, which reduces the current ripple and torque ripple. For improving the inverter DC-link consumption performance, the RPWM is connected with SVPWM, which improves the SVPWM and RPWM quality on the VSI-connected drive. The proposed PWM generates the multiple carriers with a random pattern, and it is applied to SVD to generate the switching timings. The offered multicarrier random space vector PWM structure is presented in Figure 4.
The four carrier signals with different frequencies of 1 kHz, 2 kHz, 3 kHz, and 4 kHz (random values) are made to generate the randomness carrier. In order to merge these random carrier signals, four 3 × 1 multiplexers (MUX) are used, and finally, the MUX output is given to the 4 × 1 multiplexer. The 8-bit PRBS as well as 16-bit PRBS generator are used to generate random '0' and '1' sequence, which manipulate the random combination of four different carrier frequency signals. The randomness is present in the output in the sense that one element value in a sequence is not dependent on any other element sequence. Each carrier signal is selected through MUX and random binary sequence.

Proposed Multicarrier Random Space Vector PWM
The RCPWM practice is basically related to conventional SPWM, the only variance being the usage of two different triangular carriers, which are the prerequisite frequency and 180-degree phase shifting on the carrier. RPWM targets the way of overwhelming the voltage and a current harmonic, which reduces the current ripple and torque ripple. For improving the inverter DC-link consumption performance, the RPWM is connected with SVPWM, which improves the SVPWM and RPWM quality on the VSI-connected drive. The proposed PWM generates the multiple carriers with a random pattern, and it is applied to SVD to generate the switching timings. The offered multicarrier random space vector PWM structure is presented in Figure 4.
The four carrier signals with different frequencies of 1 kHz, 2 kHz, 3 kHz, and 4 kHz (random values) are made to generate the randomness carrier. In order to merge these random carrier signals, four 3 × 1 multiplexers (MUX) are used, and finally, the MUX output is given to the 4 × 1 multiplexer. The 8-bit PRBS as well as 16-bit PRBS generator are used to generate random '0' and '1' sequence, which manipulate the random combination of four different carrier frequency signals. The randomness is present in the output in the sense that one element value in a sequence is not dependent on any other element sequence. Each carrier signal is selected through MUX and random binary sequence.  The random sequence for 16-bit PRBS and 8-bit PRBS is developed through the pseudo method. Unlike conventional random sequences, the pseudo generator continues the random signal, and N elements later, the random signal repeats automatically and gives another set of random binary sequences in contrast to real random sequences, e.g., radioactive decay and white noise. It is executed using the linear feedback type of shift registers for getting the same probability order of '1's and '0' s. The PRBS bit generator is a lead-lag random bit trainer, which is designed by using shift register and XOR gates. A more common form of LFSR is designed using a simple shift register getting feedback from two or more points or tapings available in the chain of registers.
The PRPS working in the below example is from the output of the first (bit 0) and third D-flip-flop (bit 2) of the 3-bit shift register. All the third D-flip-flops of the 3-bit shift register are triggered by the same clock signal. The input for LFSR is produced by XOR using bit 0 and bit 2 from the shift register. The rest of the D-flip-flop outputs are used only for the data-shifting function. The pattern or the sequence of bits produced is the result of the combined action of output produced by XOR and the choice of inputs of XOR.
This creates an n-bit shift register with a constant clock of frequency fc generated with the help of a random carrier wave. The input for first D-flip flop is produced by the output of the XOR gate and is shifted in series to adjacent D-flip flops. The output of the XOR gate depends on the bits tapped from the D-flip flops and XOR operation. Random pulses are generated every fc clock signal. The possible number of outputs is determined by K = 2n − 1.
The PRBS with a random variable needed to choose the PP is attained from the XOR gate output. The random selection of triangular carrier wave having discrete frequency is generated from a pseudo-random carrier method. The logic behind 8-bit and 16-bit PRBS is shown in Figure 4. The output available from PRBS bits of the random bits generator is found as follows in Equations (1) and (2) OPRBS−16bit = B16⊕B14⊕B13⊕B11 (1) The random sequence for 16-bit PRBS and 8-bit PRBS is developed through the pseudo method. Unlike conventional random sequences, the pseudo generator continues the random signal, and N elements later, the random signal repeats automatically and gives another set of random binary sequences in contrast to real random sequences, e.g., radioactive decay and white noise. It is executed using the linear feedback type of shift registers for getting the same probability order of '1' s and '0' s. The PRBS bit generator is a lead-lag random bit trainer, which is designed by using shift register and XOR gates. A more common form of LFSR is designed using a simple shift register getting feedback from two or more points or tapings available in the chain of registers.
The PRPS working in the below example is from the output of the first (bit 0) and third D-flip-flop (bit 2) of the 3-bit shift register. All the third D-flip-flops of the 3-bit shift register are triggered by the same clock signal. The input for LFSR is produced by XOR using bit 0 and bit 2 from the shift register. The rest of the D-flip-flop outputs are used only for the data-shifting function. The pattern or the sequence of bits produced is the result of the combined action of output produced by XOR and the choice of inputs of XOR.
This creates an n-bit shift register with a constant clock of frequency fc generated with the help of a random carrier wave. The input for first D-flip flop is produced by the output of the XOR gate and is shifted in series to adjacent D-flip flops. The output of the XOR gate depends on the bits tapped from the D-flip flops and XOR operation. Random pulses are generated every fc clock signal. The possible number of outputs is determined by K = 2n − 1.
The PRBS with a random variable needed to choose the PP is attained from the XOR gate output. The random selection of triangular carrier wave having discrete frequency is generated from a pseudo-random carrier method. The logic behind 8-bit and 16-bit PRBS is shown in Figure 4. The output available from PRBS bits of the random bits generator is found as follows in Equations (1) and (2) O PRBS−16bit = B 16 ⊕B 14 ⊕B 13 ⊕B 11 (1) where Bx represents the xth output bit of the n-bit shift register and ⊕ represents the XOR operator. When the output of the 8-bit PRBS generator becomes zero as well as the output of 16-bit PRBS generator becomes zero, the carrier having 2 kHz frequency is chosen. When there is zero output of the 16-bit PRBS generator and unity output of the 8-bit PRBS generator, a 3 kHz frequency carrier wave is chosen. When output of the 16-bit PRBS generator becomes one and that of the 8-bit PRBS generator becomes zero, a 4 kHz frequency carrier wave is chosen. When the output of the 16-bit PRBS generator becomes one and the output of the 8-bit PRBS generator becomes one, the carrier is determined to synthesize a random carrier wave. The random carrier wave generated is required for producing trigger gate pulses in VSI. The modulating signal is represented by three-phase reference signals. The proposed MCBRCPWM scheme waveforms are shown in Figure 4. The randomness of the PWM signals is s result of both the different randomization of carrier frequency and the bits from PRBS. This feature makes for an incessant distribution of the power spectra when compared with just the random frequency carrier scheme or the conventional scheme.
After creating a random signal, the multi-frequency random carrier signal is given to the SVPWM block. Here, the proposed SVPWM is alerted for adapting a random signal. The motor quantities (voltages and currents) can be given to the SVPWM reference generator, and these references are calculating the magnitude and phase angle of the SVD. In the SVPWM technique, the process of generating the pulse width command is reduced to a few simple equations. The basic idea behind SVPWM is the compensation of the required volt seconds by the use of discrete switching states and corresponding on-times (ta and tb) for switching. Figure 5 represents the 2-level inverter space vector diagram (SVD) and respective switching pulse [24]. Every sector of the SVD remains an equilateral triangle with height; h (=3/2) is the height of a sector. The voltage vectors can be classified into two types: large vector (LV) and zero vector (ZV The switching instants of SVPWM for six switch VSIs and switching cycles for sector-1 are shown in Figure 5. The on-time calculation for any of the six sectors (∆ i ) (where i = 1, 2, 3, 4, 5 and 6) is the same, and hence, the function of sector 1 is considered for understanding the complete SVD. V*, the reference voltage, represents the rotating SVD form of three-phase voltage.   The - plane projection of V* during any period lies in any one of the sector areas. For instance, Figure 5 shows that V* lies in the first sector edged by vector V1 and V2. From time t0, V* travels to t1 and the relationship with the time integral is given as From the above two Equations (5) and (6), the time durations Ta and Tb can be estimated.
where TS (=1/fS) is the sampling period. Thus, the Ta equation is redefined as (2) Therefore, the time spent by the zero-vector state is where T0 is turned to the zero state (off time of the switching).
The developed SVPWM is in agreement with the multicarrier (different fixed frequencies as carrier waves) and is chosen with the aid of a random binary bit generator. This contribution mainly deals with the combination of the multicarrier RPWM principle with space vector PWM (SVPWM) to generate multicarrier random space vector PWM (MCRSVPWM). The SVPWM is in agreement with multicarrier (different fixed frequencies as carrier waves) signals, which are chosen with the aid of a random binary bit generator. The proposed method generates pulses with a randomized triangular carrier (1 The α-β plane projection of V* during any period lies in any one of the sector areas.
For instance, Figure 5 shows that V* lies in the first sector edged by vector V 1 and V 2 . From time t 0 , V* travels to t 1 and the relationship with the time integral is given as From the above two Equations (5) and (6), the time durations T a and T b can be estimated.
where T S (=1/f S ) is the sampling period. Thus, the T a equation is redefined as Therefore, the time spent by the zero-vector state is where T 0 is turned to the zero state (off time of the switching). The developed SVPWM is in agreement with the multicarrier (different fixed frequencies as carrier waves) and is chosen with the aid of a random binary bit generator. This contribution mainly deals with the combination of the multicarrier RPWM principle with space vector PWM (SVPWM) to generate multicarrier random space vector PWM (MCRSVPWM). The SVPWM is in agreement with multicarrier (different fixed frequencies as carrier waves) signals, which are chosen with the aid of a random binary bit generator. The proposed method generates pulses with a randomized triangular carrier (1 kHz, 2 kHz, 3 kHz, and 4 kHz), while the conventional RPWM method contains the random pulse position with a fixed frequency triangular carrier.

Simulation
The simulation study is done through the MATLAB/Simulink software tool (2016.b) for a three-phase VSI-connected 2 kW asynchronous induction motor. The simulation model of the proposed MCRSVPWM is shown in Figure 6. In this simulation, the major structure is with three main blocks: (1) reference signal generation, (2) random carrier generation, and (3) SVPWM pulse generation. After deciding the modulation index via a reference signal, the random carrier generation block will give the carrier signal to the SVPWM sampling and a holding block to compare the inverter pulses.
Electronics 2021, 10, x FOR PEER REVIEW 9 of 20 kHz, 2 kHz, 3 kHz, and 4 kHz), while the conventional RPWM method contains the random pulse position with a fixed frequency triangular carrier.

Simulation
The simulation study is done through the MATLAB/Simulink software tool (2016.b) for a three-phase VSI-connected 2 kW asynchronous induction motor. The simulation model of the proposed MCRSVPWM is shown in Figure 6. In this simulation, the major structure is with three main blocks: (1) reference signal generation, (2) random carrier generation, and (3) SVPWM pulse generation. After deciding the modulation index via a reference signal, the random carrier generation block will give the carrier signal to the SVPWM sampling and a holding block to compare the inverter pulses. The inverter is investigated with different RPPWM including the proposed MCRSVPWM. Initially, the VSI-connected conventional RPWM and RRPWM results are captured and compared with the proposed MCRSVPWM schemes. The switching frequencies of RCPWM are 1 kHz to 4 kHz; throughout the simulation, the DC-link voltage has been maintained as 400 V, and the inverter is operated in the range of the modulation index from 0.1 Ma. to 0.9 Ma. When the multiple frequencies are fixed at the signal generator as 1 kHz, 2 kHz, 3 kHz, and 4 kHz, the analysis is taken. Around this frequency, the proposed RPWM eliminates the noise of the selective frequency, which is less than 20 kHz.  Figure 7b-d shows the voltage and its corresponding harmonics spectra with Ma = 0.7 and Ma = 0.9, respectively. Based on the results, it can be seen that the fundamental voltage is achieved linearly by changing the modulation index, and the harmonics spectra (%VTHD) is validated as 47.6% and 51.5%, which is smaller than all the other reported RPWM values. Correspondingly, when the inverter is operating at lower modulation, it is in the Ma (low speed) operating region, due to the pulse dropping the VTHD, and ITHD is increasing. Table 2 shows all the corresponding results for different operating The inverter is investigated with different RPPWM including the proposed MCRSVPWM. Initially, the VSI-connected conventional RPWM and RRPWM results are captured and compared with the proposed MCRSVPWM schemes. The switching frequencies of RCPWM are 1 kHz to 4 kHz; throughout the simulation, the DC-link voltage has been maintained as 400 V, and the inverter is operated in the range of the modulation index from 0.1 M a . to 0.9 M a . When the multiple frequencies are fixed at the signal generator as 1 kHz, 2 kHz, 3 kHz, and 4 kHz, the analysis is taken. Around this frequency, the proposed RPWM eliminates the noise of the selective frequency, which is less than 20 kHz. Figure 7a-c shows the measured inverter line voltage under modulation index M a = 0.7 and M a = 0.7. During the condition, the inverter delivers the maximum permissible DC-link utilization. Figure 7b-d shows the voltage and its corresponding harmonics spectra with M a = 0.7 and M a = 0.9, respectively. Based on the results, it can be seen that the fundamental voltage is achieved linearly by changing the modulation index, and the harmonics spectra (%V THD ) is validated as 47.6% and 51.5%, which is smaller than all the other reported RPWM values. Correspondingly, when the inverter is operating at lower modulation, it is in the M a (low speed) operating region, due to the pulse dropping the V THD , and I THD is increasing. Table 2 shows all the corresponding results for different operating regions. From the results, it can be understood that the inverter not only reduces the THD but also maintains the DC-link utilization. regions. From the results, it can be understood that the inverter not only reduces the THD but also maintains the DC-link utilization.  Similar to the HSF of voltage, the current spectra must be calculated for any random PWM schemes for evaluating their noise calculation. This is a simple statistical deviation derived in [21,22].

HSF=
H H 2 Ho= H Here, Hj = amplitude of jth harmonics and ho = the average value of all order harmonics.
When HSF stays near zero, the white noise is zero. However, the zero HSF is partially not possible. On the other hand, the HSF is too small to allow a better harmonics spread. Similar to the HSF of voltage, the current spectra must be calculated for any random PWM schemes for evaluating their noise calculation. This is a simple statistical deviation derived in [21,22].
Here, H j = amplitude of jth harmonics and h o = the average value of all order harmonics. When HSF stays near zero, the white noise is zero. However, the zero HSF is partially not possible. On the other hand, the HSF is too small to allow a better harmonics spread. Hence, the proposed PWM coins the lesser HSF through a simple algorithm. The simulated values of different PWM methods including the proposed MCRSVPWM are compared through Table 3. The tables are focusing on the fundamental voltage and current, voltage THD, and HSF. The proposed MCRSVPWM shows its victory by means of the working range when compared with the other five cases. When M a = 0.8, about a 42% reduction of HSF is achieved from RPWM and SPWM, 36% reduction is achieved from chaotic PWM, 14% reduction is achieved from RPPPWM, and 21% reduction is achieved from RCPWM. The values of V 1 and THD are not highly disturbed for the five cases, except for the nondeterministic RPWM, where about 48% of reduction in V 1 is observed. The simulations (see Figure 8a-d) were made for the four speed values of the motor, which is achieved by setting the different values of modulation indices (for M a = 0.2, M a = 0.5, M a = 0.7, and M a = 0.9). During the low-speed range, similar to RSWM, the proposed RSVPWM shows good performance by means of the disappearance of discrete frequency components from the spectrum around the switching frequency; nevertheless, the discrete components exist. In medium speed to high speed, the proposed SVPWM has a better performance than all the other reported PWM.   Table 4 shows the simulation study results for the line voltage and line voltage THD for the SPWM, RPWM, CPWM, RCRPWM, and MRCRPWM, including the proposed MCRSVPWM method. Here, it can be seen that the proposed MCRSVPWM has a better line voltage and THD compared to the other methods.  The proposed PWM completely removes the discrete components, and the discrete components of the current spectrum are located around the switching frequency, which can be easily limited by a simple filter. Table 3 shows the comparison of HSF for all the reported RPWM with proposed MCRSVPWM. From the table, it is clearly seen that the MCRSVPWM has less HSF throughout the inverter operation. The reason behind this is that most of the dominant frequency component is considerably reduced by spreading the carrier frequency; hence, the non-fundamental power is spread out in an ample wider frequency, which helps reduce the acoustic noise. Table 4 shows the simulation study results for the line voltage and line voltage THD for the SPWM, RPWM, CPWM, RCRPWM, and MRCRPWM, including the proposed MCRSVPWM method. Here, it can be seen that the proposed MCRSVPWM has a better line voltage and THD compared to the other methods. The inverter switches need to be rated to withstand the peak magnitude of the input DC-link voltage and the maximum expected output voltage, and they should be able to safely dissipate the heat generated in the switch due to conduction and switching losses. As a result of high-frequency switching, the switches in the PWM inverters have significantly more switching loss than in square wave inverters. Often, the switch chosen in the PWM inverters is oversized, in terms of its current rating, so that the sum total of switching loss and conduction loss remains well within the heat dissipation capability of the switch and the associated net output voltage. Hence, based on the PWM pulse arrangement, the output voltage of the inverter is varied.
In this study, the proposed MCRSVPWM used SVPWM, where the maximum DC-link voltage is achieved. Other PWM methods used for the comparisons except for regular SVPWM (without RPWM) are similar to that of sine PWM arrangement. Hence, for the given modulation index, the inverter line voltage is higher in the proposed MCRSVPWM and MRCRPWM. The variation in the voltage is verified and the comparison table is revised.
The random carrier pulse width modulation (RCPWM) practice is basically related to conventional SPWM with the variation in their carrier frequencies. In this method, two prerequisite frequency triangular carriers with 180-degree phase shifting are used to create the randomness on the resultant carrier. Hence, the noise of the inverter output is reduced. However, any random carriers affect the inverter DC-link utilization. Compared to sine PWM, space vector PWM has a superior quality to provide an operating region to 90.07% (maximum modulation index, m a = 0.907). Hence, the RCPWM is merged with space vector PWM, which helps spread the noise harmonics around the inverter switching spectra with better DC utilization. In addition, with RPWM and space vector PWM, the proposed random carrier pulse width modulation (RCPWM) is used with multi-carrier (different fixed frequencies as carrier waves) and is chosen with the aid of a random binary bit generator. The proposed method generates pulses with a randomized triangular carrier (1 kHz, 2 kHz, 3 kHz, and 4 kHz), while the conventional RPWM method contains the random pulse position with a fixed frequency triangular carrier. Table 5 shows the DC-link utilization (as a line voltage), the percentage voltage of THD, and HSF. From the table, it is well understood that during the entire inverter operating condition, the proposed MCRSVPWM maintains the voltage THD better than the other reported PWM schemes from the literature as well as maintains the DC-link utilization of the inverter with better HSF.

Experimental Validation
An experimental setup is built in order to validate the simulation results of the proposed induction motor (IM) drive. The experimental setup and design flow of the FPGA implementation design flow for MCRSVPWM is shown in Figures 9 and 10, respectively.  Experimental validation of the proposed RPWM is tested with the VSI-fed induction motor. The experimental setup of the three-phase VSI connected induction motor drive is Experimental validation of the proposed RPWM is tested with the VSI-fed induction motor. The experimental setup of the three-phase VSI connected induction motor drive is show in Figure 9. A 2 kW six switch (Power MOSFET-SCH2080KE) inverter power module is used as a VSI and the 3HP, three-phase induction motor is used for the experimentation. The inverter used a 3400 microF DC-link capacitor to main the DC bus voltage as 400 V. The random carrier (1 to 4 kHz) and SVPWM is developed using the Xilinx-MATLAB system generator tool, and the bit file is generated and downloaded in a Spartan-6 FPGA controller. The multicarrier signals are generated using ramp logic code using VHDL and stored using a FPGA look-up table (LTU) [40]. The different carrier frequencies are mixed through a PRPS generating random binary and given to the SVPWM block. The dead time is fixed for an inverter leg as 6 microseconds. The VSI-fed IM drive is tested for different frequency combinations for changing the sequences of the mixer of carrier frequencies. The SVPWM block is designed to support the variation of the inverter modulation index M a between 0 and 0.9. Figure 11 shows the inverter excremental results of switching the pulses of the MCRSVPWM-fed VSI for M a = 0.9.
Initially, the inverter is tested for the frequencies without floating combinations as f c1 = 1 kHz, f c2 = 2 kHz, f c3 = 3 kHz, and f c4 = 4 kHz. Figures 12 and 13 show the inverter operating line voltage and voltage harmonics performance at M a = 0.6 and 0.9. It is illustrating the line-to-line voltage of V AB and its percentage V THD of M a = 0.6 and M a = 0.9. When the inverter drive is operating at medium speed (M a = 0.6), the VA B and its THD are observed as 173 V and 51.6%, respectively. Similarly, when the inverter is operating at a higher modulation index, M a = 0.9 operating region, the line-to-line voltage, V AB is increasing linearity to 262.5 V, and its percentage V THD is recovered as 51.7%. From these results, it can be understood that during the entire inverter operating condition proposed, MCRSVPWM maintains the voltage THD better than the other reported RPWM schemes and also maintains the DC-link utilization of the inverter.
trating the line-to-line voltage of VAB and its percentage VTHD of Ma = 0.6 and Ma = 0. 9. When the inverter drive is operating at medium speed (Ma = 0.6), the VAB and its THD are observed as 173 V and 51.6%, respectively. Similarly, when the inverter is operating at a higher modulation index, Ma = 0.9 operating region, the line-to-line voltage, VAB is increasing linearity to 262.5 V, and its percentage VTHD is recovered as 51.7%. From these results, it can be understood that during the entire inverter operating condition proposed, MCRSVPWM maintains the voltage THD better than the other reported RPWM schemes and also maintains the DC-link utilization of the inverter.  The different hardware results with respect to different modulation conditions are reordered and given in Table 6. The hardware results confirm the simulation results. The MCRSVPWM confirms the superiority of their reduction of noise (HFS %) and better DC- The different hardware results with respect to different modulation conditions are reordered and given in Table 6. The hardware results confirm the simulation results. The MCRSVPWM confirms the superiority of their reduction of noise (HFS %) and better DC- The different hardware results with respect to different modulation conditions are reordered and given in Table 6. The hardware results confirm the simulation results. The MCRSVPWM confirms the superiority of their reduction of noise (HFS %) and better DC-link utilizations. Comparisons of simulation and experimental results are given in Figure 14. Figure 14a shows the line voltage versus the modulation index, and Figure 14b shows the reduction of noise (HFS %) versus the modulation index. Figure 14a shows that the simulation line voltage is slightly higher than the experimental line voltage. This is due to the switching and conduction losses in real-time experimentations factors. The noise HFS% is slightly higher in the experimental results against all modulation indices. This is due to the higher harmonics that appeared in the experimentation. Comparisons of simulation and experimental results are given in Figure 14. Figure  14a shows the line voltage versus the modulation index, and Figure 14b shows the reduction of noise (HFS %) versus the modulation index. Figure 14a shows that the simulation line voltage is slightly higher than the experimental line voltage. This is due to the switching and conduction losses in real-time experimentations factors. The noise HFS% is slightly higher in the experimental results against all modulation indices. This is due to the higher harmonics that appeared in the experimentation. The proposed MCRSVPWM can be used in various applications such as drives and power system power quality improvement. The proposed random PWM is able to reduce the acoustic noise and electromagnetic interference in VSI-fed motor drives. It also can be extended for CSI drives such as current controlled and Direct Torque Control (DTC) AC drives. The time for zero voltage is randomized to get better results with Direct Torque Control (DTC) for drives. The proposed MCRSVPWM can help flatten the power density spectrum of the drive, reduce switching loss, decrease current ripple, and auto-adjust load characteristics. The proposed RPWM can be used to reduce the particular acoustic noise and electromagnetic noise. Hence, it can be used for dynamic load characteristics applications such as electrical vehicles' drives and automobiles' AC motor drives (induction motor and PMSM motor drives). In shunt active power filter is used to improve power quality issues such as current harmonics and power factor for a power system with nonlinear load. With random PWM, the APF response can be improved without adding any cost. The proposed MCRSVPWM can be used in various applications such as drives and power system power quality improvement. The proposed random PWM is able to reduce the acoustic noise and electromagnetic interference in VSI-fed motor drives. It also can be extended for CSI drives such as current controlled and Direct Torque Control (DTC) AC drives. The time for zero voltage is randomized to get better results with Direct Torque Control (DTC) for drives. The proposed MCRSVPWM can help flatten the power density spectrum of the drive, reduce switching loss, decrease current ripple, and auto-adjust load characteristics. The proposed RPWM can be used to reduce the particular acoustic noise and electromagnetic noise. Hence, it can be used for dynamic load characteristics applications such as electrical vehicles' drives and automobiles' AC motor drives (induction motor and PMSM motor drives). In shunt active power filter is used to improve power quality issues such as current harmonics and power factor for a power system with nonlinear load. With random PWM, the APF response can be improved without adding any cost.

Conclusions
In this paper, a multicarrier random space vector PWM was presented for a three-phase two-level six switch voltage source inverter-fed induction motor. The proposed multiple carrier-based random method improves the randomness, which helps spread the harmonics around the spectra. The SVPWM agrees with multicarrier (different fixed frequencies as carrier waves), which are chosen with the aid of a random binary bit generator. The proposed MCRSVPWM generated pulses with a randomized triangular carrier (1 to 4 kHz), while the conventional RPWM method contains the random pulse position with a fixed frequency triangular carrier. The FPGA-based two PRBS bit (8 bit and 16 bit) generators are used to generate the random binary for getting random carriers for the pulse generations. The simulation study is performed through MATLAB/Simulink for a 2.5A asynchronous induction motor drive. The experimental validation of the proposed RSVM is tested with a 2 kW six switch (Power MOSFET-SCH2080KE) inverter power module-fed induction motor drive. The MCRSVPWM is confirming the superiority of their reduction of noise and better DC-link utilizations. The proposed PWM is capable of eradicating the highfrequency unpleasant acoustic noise more effectually than a conventional RPWM with a shorter random frequency range.
The proposed MCRSVPWM can be used in drives and a power system shunt active power filter to improve the power quality. The proposed random PWM is able to reduce the acoustic noise and electromagnetic interference VSI-fed motor drives. The proposed MCRSVPWM can help flatten the power density spectrum of the drive, reduce the switching loss, decrease the current ripple, and auto-adjust load characteristics. The proposed RPWM can be used to reduce the particular acoustic noise and electromagnetic noise. Hence, it can be used for dynamic load characteristics applications such as electrical vehicles drives.