Study on Multiple Input Asymmetric Boost Converters with Simultaneous and Sequential Triggering

: Paralleled boost asymmetric conﬁgurations operating in discontinuous conduction mode (DCM) are suitable for integrating dissimilar green energy generating sources and control algorithms in versatile scenarios where voltage step-up, low cost, stable operation, low output ripple, uncomplicated design, and acceptable efﬁciency are needed. Unfortunately, research has mainly been conducted on the buck, sepic, switched-capacitor, among other asymmetric conﬁgurations operating in continuous conduction mode (CCM), to the authors’ knowledge. For asymmetric boost type topologies, achieving simultaneous CCM is not a trivial task, and other problems such as circulating currents arise. Research for interleaved converters cannot be easily extended to asymmetric boost topologies due to the dissimilarity of control algorithms and types of sources and parallel stages. This paper analytically establishes properties of stability, output ripple, output voltage, and design for asymmetrical paralleled boost converters operating in DCM with simultaneous or phase delayed (sequential) triggering. A 300 W experimental design and the respective tests allow validation of such properties, resulting in an easy-to-implement conﬁguration with acceptable efﬁciency.


Introduction
Wind generators, photovoltaic modules (PVM), fuel cells (FC), storage systems (batteries), and many other energy sources should be integrated into green power distributed generation plants (hybrid sources) [1][2][3][4] and modern smart grids [5][6][7][8]. If any energy sources cannot provide energy, the rest could satisfy the customers' energy demand as a multiple uninterrupted power supply.
Smart grids require higher voltage levels (enough to convert to 120/220 VAC) than those provided by energy sources such as PVM or FC. For example, outstanding research was aimed to obtain very high gain and efficiency levels for a single source by combining switched-capacitor and sepic stages [9] or new interleaved boost configurations [10]. Several investigations on interleaved-type converters proposed models and control schemes based on phase-shifted triggering for multiple stages and a single source; these would allow for a power increase, decrease input and output distortions (ripple), and even mitigate nonlinear bifurcation phenomena [11][12][13][14][15][16][17][18].
However, the integration of several different energy sources by power electronic converters (PEC) is necessary but presents complications (recirculating currents, harmonics, Some interesting adverse effects of uncontrolled and arbitrary phase-delay triggering in paralleled stages with a final diode (as the case of boost topologies), were numerically shown in [45]; however, the benefit of a sequential triggering over the input/output current ripple reduction is well known [46,47]. Regardless of the above, no analytical research has been conducted on the benefits of a sequential triggering (with phase delay instead simultaneous) for paralleled boost converters operating in DCM for n stages and controllers, to the authors' knowledge. Neither was any study found on the combination of MPPT algorithms for some sources, with other control strategies for different sources, for boost paralleled converters.
Hence, from the review above, the found research cannot be easily extended or modified to the design of multiple-input converters, with n asymmetric boost stages, operating in DCM and sequential or simultaneous triggering. This paper presents the following contributions: • An output voltage stability analysis for an n paralleled boost stages converter operation with MPPT control combined with other controllers. • Formulations for the steady-state voltage gain and the output voltage ripple. • An approach to design an easy-to-implement, versatile, and stable boost-type paralleled MIC with n unequal stages and sources and independent controllers (MPPT/other). This strategy allows different energy sources to feed a resistive load and decouple the paralleled boost stages without extra components, avoiding circulating currents with a low-cost implementation. The output voltage and current ripples are diminished in comparison with simultaneous triggering schemes; an experimental exemplification of the MIC design is provided.
With these objectives in mind, this document is organized as follows. Section 2 presents the MIC setup and dynamic modeling from a switched-systems perspective. The analysis ensures stability regardless of whether multiple MPPT controllers are combined with other strategies. In Section 3, the steady-state analysis to determine the averaged and ripple output voltage levels for sequential triggering are presented, and the ripple concerning simultaneous triggering is compared. Section 4 is aimed at the design of the MIC and the experimental platform. Sections 5 and 6 present numerical and experimental validations of the models and, finally, Section 7 is dedicated to providing some discussion, conclusions, and future work.

Paralleled-Boost-Converter, Dynamic Modeling, and Stability
Let us begin by recalling the boost converter large-signal analysis, which is regularly used in the literature [20,48,49]. This analysis can be extended to n asymmetric boost stages connected in parallel to study the MIC configuration shown in Figure 1a. For sequential or phase-delayed triggering, the activations of MOSFETs/switches are ordered and evenly distributed within every operation period T s , of a pulse width modulator (PWM). To be precise, sequential triggering means that the Q i -th MOSFET is deactivated (off-state) T s /n seconds after the Q i−1 switch was deactivated, and the first MOSFET is deactivated T s /n seconds after the n-th MOSFET (n is the number of stages); activation-timing must be calculated on this time base (see Figure 1b) with u i,1 ≤ 1/n where u i,1 is the dutycycle of the i-th stage. Only a single switch is activated at a time, and the next switch is activated when the previous has been deactivated; this allows simultaneous energy charge of inductors to be avoided. On the other hand, while the first switch is deactivated, the stored energy flows towards the load until it is discharged. Within this period, two scenarios are possible: another single switch can be activated to charge the next inductor, or all switches remain deactivated until another switch should be activated. In other words, for the sequential triggering proposed in this paper, the simultaneous charge of two or more inductors is not allowed, nor is the simultaneous discharge of two or more inductors allowed; this is because additional harmonics are introduced (currents through the diodes are summed within T S /n, and the ripple stops having a triangular shape). (1/n) while for PW M 2 is lesser; hence, every PWM can operate independently. Only a single inductor discharge is allowed at a time; simultaneously, at most, a single inductor is allowed to charge. Table 1 illustrates the allowed operation modes of the MIC with two stages, including their corresponding dynamic equations; note that the quantity of modes depends on the number of stages, but only subindexes in equations change and can be easily extended to n > 2. The gray lines in the schematics indicate no current flow, while black lines mean a current flow. Figure 2 shows an exemplification of the sequential triggering for the two stages MIC and the obtained mode sequence. Note that such a sequence depends on the duty cycles, but simultaneous charge and discharge of inductors are avoided. Charging periods are alternated. A charge and discharge of inductors can occur simultaneously, depending on the duty cycles; hence, one of the seven dynamic operating modes shown in Table 1 is possible with two stages. The sequential triggering and proper component selection (see Section 4) exclude other modes for dual charge/discharge.
From a switched-systems perspective, considering that the duty cycle for any stage is 0 ≤ D i < 1/n where i = 1, 2, ..., n and differentiating the voltage equations in each mode (one looks only for the output voltage dynamic behavior), one can get the following switched system (arbitrary switching) from Table 1 equations: .., n + 1, and Since the dynamic (qualitative) behavior of each autonomous subsystem is invariant to shifts in the equilibrium point [50], one can propose n coordinate changes y = x − x e where x e is the respective equilibrium point (abusing notation):

RC
, and ρ ∈ {0, 1} is introduced to consider the last (A n+1 ) subsystem (for simplicity in the next algebra).
In the following, a stability test is developed under a common Lyapunov function (CLF) design approach. Hence, stability is ensured despite arbitrary switching [51] regardless of the control actions of n MPPT control systems or of the combination of MPPT control for some stages, and other controllers for the rest.
Consider the common Lyapunov candidate function: where p 2 , p 3 ∈ R must be constants such that P 0 (positive definite); note that V(y) = 0 in y = [0, 0] T . Since one looks for P 0, the leading minors of P must be positive, hence det(P) > 0 (Sylvester's criterion) such that p 3 > p 2 2 is the first condition to meet. The time derivative of V(y) along the system trajectories is: In order to ensure stability despite the arbitrary switching, Q i = PA i + A T i P ≺ 0 (negative definite) for all i, and for all ρ ∈ {0, 1}. Consider the case ρ = 1, the principal minors of Q i are as follows: Q i ≺ 0 if M 1 < 0 hence, p 2 > 0 is a second condition to meet (odd leading minors must be less than zero). Besides, it must also be fulfilled that M 2 > 0: This is to say, the even minor must be greater than zero. Selecting the worst-case values (for the previous inequality) of L m ≤ L i ≤ L M , where L m is the lowest L i value and L M is the highest L i value, p 2 and p 3 values should be selected such that Selecting the second condition is met, and the inequality (8) reduces to Setting Inequality (10) reduces to such that the second condition is congruent. Now, it must be proved that p 3 > p 2 2 , which is the first previously stated condition; substituting p 3 from (11) in such inequality one has: (13) and it is enough to demonstrate that the sole first term is greater than the right side of the previous inequality when p 2 from (9) is used: Consider now the case ρ = 0 and note that ρ → 0 when L i → ∞ ∀i, such that the previous analysis for M 2 holds. On the other hand, it is easy to demonstrate that M 1 → 0 when L i → ∞, hence Q i is negative semi-definite. In other words, the bounding of the solutions or practical stability (or simply 'stability') can be ensured; in fact, since there will always be a ripple in the output voltage due to switching between modes, asymptotic stability cannot be expected, but rather the confinement of the system solutions to a small region of the state space. Such regions, in this case, correspond to the level of the ripple of the output voltage that will be estimated in the next section.

Steady-State Analysis
In the previous section, a dynamic analysis of the MIC was done regardless of the triggering. Next, the output voltage level and the voltage ripple will be obtained by steadystate analysis for the multiple-input, sequential triggering converter (MISeC), and, for completeness purposes, also with simultaneous triggering (MISiC) for comparison purposes.

Averaged Output Voltage for the MISeC
Considering the MISeC with n parallel boost stages and ideal components, each inductor current will increase linearly when the corresponding MOSFET is activated (onstate), as illustrated in Figure 1b. If the MOSFET is turned off, the corresponding inductor current decreases linearly to zero. Note that the corresponding diode prevents a reverse current through such an inductor; hence the current remains zero (DCM) until the next period (T s ) is started, as illustrated in Figure 3a. The sequential triggering can grant an energy flow toward the load with independent control for each stage, ensuring that the average current < i D,out > can be calculated as follows: where i D i is the corresponding current through the diode for each stage.
To calculate i D i , the graphic depicted in Figure 3b shows the behavior of the current through the diode within a T s period, and whose value can be calculated using the triangle area formulation: Substituting (18) in (17) one has: where u i,2 is the i-th inductor discharge period, and I pk i represents the respective inductor peak current (see Figure 3). I pk i can be calculated as [52]: Substituting (20) in (19), the average current of all of the diodes can be approximated by: The discharge period u i,2 can be calculated by the relationship between the legs and the hypotenuse derived from the current's triangular shape through the diode, as shown in Figure 3b. This means that the tangent angle is a function of u i,2 , and I pk i , and its value can be expressed as follows: Solving for u i,2 one has: Note that in the previous equations, the notation for V o is being abused because it was also used in the switched model, and it should not cause confusion since it now represents the same voltage but is seen in an averaged way.
Substituting u i,2 from the preceding expression into Equation (21) and considering that the maximum current through the diodes is i D,out,max = V o R , the average output voltage can be expressed as follows: where Equation (24) is a polynomial function where the roots are V o values. One can infer that the real V o value must be the maximum, real and positive one. In later sections, this assumption is validated.

Output Voltage Ripple for the MISeC
The voltage ripple (∆ V ripple ) is defined as the difference between the maximum and minimum of the steady-state output voltage, as illustrated in Figure 3c; in this paper, this difference is expressed as a function of the capacitor current as depicted in Figure 3d: where Q is the capacitor charge. The differential of charge for each stage (dQ i ) can be approximated using the capacitor charge period u i,2 , and the triangle area formulation (see Figure 3d): where h i = I pk i − i o is the triangle height, i o the output current, and b i the base width.
Using similarity theorems, one has: To determine the value of b i as a u i,1 function, one can substitute (23) in (27), thus: Substituting the value of u i,2 in Equation (23), and substituting Equation (27) in (26): Replacing (29) in (25) and solving for the i-th dV ripple : Using L i from Equation (20), Equation (30) can be expressed as: Since one looks only for the maximum ripple: Usually, keeping a lower percentage of voltage ripple is desirable in converter applications. If the output voltage ripple is greater than that supported by the load, it could be damaged. In the following, the output ripple for the MISiC is calculated; an analytic comparative is performed to show the sequential benefits concerning simultaneous triggering.

Average Output Voltage for the MISiC
In this scenario, the average current through all of the diodes can be approximated as in Equation (21). Since < I D out > = V o /R, the average output voltage can be estimated as: It is important to recall that in this scenario, all of the switches are activated within the same period; this formulation is not precise for the MISeC.

Output Voltage Ripple for the MISiC
In this scenario, the total peak current I pk due to simultaneous triggering can be calculated as: I pk = I pk1 + I pk2 + I pk3 + ... + I pkn .
Considering that the charge interval ui, 1 ends within the same period, the capacitor current can be calculated as in Equation (25). Two scenarios to calculate the area for dQ i are possible. All input/source voltages are the same in the former, and in the latter, all input voltages are different. For the former, substituting Equation (34) in (25) and solving for ∆V ripple,i , one has: Note that again, one looks only for the maximum ripple. For the latter case (different input voltages), and using Figure 4, dQ can be approximated as: whereū 2 is the average of the discharge periods. Substituting Equation (36) in (25): Sinceū 2 can be expressed in terms of u i,1 , (37) can be rewritten as:

Analytic Ripple Comparison for Sequential and Simultaneous Triggering
From Equations (20), (32), and (35), it is easy to see that the ripple for the simultaneous triggering with the same voltage inputs is greater than the sequential case because I pk = I pk1 + I pk2 + I pk3 + ... + I pkn > I pki (39) for the same duty cycles, except for the trivial case in which all peak currents are zero.
To show that the ripple with simultaneous triggering and unequal voltage inputs is greater than that with sequential triggering, it is enough to compare Equations (20), (32) and (38): Since the input voltages e i are different: Using γ = (I pk i − i o )/I pk i < 1: Hence, |I pk i | < |I pk1 + I pk2 + ... + I pkn | (44) and all of the (rest of the) triangle inequality theorem conditions are met, except, again, for trivial cases in which all or almost all, peak currents are zero. Section 5 illustrates numerically and graphically how the ripple is considerably less using sequential triggering.

Component Selection
The configuration of n parallel stages of the proposed MISeC allows individual component sizing, with the only condition of maintaining the DCM. Considering that the MISeC enables the use of different types of DC sources, a scenario is illustrated and experimented with three 100 W maximum power sources without loss of generality. These sources are two 100 W maximum-power PVM (at 1000 W/m 2 irradiation) and a battery with the capacity to give a constant 100 Wh rate (emulated by a power supply).
For such design, the maximum duty cycle for each stage u max , to avoid the superposition of each stage ripple and get a clean (regular) output-voltage signal, is 0 ≤ u < 1/3. Here, the PWM operating frequency f s is established as 10 kHz without loss of generality; this frequency is selected here because it is easy to achieve with cheap components such as micro-controllers. Hence, for DCM, the critical inductance is defined as [53,54]: Using an R ≥ 10 Ω load, L i < 74 µH, and from Equation (20), a maximum-voltage vs. current trade-off is advertised. Looking for commercial values, Coilcraft inductors of 22 µH and a 35.4 A maximum current are selected because of their availability and low cost. Hence, the peak voltage supported is 23.364 V per stage.
From Figure 5a, the power output and output voltage can be estimated since they depend on the load resistance as stated in the previous sections. The range of power for this design is approximately [300, 600], W and the range of average output voltage is [35,670] V. Here, the load is selected as R = 75 Ω, according to this design. Figure 5b illustrates the output voltage and the voltage ripple as a function of the load resistance for a 25 µF capacitor; hence, this capacitance is selected for the design (this value must be chosen based on the real-application desired ripple level). Table 2 shows the relevant and real (experimentally measured) parameters obtained from commercial parts. Note that relevant parameters for inductors were individually validated to gain precision on the next validations.

Numerical Validation of the Models
To validate the formulations provided, in this section, the results of numerical comparison against PSIM are presented. The previously stated design includes three boost stages, and 22 operation modes are possible. This switched model is integrated into Matlab Simulink, and in both models, the components are considered ideal.
The first validation consists of comparing the output voltage obtained with the proposed model against that provided by PSIM. For this test, e 1 = 17.7 V, e 2 = 17.7 V, and e 3 = 23 (design parameters for maximum irradiation), with 33.3% duty cycles. In Figure 6, the average and ripple outputs are compared. The PSIM model response is plotted in purple for the averaged output voltage and yellow for the ripple. The model response is plotted in red and blue for the averaged output voltage and ripple, respectively. It can be seen that the average voltage is 157.80 V and 155.92 V, with PSIM and the proposed models, respectively; the voltage ripple is 3.4717 V for the PSIM simulation and 3.3977 V for the proposed model. This is a −0.33% numerical precision error in average that can be neglected. Two scenarios for validation for the steady-state formulations are presented. In the former, equal 17.7 V input voltage sources were used, and in the latter e 1 = 12 V, e 2 = 17.3 V, and e 3 = 22 V. In both scenarios, a 33% duty cycle for all stages is used. Other tests with different combinations of input voltage levels and duty cycles were performed, corroborating the model's validity; however, only representative results are presented. Other tests with different combinations of voltage levels and duty cycles were performed, corroborating the validity of the formulations; however, only representative results are presented here. Note that both the provided model and the formulations for the steady-state output voltage provide reasonable approximations.  For completeness purposes, a comparison of the output voltage ripple (for both MISeC and MISiC) as a function of R is presented. This is, the load resistance varies within a [1, 100] Ω range. Such comparison is plotted in Figure 9. The diminution of the ripple with the MISeC is notable for a wide range of loads, as expected from Section 3.5.  Figure 10 shows the complete system for the experimental tests, where each photovoltaic module is connected to each of the inputs and the power supply, emulating a battery. The MISeC uses a Microchip DSPIC33, three inline current sensors (at the bottom of the PCB), and other basic circuitry. The DSPIC performs analog to digital conversion, MPPT, and PWM functions. The PCB was built only for prototype test purposes; hence, some noise is expected. A final production PCB design is not the purpose of this paper and is left for future research.

Controller Design
The following experimental tests are intended to demonstrate that the MISeC allows the independent operation of n MPPT controllers, simultaneously with other power tracking techniques as a constant power rate one-to avoid degradation of fuel cells or batteries, for instance. There are various MPPT algorithms in the literature. Whether by direct methods [55][56][57], or indirect methods [55], it is essential to maintain the maximum power point available. Here, a simple and easy-to-implement technique is used, known as a perturb and observe (P&O) [58,59], illustrated in Figure 11 (for a single MPPT algorithm). This article is not aimed at developing a novel maximum power tracking method. It is important to recall that different MPPT algorithms are calculated individually in the MISeC. Particularly, two independent P&O MPPT algorithms are calculated by the DSPIC33, one for each photovoltaic module stage. The last stage is set to control its output power using a PI controller; this is the case for some fuel cells or batteries in diverse scenarios and is quite different from an MPPT. -1),...,V n (k-1) -1),...,I n (k-1) -1),..., Figure 11. Description of a single MPPT algorithm operation. Figure 12a shows the PVM voltages, the output voltage, and the output current for high (full) irradiation conditions in both PVMs. Figure 12b shows the currents through the inductors. Note that the charging periods are not simultaneous, and the MPPT algorithms can operate independently from the third stage (constant power). Figure 13 shows the triggering signals and the output voltage for the MISeC. Please refer to Table 3 for efficiency, voltage, power, and current levels. The upper signals (blue and red) are for the PVM stages with a 30% duty-cycle. The third signal (green) is for the battery at 33% duty-cycle. Please refer to Table 3 for efficiency, voltage, power and current levels.  Figure 14a shows the output voltage ripple with a 5 V/div scale for the MISeC. The average estimated value is 3.40 V, which represents a −2.39% error with respect to the 3.4834 V calculated with the previously stated formulations. Comparatively, Figure 14b shows the ripple for the MISiC under the same conditions; note that 6.2 V is considerably greater (82%) than for the MISeC. Figure 15 shows the simulations for this previous scenario (the proposed model and PSIM model). It should be mentioned that for this simulation, the values in Table 2 are used, including parasitic resistances. Comparatively, Figure 16 shows the related voltages for the MISiC. Table 4 summarizes the accuracy of the proposed models for this test. The last two columns represent the PSIM model error, and the proposed model error, respectively, both regarding the experimental values. Note that the formulations provide acceptable values.

Experimental Tests
Finally, two additional experimental tests are presented. For the first one, irradiation is manually depleted on the first photovoltaic module (covered with a translucent film). For the second experiment, the two panels are covered. Figure 17a,b show the triggering pulses and output voltages for such scenarios, respectively. In Figures 18a and 19a, the PVM voltages, the output voltage, and the output current, respectively, are shown for each test. The duty cycle is 25% for a covered panel, while the other remains as in the full irradiation scenario. Figures 18b and 19b show the behavior of the currents through the inductors for each test. Please refer to Table 3 for efficiency, voltage, power, and current levels.  Note that the MISeC allows the independent operation of each MPPT while the ripple is small compared to other configurations and triggering strategies. For completeness purposes, Table 3 resumes power and efficiency values for all the experimental tests. Final production PCB and other considerations will provide better efficiency values; it is not the purpose of this paper to improve the efficiency, but, according to experiments, at least 88% can be obtained. Regardless of the above, the efficiency is much better for the MISeC, with less ripple, and n independent MPPT controllers can be integrated.
From the previous tests, a stable operation of the MISeC can be concluded; multiple MPPT algorithms along with other controllers, such as the constant power one, can be used with acceptable efficiency and low ripple.   The two upper signals are the duty cycles for the modules (5 V/div), followed by those for the battery (5 V/div) and the output voltage (100 V/div). The MPPT algorithms can operate independently, even in the presence of the constant rate source. Please refer to Table 3 for efficiency, voltage, power and current levels.  Figure 18. PVM voltages, output voltage, output current, and currents through the inductors for a single photovoltaic module partially shaded of the MISeC. (a) The two upper signals are the modules voltages (20 V/div), followed by the output voltage (50 V/div), and the output current (5 A/div). The MPPT algorithms can operate independently, even in the presence of the constant rate supply. (b) The upper signals are for the photovoltaic panels with 25 and 30% duty cycles, respectively. The third signal is for the battery at 33% duty-cycle. Please refer to Table 3 for efficiency, voltage, power and current levels.
(a) (b) Figure 19. PVM voltages, output voltage, output current, and currents through the inductors for both PVM partially shaded of the MISeC. (a) The two upper signals are the modules voltages (20 V/div), followed by the output voltage (50 V/div), and the output current (5 A/div). The MPPT algorithms can operate independently, even in the presence of the constant rate supply. (b) The upper signals are for the photovoltaic panels with 25% duty cycles. The third signal is for the battery at 33% duty-cycle. Please refer to Table 3 for efficiency, voltage, power and current levels.

Discussion, Conclusions, and Future Work
A dynamic model for the boost-type (paralleled) MIC with any finite number of stages/input sources is developed in this paper. Such a model can be used for different control objectives as voltage or current regulation. It is analytically demonstrated that the dynamic model is output-voltage stable for a resistive load regardless of the switching, and hence, of the conduction mode under regular (appropriate) parametrization. The stability in such a sense does not depend on the used controllers, and the controllers can operate independently as long as they follow compatible objectives.
Steady-state analyzes are performed to estimate the average output voltage and the output voltage ripple, including any finite number of stages/input sources. These analyzes can be extended to obtain the ripple of the currents through the inductors, output current ripple, and other variables of interest. Additional study analytically shows that the ripple is considerably reduced regarding a simultaneous triggering in the same electric configuration. The presented dynamic model, the formulations obtained, the ripple reduction concerning a simultaneous triggering and, the stability under multiple control types (MPPT + constant rate) are validated numerically and experimentally.
The presented configuration allows any finite number of different DC voltage levels to be connected; hence, other energy collectors can be used. PVMs in different locations (irradiation conditions) can be integrated into a single DC bus, avoiding the potential induced degradation (because of their parallel interconnection instead of a series one). Even more, the implementation cost of the MISeC is relatively low.
Future work must consider AC input sources; although rectification could initially solve their integration in the MISeC, new phenomena can be generated, such as power quality issues and resonance effects.