An analysis and modeling of the class-e inverter for zvs/zvds at any duty ratio with high input ripple current

: This paper presents an analysis and modeling of the class-E inverter for ZVS/ZVDS execution at any duty ratio. The methodology is to determine the input current to the inverter analytically under the assumption that it always remains positive. The latter is ensured by proper selection of the input inductance such that the inverter always operates either in (1) the border condition mode or in (2) the continuous conduction mode regardless of the input ripple. Using this input current and applying the boundary conditions, the required input capacitance for the ZVS/ZVDS execution is determined at a speciﬁed input/output voltage, output power and load. The analysis shows that the ZVS/ZVDS can be achieved while the input capacitance is selected appropriately. A comparison between the analytical and simulation results is also formulated involving the proposed and other existing models. The simulation results that are provided at different duty ratios demonstrate that they are in a better agreement with the proposed analytical model regardless of the input inductance and the state of input ripple current. The analytical modeling is facilitated by using MAPLE ® .


Introduction
The class-E inverter has found numerous applications in radio transmission, induction heating, industrial ultrasonic, renewable energy systems or commercial electronics industry [1][2][3][4][5].In that regard, many application-specific designs are also proposed [3][4][5][6][7].The widespread adoption of this inverter is mainly due to the compact topology with low component count and the capability of the circuit to deliver high power.On top of that, it can operate at high switching frequency with high efficiency if coupled with the zero-voltage switching (ZVS) or zero derivative voltage switching (ZVDS) techniques.The analysis and modeling of the ZVS/ZVDS class-E inverters are well reported in the literature [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16].Some of these modeling techniques are described here [1,2,8,11,12].These techniques assume that the resonant current is sinusoidal, and, most importantly, the input current is a pure dc with very low ac component.The latter can be achieved if the input inductance is kept sufficiently large.Consequently, these models can define the behavior of the input current with the change in duty ratio.However, at lower inductances and higher ripple current, the assumption is no longer valid.The input current to the inverter is dependent on the input inductance, the input capacitance along with the duty ratio of the circuit.Consequently, the existing modeling techniques [1][2][3][4][5][6][7][8][9][12][13][14][15][16].fail to define the input current accurately.This inaccuracy further leads to miscalculation of the input/output power and the efficiency of the circuit.Henceforth, this work proposes an input current-based modeling of the class-E inverter.This proposed modeling technique has the following key features: (1) It provides an analysis and modeling of the class-E ZVS/ZVDS inverter for any duty ratio.
(2) More accurate modeling of the input current, regardless of the input inductance and input ripple current.This feature helps to determine the input power and efficiency more accurately.
(3) The model can ensure the ZVS/ZVDS operation at any given load.
In the following sections, this model is discussed, analyzed and compared with the simulated results.The analytical modeling presented is performed using MAPLE ® .

The Circuit Operation of Class-E Inverter
The topology of the class-E inverter is given in Figure 1.The inductance Lr and the capacitance C r is chosen to resonate at f r , which is also the switching frequency of the inverter.The L f can be chosen to provide a constant dc current.However, the input ripple current percentage will increase with the decreasing size of the inductance L f .The input capacitance C in is inclusive of any parasitic drain to source capacitance of the switch and any external capacitance added.The switch S1 is operated with a duty ratio D. The switching pattern is given as follows.

Switch =
Turned ON, 0 ≤ θ < 2πD Turned OFF, 2πD ≤< θ < 2π Electronics 2021, 10, x FOR PEER REVIEW 2 of 23 and higher ripple current, the assumption is no longer valid.The input current to the inverter is dependent on the input inductance, the input capacitance along with the duty ratio of the circuit.Consequently, the existing modeling techniques [1][2][3][4][5][6][7][8][9][12][13][14][15][16].fail to define the input current accurately.This inaccuracy further leads to miscalculation of the input/output power and the efficiency of the circuit.Henceforth, this work proposes an input current-based modeling of the class-E inverter.This proposed modeling technique has the following key features: (1) It provides an analysis and modeling of the class-E ZVS/ZVDS inverter for any duty ratio.
(2) More accurate modeling of the input current, regardless of the input inductance and input ripple current.This feature helps to determine the input power and efficiency more accurately.
(3) The model can ensure the ZVS/ZVDS operation at any given load.
In the following sections, this model is discussed, analyzed and compared with the simulated results.The analytical modeling presented is performed using MAPLE ® .

The Circuit Operation of Class-E Inverter
The topology of the class-E inverter is given in Figure 1.The inductance Lr and the capacitance Cr is chosen to resonate at fr, which is also the switching frequency of the inverter.The Lf can be chosen to provide a constant dc current.However, the input ripple current percentage will increase with the decreasing size of the inductance Lf.The input capacitance Cin is inclusive of any parasitic drain to source capacitance of the switch and any external capacitance added.The switch S1 is operated with a duty ratio D. The switching pattern is given as follows.

Modes of Operation
The circuit is operated in two modes.In mode 1, the switch is turned ON and the voltage across the capacitor Cin falls to zero.The input current flows through the switch S1 and the Lf is charged.In the resonant tank, resonant current flows to the switch direction exchanging stored energy from Cr to Lr and completing half of the resonance cycle.This is shown in Figure 2a.In mode 2 (Figure 2b), the switch S1 is turned off and the input current Iin is diverted to the input capacitance Cin.At this moment, the input capacitor is charged to the peak switch voltage.Subsequently, it is discharged to zero at the end of this mode aiding in ZVS/ZVDS turn on of S1.If we assume the switch voltage is vs (θ), the following conditions must be satisfied in order to achieve ZVS or ZVDS: (2 ) 0

Modes of Operation
The circuit is operated in two modes.In mode 1, the switch is turned ON and the voltage across the capacitor C in falls to zero.The input current flows through the switch S 1 and the L f is charged.In the resonant tank, resonant current flows to the switch direction exchanging stored energy from C r to L r and completing half of the resonance cycle.This is shown in Figure 2a.In mode 2 (Figure 2b), the switch S 1 is turned off and the input current I in is diverted to the input capacitance C in .At this moment, the input capacitor is charged to the peak switch voltage.Subsequently, it is discharged to zero at the end of this mode aiding in ZVS/ZVDS turn on of S 1 .If we assume the switch voltage is vs (θ), the following conditions must be satisfied in order to achieve ZVS or ZVDS: The class-E inverter operating modes are shown in Figure 2. The current through the switch diverts to charge the input capacitor Cin when the switch is closed at θ = 2πD.As soon as Cin is charged completely, the current alters direction and Cin discharges.Due to the inductive effect of the resonant tank in Mode 2, the output current (Iout) lags the output voltage (Vout).

Assumptions
The circuit analysis is performed by applying the following assumptions.a.All the components are ideal and do not possess any parasitic resistance or capacitances.b.The switch is ideal.It is an open circuit (vs = ∞) while OFF and shorted (vs = 0) while ON.c.The input current (Iin) is always positive.

Modeling Approach
Given, where, Lf_boundary = boundary value of the input inductor (Lf) while the inverter operates at the border condition mode (BCM) and N = inductance ratio.Now, the modeling approach is stated as follows Step 1: To determine the switch voltage (vs(θ)) Step 2: To apply the boundary conditions for ZVS/ZVDS and find input current (Iin(θ)) Step 3: To find Lf_boundary and the input ripple current (Δiin) Step 4: (1) To determine the average input current (Iin_avg_case2) (2) Using Iin_avg_case2 to find the input capacitance (Cin_case2) Case 3 (N ≥ 3) (1) To determine the average input current (Iin_avg_case3) (2) Using Iin_avg_case3 to find the input capacitance (Cin_case3) Step 5: To find the peak switch voltage (vs_pk) and the peak switch current (is_pk) The class-E inverter operating modes are shown in Figure 2. The current through the switch diverts to charge the input capacitor C in when the switch is closed at θ = 2πD.As soon as C in is charged completely, the current alters direction and C in discharges.Due to the inductive effect of the resonant tank in Mode 2, the output current (I out ) lags the output voltage (V out ).

Assumptions
The circuit analysis is performed by applying the following assumptions.

a.
All the components are ideal and do not possess any parasitic resistance or capacitances.b.
The switch is ideal.
It is an open circuit (v s = ∞) while OFF and shorted (v s = 0) while ON.c.
The input current (I in ) is always positive.

Modeling Approach
Given, where, L f_boundary = boundary value of the input inductor (L f ) while the inverter operates at the border condition mode (BCM) and N = inductance ratio.Now, the modeling approach is stated as follows Step 1: To determine the switch voltage (v s (θ)) Step 2: To apply the boundary conditions for ZVS/ZVDS and find input current (I in (θ)) Step 3: To find L f_boundary and the input ripple current (∆i in ) Step 4: To determine the average input current (I in_avg_case1 ) (2) Using I in_avg_case1 to find the input capacitance (C in_case1 ) Case 2 (1.5 < N < 3) (1) To determine the average input current (I in_avg_case2 ) (2) Using I in_avg_case2 to find the input capacitance (C in_case2 ) To determine the average input current (I in_avg_case3 ) (2) Using I in_avg_case3 to find the input capacitance (C in_case3 ) Step 5: To find the peak switch voltage (v s_pk ) and the peak switch current (i s_pk ) 3.2.The Derivation 3.2.1.
Step 1 If the current through the input capacitor (C in ) is I Cin , the switch voltage can be expressed as From Figure 2a, the input current I in can be written as where I r (θ) is the resonant current; I Cin is the capacitor current; I in (θ) is the input current.
From (1), Step 2 Applying v s (2π) = 0 for ZVS to (4), or, Again, applying v s (2π) = 0 and using ( 5) and (6), Now, replacing (6) into (4) and simplifying (A1) (see Appendix A) is obtained.The output power to the load is defined by or where R L is the given load resistance.Now, replacing I m from (9) into (7) and simplifying (A2) (see Appendix A) is obtained.The inductor v Lf voltage can be expressed as Now, Now, considering the initial conditions, the current through L f can be written as expressed in (A3) (see Appendix A).Now, f n (θ) can be written as where ( 12) is extended in (A4) (see Appendix A).If n is odd and m is even, by generalizing, (A4) and (A5) (see Appendix A) can be obtained for n and m, respectively.

Step 3
The boundary value of the input inductor can be determined by the following: which gives Now, the ripple current can be measured as Substituting the values of I in from (A4) and (A5) and simplifying, the following is obtained: Now, if N ≈ 1, the current is always positive and the inverter operates in close proximity of the BCM with high ripple current.The theoretical input current waveform is shown in Figure 3.In this case, the average current can be defined as Now, simplifying (17) and using (A6)-(A8) can be obtained, which is shown in the Appendix A; where Again, from (3), (A9) (see Appendix A) is obtained.Alternatively, the average current (I in_avg_case1_alt ) can be found (while n = 5 and m = 6) as shown in (A10) (see Appendix A).Accordingly, solving and simplifying (A10), (A11) (see Appendix A) is obtained, where Now, the output power of the converter is Now, I m from ( 9) for case 1 is Replacing from ( 19) in ( 18), P out,rma is obtained as demonstrated in (A12) (see Appendix A).Then, (A12) is solved for C in , where N 1 and D 1 are demonstrated in (A13) and (A14) (see Appendix A).
The negative quotient of C in_case1 is neglected.
(b) Case 2: The input average current and the input capacitance for 1.5 < N < 3: In this case, the input inductor is slightly greater than the L f_boundary (approximately 1.5 to 2.5 times of L f_boundary ).The L f_boundary , which is calculated from (14), is 50 µH and 55 µH at D = 0.55 and 0.50, respectively.The theoretical input current waveform is shown in Figure 4.The current is always positive and the inverter operates at the continuous conduction mode (CCM) with high current ripple.The average current I in_avg_case_alt as derived in (29) is appropriate.However, due to the transient nature of the input current, I in_avg_sum34 is determined to define the input current more accurately.
For a better understanding, I in_avg_78 is derived in (A15), where The current is shown in Figure 5. Now, using (21) and (A16) (see Appendix A) is solved for C in as demonstrated in (A17) (see Appendix A).The negative quotient of C in_case2 is neglected.D = 0.55 and 0.50, respectively.The theoretical input current waveform is shown in Figure 4.The current is always positive and the inverter operates at the continuous conduction mode (CCM) with high current ripple.The average current Iin_avg_case_alt as derived in (29) is appropriate.However, due to the transient nature of the input current, Iin_avg_sum34 is determined to define the input current more accurately.For a better understanding, Iin_avg_78 is derived in (A15), where ( ) The current is shown in  In this case, the input inductor is greater than the Lf_boundary (approximately 3 to 5 times of Lf_boundary).The Lf_boundary, which is calculated from (14), is 50 µH and 55 µH at D = 0.55 and 0.50, respectively.The theoretical input current waveform is shown in Figure 5.The  For a better understanding, Iin_avg_78 is derived in (A15), where ( ) The current is shown in Figure 5. Now, using ( 21) and (A16) (see Appendix A) is solved for Cin as demonstrated in (A17) (see Appendix A).The negative quotient of Cin_case2 is neglected.(c) Case 3-The input average current and the input capacitance for N ≥ 3: In this case, the input inductor is greater than the Lf_boundary (approximately 3 to 5 times of Lf_boundary).The Lf_boundary, which is calculated from (14), is 50 µH and 55 µH at D = 0.55 and 0.50, respectively.The theoretical input current waveform is shown in Figure 5.The (c) Case 3-The input average current and the input capacitance for N ≥ 3: In this case, the input inductor is greater than the L f_boundary (approximately 3 to 5 times of L f_boundary ).The L f_boundary , which is calculated from ( 14), is 50 µH and 55 µH at D = 0.55 and 0.50, respectively.The theoretical input current waveform is shown in Figure 5.The current is always positive and the inverter operates at the continuous conduction mode (CCM) with low current ripple.Moreover, in this case, I in_avg_case2 is sufficient.However, I in_avg_15-16 is determined to define the input current more accurately.The C in_case3 is shown in (A20). Hence, Replacing values in (22) and simplifying, (A18) (see Appendix A) is obtained.

Step 5
The switch voltage can be determined from ( 3), ( 6) and ( 9).Now, if n = 6, solving for dv s /dθ = 0, Replacing θ pk from (23) into (A19) (see Appendix A) gives the peak switch voltage, The switch current, Replacing I in from ( 5), The current peaks at Hence, replacing from ( 23) and ( 24) in (26), The phase difference between the output voltage and current is given in (8).Now, if In Figure 6, ϕ is plotted against D. At D = 0, ϕ is maximum at π.As D increases, the phase difference decreases.

The Input Current Ripple
The input current ripple decreases with increasing size of Lf.In Figure 7, the input current ripple percentage is demonstrated against Lf.A creases, the ripple percentage increases according to (13).However, the input cur remains positive as long as Lf > Lf_boundary.

The Input Current Ripple
The input current ripple decreases with increasing size of L f .In Figure 7, the input current ripple percentage is demonstrated against L f .As L f decreases, the ripple percentage increases according to (13).However, the input current (I in ) remains positive as long as L f > L f_boundary .9 of 23

The Input Current Ripple
The input current ripple decreases with increasing size of Lf.In Figure 7, the input current ripple percentage is demonstrated against Lf.As Lf decreases, the ripple percentage increases according to (13).However, the input current (Iin) remains positive as long as Lf > Lf_boundary.

Case 2
In Figure 9a,b, C in_case2 is plotted against D and L f , respectively, while V in = 15 V, V out_peak = 20 V, P out_rms = 10 W and f s = 150 kHz.As obvious from Figure 10a, C in_case2 is always positive for D cr ≥ 0.52, D cr ≥ 0.54 and D cr ≥ 0.60, while L f = 100, 90 and 80 µH, respectively.In Figure 9b, C in_case2 is positive for L f_c > 92.5 and L f_cr > 105.2 for D = 0.55 and 0.50, respectively.To achieve ZVS/ZVDS, these critical duty ratio and input inductances have to be maintained with C in_case1 being chosen appropriately under the specified conditions.

Case 3
In Figure 10a,b, C in_case3 is plotted against D and L f , respectively, while V in = 15 V, V out_peak = 20 V, P out_rms = 10 W and f s = 150 kHz.As obvious from Figure 10a, C in_case3 is always positive for D cr ≥ 0.48, D cr ≥ 0.52 and D cr ≥ 0.61, while L f = 170, 150 and 120 µH, respectively.In Figure 10b, C in_case2 is positive for L f_cr > 138.2 and L f_cr > 159 at D = 0.55 and 0.50, respectively.To achieve ZVS/ZVDS, these critical duty ratio and input inductances have to be maintained with C in_case3 being chosen appropriately under the specified conditions.

Peak Switch Voltage (V s-pk )
The peak switch voltage (v s_pk ) from ( 24) is demonstrated in Figure 11.The rating of the switch should be 2-3 times the peak voltage for safe operation under the specified operating conditions.Moreover, from Figure 12b, it is obvious that the peak switch voltage can be lowered by lowering the output power at a given D and R L .Similarly, it can be lowered by lowering the R L at a given D and P out_rms as obvious from Figure 12c.However, for both cases, the output voltage is also affected with v s_pk .
The peak switch voltage (vs_pk) from ( 24) is demonstrated in Figure 11.The rating of the switch should be 2-3 times the peak voltage for safe operation under the specified operating conditions.Moreover, from Figure 12b, it is obvious that the peak switch voltage can be lowered by lowering the output power at a given D and RL.Similarly, it can be lowered by lowering the RL at a given D and Pout_rms as obvious from Figure 12c.However, for both cases, the output voltage is also affected with vs_pk.

Peak Switch Current (is-pk)
The peak switch current (is_pk) from ( 28) is demonstrated in Figure 12.The peak current has a maximum in the mid region of D (0.3 to 0.5) and gradually decreases on both sides.Hence, given the optimum D = 0.5, the rating of the switch should be 2-3 times the peak current for safe operation.

Simulation and Experimental Verification
The class-E inverter is simulated in MATLAB Simulink environment to demonstrate the waveforms.Table 1 demonstrates the common parametric values.
The Lr and Cr is selected to maintain a high loaded QL factor (QL ≥ 10), which is given as

Peak Switch Current (i s-pk )
The peak switch current (i s_pk ) from ( 28) is demonstrated in Figure 12.The peak current has a maximum in the mid region of D (0.3 to 0.5) and gradually decreases on both sides.Hence, given the optimum D = 0.5, the rating of the switch should be 2-3 times the peak current for safe operation.

Simulation and Experimental Verification
The class-E inverter is simulated in MATLAB Simulink environment to demonstrate the waveforms.Table 1 demonstrates the common parametric values.The L r and C r is selected to maintain a high loaded Q L factor (Q L ≥ 10), which is given as Hence, the resonance frequency of the circuit is Once, L r is selected for the desired Q L from (46), C r can be determined.In this case, the input inductor is equal or close to the L f_boundary .The L f_boundary , which is calculated from (14), is 50 µH and 55 µH at D = 0.55 and 0.50, respectively.The output voltage and power of the inverter should demonstrate the specified value with minimal error.In addition, the average input current from the simulation must concur with the analytical value from (A8).Accordingly, as C in is implemented calculated from (A17), the ZVS/ZVDS should be executed.
The circuit is simulated at the designated parametric values stated in Table 1.The output voltage and power waveforms are shown in Figure 13 for D = 0.50.As opposed to the ideal lossless analytical model, the switch in the simulation induces a conduction loss across the ON resistance (R ds-ON = 0.015 Ω).
In Figure 14, the analytical values of V in , V out , P in , P out , η, I in_avg , I m from the proposed model and [1,2] are stated along with the simulated results for D = 0.55 and 0.50.The percentage differences between the analytical and simulation results are calculated.
error.In addition, the average input current from the simulation must concur with the analytical value from (A8).Accordingly, as Cin is implemented calculated from (A17), the ZVS/ZVDS should be executed.
The circuit is simulated at the designated parametric values stated in Table 1.The output voltage and power waveforms are shown in Figure 13   voltage and power of the inverter should demonstrate the specified value with minimal error.In addition, the average input current from the simulation must concur with the analytical value from (A8).Accordingly, as Cin is implemented calculated from (A17), the ZVS/ZVDS should be executed.The circuit is simulated at the designated parametric values stated in Table 1.The output voltage and power waveforms are shown in Figure 13 for D = 0.50.As opposed to the ideal lossless analytical model, the switch in the simulation induces a conduction loss across the ON resistance (Rds-ON = 0.015 Ω).In Figure 14, the analytical values of Vin, Vout, Pin, Pout, η, Iin_avg, Im from the proposed model and [1,2] are stated along with the simulated results for D = 0.55 and 0.50.The percentage differences between the analytical and simulation results are calculated.In Figure 14a, at D = 0.55, Vout_peak and Pin from the proposed model demonstrate a difference of 2.43% and 17.29% with the simulated value, respectively.For [1], these differences are maximum at 24.85% and 67.29%, respectively.In Figure 14b, the proposed model demonstrates a difference of 9.05% and 15.17% for Iin_avg and Im while the maximum In Figure 14a, at D = 0.55, V out_peak and P in from the proposed model demonstrate a difference of 2.43% and 17.29% with the simulated value, respectively.For [1], these differences are maximum at 24.85% and 67.29%, respectively.In Figure 14b, the proposed model demonstrates a difference of 9.05% and 15.17% for I in_avg and I m while the maximum is 64.05% and 34.74%, respectively, for [1].
In Figure 14c, at D = 0.50, P in , P out_rms and V out_peak demonstrate a difference of 10.25, 37.34 and 16.90%, respectively, for the proposed model.These parameters demonstrate a maximum difference of 52.03, 48.09 and 19.45%, respectively, for [1].Again, in Figure 14d, a maximum difference of 52.07% in I in_avg and 31.11% in I m are observed for [1].However, I in_avg and I m are most accurately determined by the proposed model and [2] demonstrating an error of 9.25% and 4.38%, respectively.
In Figure 15, the input average current for the proposed model, the model in [1,2] and for the simulation is demonstrated against D. As obvious, the optimum operating condition for the proposed model is D ≈ 0.43 to 0.61.The shaded area stands for an error ≤10%.
(c) (d) In Figure 14a, at D = 0.55, Vout_peak and Pin from the proposed model demonstrate a difference of 2.43% and 17.29% with the simulated value, respectively.For [1], these differences are maximum at 24.85% and 67.29%, respectively.In Figure 14b, the proposed model demonstrates a difference of 9.05% and 15.17% for Iin_avg and Im while the maximum is 64.05% and 34.74%, respectively, for [1].
In Figure 14c, at D = 0.50, Pin, Pout_rms and Vout_peak demonstrate a difference of 10.25, 37.34 and 16.90%, respectively, for the proposed model.These parameters demonstrate a maximum difference of 52.03, 48.09 and 19.45%, respectively, for [1].Again, in Figure 14d, a maximum difference of 52.07% in Iin_avg and 31.11% in Im are observed for [1].However, Iin_avg and Im are most accurately determined by the proposed model and [2] demonstrating an error of 9.25% and 4.38%, respectively.
In Figure 15, the input average current for the proposed model, the model in [1,2] and for the simulation is demonstrated against D. As obvious, the optimum operating condition for the proposed model is D≈ 0.43 to 0.61.The shaded area stands for an error ≤10%.As stated previously, this model is accurate when the input inductor is equal or close to the boundary value (Lf_boundary).Hence, the analytical value of Iin should closely match to that from the simulation.In Figure 16, the input average current for the proposed model is compared with [1,2] and the simulation against D. The results are summarized in Table 2.As obvious, the percentage error between the analytical and simulated values are As stated previously, this model is accurate when the input inductor is equal or close to the boundary value (L f_boundary ).Hence, the analytical value of I in should closely match to that from the simulation.In Figure 16, the input average current for the proposed model is compared with [1,2] and the simulation against D. The results are summarized in Table 2.As obvious, the percentage error between the analytical and simulated values are maximum when the input current is negative (at low L f ).As L f approaches to L f_boundary , the current always remains positive.Subsequently, the error is minimized.As L f continues to increase from L f_boundary , I in_avg_56 provides better approximation than I in_avg_12 .This is because of the transient nature of the current when the switch is turned ON.The error is as low as 1.5% (for I in_avg_12 ) near L f_boundary and 3.10% (for I in_avg_56 ) at higher inductances.This is graphically shown in Figure 16a,b where the high error region (>20%) is shaded for D = 0.55 and D = 0.50, respectively.Accordingly, this region falls out of the scope of this model because of a significant error in approximating the average input current.

Case-2: The Continuous Conduction Mode (1 < N < 3)
As stated earlier, the input inductor is slightly greater than the L f_boundary (approximately 1.5 to 2.5 times of L f_boundary ).The analytical values of V out , P out , I in_avg and I m are derived in Section 3.2.In this section, the average input current for the proposed model as stated in (A15) is calculated and compared with the simulation results.
In Figure 17, the input average current for the proposed model, the model in [1,2] and for the simulation is demonstrated against D. The optimum operating condition for the proposed model is D ≈ 0.50 to 0.63.The shaded area stands for an error ≤10%.mately 1.5 to 2.5 times of Lf_boundary).The analytical values of Vout, Pout, Iin_avg and Im are derived in Section 3.2.In this section, the average input current for the proposed model as stated in (A15) is calculated and compared with the simulation results.
In Figure 17, the input average current for the proposed model, the model in [1,2 and for the simulation is demonstrated against D. The optimum operating condition fo the proposed model is D ≈ 0.50 to 0.63.The shaded area stands for an error ≤10%.In Figure 18, the input average current for the proposed model is compared with [1,2] and the simulation against D. The analytical and simulation results are summarized in Table 3. Owing to the transient nature of the input current, I in_avg_56 gives rise to significant error in tracking the simulated values.The error becomes maximum, i.e., 44% and 36% at D = 0.55 and 0.50, respectively, for L f = 110 µH.However, I in_avg_sum34 provides a better approximation of the input current as L f continues to increase.The minimum error of 0.36% and 16 % is recorded at D = 0.55 and 0.50, respectively, for L f = 110 µH.The results are graphically shown in Figure 18a,b where the lower error region (≤10%) is shaded.For case 3, the input inductor is greater than the Lf_boundary (approximately 2.5 to 5 tim of Lf_boundary).The analytical values of Vout, Pout, Iin_avg and Im are derived in Section 3.2.In t section, the average input current for the proposed model as stated in (A19) is calcula and compared with the simulation results.In Figure 19, the input average current for proposed model, the model in [1,2] and for the simulation is demonstrated against D. T optimum operating condition for the proposed model is D ≈ 0.50 to 0.63.The shaded  In Figure 20, the input average current for the proposed is compared with [1,2] and the simulation against D. The analytical and simulation results are summarized in Table 4. Owing to the transient nature of the input current, I in_avg_sum34 gives rise to significant error in tracking the simulated values at L f = 160 µH.Beyond the latter, I in_avg_sum56 provides a better approximation of the input current than [1,2]   The switch voltage and current waveforms are shown in Figure 22a,b for D = 0.50 and 0.55, respectively, for case 2. As expected, the switch voltage is either zero or negative at constant dvs/dt.In Figure 22, the switch voltage and current waveforms are multiplied to measure the turn off losses.As observed, the turn off loss (Pswitching_loss_rms) is approximately 0.60, 1.08 and 1.52% of the output power (Pout_rms =7.786 W) for D = 0.50 and 0.55, respectively.In all cases, the turn on loss is negligible.The results are accumulated in Table 5.The switch voltage and current waveforms are shown in Figure 23a,b for D = 0.50, 0.55 and 0.60, respectively, for case 3.As expected, the switch voltage is either zero or negative at constant dvs/dt.In Figure 23, the switch voltage and current waveforms are multiplied to measure the turn off losses.As observed, the turn off loss (Pswitching_loss_rms) is approximately 0.56, 0.20 and 1.27 % of the output power (Pout_rms = 7.786 W) for D = 0.50 and 0.55, respectively.In all cases, the turn on loss is negligible.The results are accumulated in Table 5 below.The switch voltage and current waveforms are shown in Figure 22a,b for D = 0.50 and 0.55, respectively, for case 2. As expected, the switch voltage is either zero or negative at constant dv s /dt.In Figure 22, the switch voltage and current waveforms are multiplied to measure the turn off losses.As observed, the turn off loss (P switching_loss_rms ) is approximately 0.60, 1.08 and 1.52% of the output power (P out_rms = 7.786 W) for D = 0.50 and 0.55, respectively.In all cases, the turn on loss is negligible.The results are accumulated in Table 5.The switch voltage and current waveforms are shown in Figure 22a,b for D = 0.50 and 0.55, respectively, for case 2. As expected, the switch voltage is either zero or negative at constant dvs/dt.In Figure 22, the switch voltage and current waveforms are multiplied to measure the turn off losses.As observed, the turn off loss (Pswitching_loss_rms) is approximately 0.60, 1.08 and 1.52% of the output power (Pout_rms =7.786 W) for D = 0.50 and 0.55, respectively.In all cases, the turn on loss is negligible.The results are accumulated in Table 5.The switch voltage and current waveforms are shown in Figure 23a,b for D = 0.50, 0.55 and 0.60, respectively, for case 3.As expected, the switch voltage is either zero or negative at constant dv s /dt.In Figure 23, the switch voltage and current waveforms are multiplied to measure the turn off losses.As observed, the turn off loss (P switching_loss_rms ) is approximately 0.56, 0.20 and 1.27 % of the output power (P out_rms = 7.786 W) for D = 0.50 and 0.55, respectively.In all cases, the turn on loss is negligible.The results are accumulated in Table 5 below.In Figure 24, the switching waveforms reconfirms the ZVS achievement for case 1, 2 and 3.In Figure 24, the switching waveforms reconfirms the ZVS achievement for case 1, 2 and 3.In Figure 24, the switching waveforms reconfirms the ZVS achievement for case 1, 2 and 3.

Conclusions
In this paper, the class-E inverter is modeled and analyzed for ZVS/ZVDS implementation.The modeling is based upon determining the input current to the inverter for various input inductances and state of ripple current under a specified condition.A comprehensive simulation and experimental testing are performed to support the proposed analytical model.Eventually, as opposed to the existing models, the proposed model can determine the input current, input/output power, efficiency more accurately.The percentage of error is also determined for different size of the input inductor and the duty ratio.For most of the part, the percentage error increases with increasing input inductor size at higher duty ratio and decreases at lower duty ratio.This input current is also used to determine the input capacitance of the inverter to aid ZVS/ZVDS execution.It is observed that the percentage loss is <2% for all cases.In general, the results demonstrate that the proposed model is in better agreement with the test results as compared with the other existing models regardless of the inductance and the input ripple current.

Figure 1 .
Figure 1.The class-E inverter. and

. 2 . 4 . Step 4 (a) Case 1 :
The input average current and the input capacitance for N ≈ 1

Figure 3 .Figure 3 .
Figure 3.The theoretical input current when N ≈ 1 and D = 0.50.Assume usual units for all parameters.

Figure 4 .
Figure 4.The theoretical input current when 1 < N < 3 and D = 0.50.Assume usual units for all parameters.

Figure 5 .
Now, using (21) and (A16) (see Appendix A) is solved for Cin as demonstrated in (A17) (see Appendix A).The negative quotient of Cin_case2 is neglected.(c) Case 3-The input average current and the input capacitance for N ≥ 3:

Figure 5 .
Figure 5.The theoretical input current when N > 3 and D = 0.50.Assume usual units for all parameters.

Figure 4 .
Figure 4.The theoretical input current when 1 < N < 3 and D = 0.50.Assume usual units for all parameters.

Figure 4 .
Figure 4.The theoretical input current when 1 < N < 3 and D = 0.50.Assume usual units for all parameters.

Figure 5 .
Figure 5.The theoretical input current when N > 3 and D = 0.50.Assume usual units for all parameters.

Figure 5 .
Figure 5.The theoretical input current when N > 3 and D = 0.50.Assume usual units for all parameters.

Figure 6 .
Figure 6.The phase difference against D at V in = 15 V, V out_peak = 20 V, P out_rms = 10 W and f s = 150 kHz.

Figure 7 .
Figure 7. L f vs. M (input current ripple percentage) at D = 0.55, V in = 15 V, V out = 20 V, P out = 10 W, C in = 13 nF and f s = 150 kHz.

Figure 12 .
Figure 12.The peak switch current (i s_pk ) against D.
for D = 0.50.As opposed to the ideal lossless analytical model, the switch in the simulation induces a conduction

Figure 14 .
Figure 14.The comparison of the analytical and simulated results of (a) P in , V out_peak and P out_rms at D = 0.55; (b) η, I in_avg and I m at D = 0.55; (c) P in , V out_peak and P out_rms at D = 0.50; (d) η, I in_avg and I m at D = 0.50.
as L f continues to increase.The minimum error of 7.56% and 1.39% is recorded at D = 0.55, L f = 180 and D = 0.50, L f = 200, respectively.The results are graphically shown in Figure 20a,b where the lower error region (≤10%) is shaded.

Figure 22 .
Figure 22.Case 2: (a) The switching waveforms at D = 0.50, Lf = 80 µH and Cin = 10 nF (b) The switching waveforms at D = 0.55, Lf = 100 µH and Cin = 5 nF.The switch voltage and current waveforms are shown in Figure 23a,b for D = 0.50, 0.55 and 0.60, respectively, for case 3.As expected, the switch voltage is either zero or negative at constant dvs/dt.In Figure 23, the switch voltage and current waveforms are multiplied to measure the turn off losses.As observed, the turn off loss (Pswitching_loss_rms) is approximately 0.56, 0.20 and 1.27 % of the output power (Pout_rms = 7.786 W) for D = 0.50

Table 1 .
Specifications for Class-E Inverter.

Table 2 .
The input current comparison against Lf (Iin_avg_12 and Iin_avg_56) D = 0.55

Table 2 .
The input current comparison against L f (I in_avg_12 and I in_avg_56 ).

Table 3 .
The input current comparison against Lf (Iin_avg_56 and Iin_avg_sum34)

Table 3 .
The input current comparison against L f (I in_avg_56 and I in_avg_sum34 ).

Table 5 .
The Approximate Switching Losses in Case 1, 2 and 3.

Table 5 .
The Approximate Switching Losses in Case 1, 2 and 3.

Table 5 .
The Approximate Switching Losses in Case 1, 2 and 3.