Design of a Charge Pump Circuit and System with Input Impedance Modulation for a Flexible-Type Thermoelectric Generator with High-Output Impedance

: This paper describes a charge pump system for a ﬂexible thermoelectric generator (TEG). Even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by modulating the input impedance of the charge pump using two-phase operation with low- and high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. How the system can be designed is also described in detail. A design demonstration was performed for the TEG with 400 W . The fabricated system was also measured with a ﬂexible-type TEG based on carbon nanotubes. Even with an output impedance of 1.4 k W , the system converted thermal energy into electric power of 30 (cid:22) W at 2.5 V to the following sensor ICs.


Introduction
The Internet of Things (IoT) currently is attracting researchers' attention, which is a system for the interaction of information from things such as sensing edge devices to the cloud and servers via the Internet and vice versa [1]. The maintenance costs to replace batteries can be a large portion of the costs of edge devices. Therefore, it is expected that sensing devices should be battery free based on the energy transducer generating electric power from environmental energy such as sunlight and vibration kinetic energy. A thermoelectric generator (TEG) extracts power from a temperature gradient. The opencircuit voltage V OC of the TEG increases in proportion to the temperature difference between hot and cold heat sources [2]. Bulk-type TEGs [3] have a low output impedance (R TEG ) of the order of Ω and are in production together with boost converters. Flexible-type thin film TEGs [4] are expected to have various applications because they can be placed on curved surfaces. A drawback of the flexible-type TEG is the high-output impedance of the order of 10-100 Ω, especially in the case of a small form-factor. Even worse, a low-cost small form-factor TEG generates V OC as low as a few hundred mV. To operate sensor ICs, boost converters are required [5][6][7]. In this research, the design of boost charge pump circuits (CPs) is proposed for a flexible-type TEG with high-output impedance, as illustrated in Figure 1. Such a system is used for heat pipes [8] and wrist watches [9].
To design systems with TEGs and integrated CPs, the circuit area and power conversion efficiency (PCE) are key figures of merit. Table 1 summarizes the key features of existing designs and this work. In [10], the design of low-voltage CPs was developed to strike a balance between the circuit area and power efficiency under the conditions of a given output voltage and current. In this design, CPs are driven by voltage sources with zero impedance, while TEGs have a finite output impedance. In [11], both TEGs and CPs were optimally designed to minimize their areas when CPs were driven by TEGs. However, design constraints such as temperature differences and the number of TEG units connected in parallel and in series were not taken into consideration. A design methodology was proposed when V OC and R TEG were given in [12,13]. In [12], an optimum design was provided to determine the dimensions of switching devices and the clock frequency to maximize the output power of the CP when the number of stages N and stage capacitors C of the CP and the V OC and R TEG of TEG were given. However, the output voltage of the CP was not given, whereas the input voltage of the load circuit must be controlled with a specific voltage. In [13], how the input voltage of the CP or the output voltage of the TEG is determined theoretically was discussed when the circuit area of the CP was minimized or, in other words, when the output power of the CP was maximized with a given CP circuit area to generate a target output current at a specific output voltage, as shown in Figure 2a, which is the same target design of this work. However, the minimum operation voltage of circuits was not considered in [13], but it was assumed that the input voltage of the CP can be set at any voltage. Furthermore, no control circuit was disclosed to control the input voltage of the CP in [13]. In this work, the minimum operating voltage of the circuits was taken into consideration in the design, as shown in Figure 2b. This can be a key design point especially for TEGs with a high-output impedance, which have a potentially large IR drop at V DD .
This paper is an extended version of a conference paper [14] to describe its details. A control circuit to operate the CP was proposed to meet the demand that the output current be generated as high as the target current at a specific voltage while the input voltage of the CP is controlled at a voltage higher than the minimum operating voltage. The designs of the CP system and building blocks are presented in Sections 2.1 and 2.2, respectively, to discuss how the circuits can be optimally designed. The entire system was fabricated in 65 nm CMOS. Experimental results are shown in Section 2.3, and Section 3 gives a summary of this work.  Figure 3 illustrates the proposed CP system to extract power from the TEG with high-output impedance and to drive the following sensor ICs. Table 2 shows the condition to resume or suspend CP operation. A detector DETi monitors V DD and outputs ENi. A detector DETo monitors V PP and outputs ENo. Only when both signals become high, an oscillator OSC outputs a clock to drive the CP. Otherwise, the OSC stops working to not drive the CP. The third detector DETpp generates a signal VPP_OK to let the sensor ICs know the supply voltage is sufficiently high to work.  Table 2. Operation condition of the main CP against V DD and V PP . Figure 4 shows two operation phases in steady state. In Phase (a), the CP inputs the current mainly from C DD . Even though R TEG is much larger than the input impedance of CP, V DD can be controlled to be higher than V DD_MIN . Phase (a) starts with EN high when V PP hits V PPM = V PPT , where V PPM and V PPT are the minimum voltage of V PP and the target voltage of V PP , respectively. V PP increases while V DD decreases due to CP operation. EN goes low when (1) ENo goes low or (2) ENi goes low. In the case of (1), the ripple V PP is determined by the loop response from the output node of the CP to EN. V DDM must be higher than V DDT . In the case of (2), V DDM is equal to V DDT . In Phase (b), V DD increases with the charging current from the TEG, while V PP decreases with the discharging load current. The input impedance of the CP becomes very large because the main charge pump CP is suspended with EN low, even though a small amount of current flows into small building blocks such as LV-CP. Thus, even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by modulating the input impedance of the charge pump using two-phase operation with lowand high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. On the other hand, such an operation is not required when the output impedance of TEGs such as the bulk-type is much lower than the input impedance of the CP in operation. The operating point approaches V OC , but the system can work as long as V OC is higher than the minimum operating voltage.

System Design
I PP and I LOAD are related as Equation (3).
When one can regard I TEG as constant in the case of ∆V DD << V DD , I DD and I TEG are related as Equation (4).

Building Blocks' Design
B1: Main charge pump The given design parameters are the minimum open-circuit voltage of the TEG (V OCMIN ), R TEG , V PPT . The number of stages N was designed to maximize I PP at V PPT when the circuit area is given. Based on [15], N is given by Equation (5).
where [x] indicates the floor function of x, N MIN is the minimum number of stages to barely generate V PP , and V EFF TH is an effective threshold voltage of switching transistors, which were called ultra-low power diodes in [16]. The capacitance of each stage capacitor C is related with I PP and I DD as Equations (6) and (7), where the clock frequency f is determined to maximize I PP .
where α T and α B are the ratios of the top (C TOP ) and bottom plate parasitic capacitance (C BTM ) to C, C TOP /C and C BTM /C, respectively. Note that C BTM includes the parasitic capacitance of an oscillator to drive the main CP. I CTRL is the input current for the control circuits, which was assumed to be βI DD using the design parameter β (<1) in this paper because the auxiliary circuits assumed in this paper as shown later steadily ran regardless of T ON . I DD is also given by Equation (8) at the extreme case of T ON = T and T OFF = 0.
To have a duty ratio of T ON /T smaller than a factor of γ, the C to be designed must be increased by a factor of 1/γ. The parameters shown in Table 3 were used for design demonstration. V DDMIN was mainly determined by the technology used to design, e.g., the availability of low-Vt CMOS and circuits used in the system. As will be shown later, it was limited by an oscillator to generate a clock with 10 MHz. Such a moderate frequency was required to have a sufficiently small circuit system built in the same sensor ICs. From Equations (5) and (9), N and C were calculated to be 19 and 4.8 pF at V DDT = 0.5 V, respectively. Figure 5 shows P PP and CP area NC/ γ as a function of V DD .

B2: Auxiliary circuits
As illustrated in Figure 3, the detectors compare V DD and V PP with a reference voltage V REF generated by bandgap reference BGR [17]. To provide a supply voltage V 1V~1 V to the BGR, another small CP (LV-CP) was implemented. The LV-CP is operated in open loop not to affect the V DDMIN of the system. A dedicated oscillator starts running without any input signal other than V DD . When LV-CP converts power to the output terminal and V 1V reaches about 1 V, a clamping circuit CLAMP with NMOSFETs connected in series with the output terminal clamps the output voltage. V 1V is also used as the supply voltage of all the logic gates and the detectors. Figure 6 shows a simulated result of the BGR. V REF is saturated when V 1V > 0.8 V.

Experimental Results
The system was designed in 65 nm low-Vt CMOS technology, as shown in Figure 7. The entire area was 0.28 µm 2 . The CPs had an N of 20 and a C of 15 pF. The LV-CP had an N of six and a C of 3 pF to generate the supply current of 10 µA at 1 V, which was sufficiently high for the following circuits while keeping γ < 0.2. The input terminal was connected to an equivalent circuit of the TEG with V OC and R TEG . A C DD of 300 nF and a C PP of 1 nF were connected to the input and output terminals of the CP system, respectively. Since the system did not work at a V OC of 0.6 V probably because the V TH of MOSFETs was close to the slow corner while the simulation was performed at the typical corner, the experiments were performed at V OC of 0.8 V. Figure 8 shows I PP , I DD , V DD , and P PP as a function of V PP where V PP was varied by varying the load resistance. All the simulations were performed with the slow-corner model. The measured results were matched with the simulated ones with an error of about 10%. V PP was regulated at 2.5 V when I PP was 25 µA or lower. The average V DD was 0.6 V or higher when V PP was regulated. To see the dynamic response of V PP and V DD against V OC , V OC was made to go up and down between 0.5 V and 1 V in 200 µs, as shown in Figure 9. A signal EN was also monitored using a buffer whose supply voltage was V 1V . In the period T 1 , because V DD was lower than V DDT , EN stayed low. In the period T 2 , because V DD was higher than V DDT , but V PP was lower than V PPT , EN stayed high. Once V PP reached V PPT , in the period T 3 , the system stayed in the steady state where the T ON /T OFF operation was repeated to keep V PP and V DD at V PPT and V DDT , respectively. The system was also tested with the TEG using a thermal source, as shown in Figure 10. The TEG was based on carbon nanotubes [18]. The TEG module was built to fit with a pipe, which flowed hot liquid or gas. Because the TEG module had an R TEG of 1.4 kΩ, V OC needed to be set at a higher voltage of 1.1 V with a temperature difference of 66 K to enable the fabricated converter system to be functional, as shown in Figure 11.   Figure 12 shows I PP , I DD , V DD , P PP , η SYS , and η CP as a function of V PP . η SYS and η CP are defined by (V PP ×I PP )/(V OC ×I DD ) and (V PP ×I PP )/(V DD ×I DD ), respectively. The V PP regulation point was different by 0.3 V between measured and simulated, but the electric values except for it were in good agreement. It was confirmed that the converter system with the TEG module under the experimental condition could supply power of 30 µW at 2.5 V to the following sensor ICs. The overall power conversion efficiency η SYS was hit at about 7% against a theoretical limit with no loss of 50%. The power conversion efficiency of the converter system η CP was 15% when V DD was 0.55 V at V PP of 2.5 V, i.e., a voltage ratio (V PP /V DD ) of 4.5. For comparison, η CP of 20%, 32%, and 45% was realized with a V DD of 0.1 V, 0.2 V, and 0.3 V at a V PP of 0.5 V, respectively, in [10]. Thus, the η CP of the proposed converter system was a little lower than that of [10] at the voltage ratio of 4.5. The design optimization may need to be improved to increase power conversion efficiency by including the TEG electrical parameters in the design parameters.

Conclusions
A charge pump circuit system was presented for energy harvesting based on a flexibletype thermoelectric generator with high-output impedance. Even though the charge pump was operated with a highly resistive TEG, the input voltage could be controlled at a voltage higher than V DDMIN by modulating the input impedance of the CP using two-phase operation with low-and high-input impedance modes. The average input impedance could be matched with the output impedance of TEG. The design methodology was proposed to determine the N and C of the main charge pump when V OC , R TEG , V PP , f, and V DD MIN were given. The system was fabricated in 65 nm CMOS to demonstrate the functionality of the system with the TEG. Using an equivalent circuit for the TEG, the system was validated with a V OC of 0.8 V and an R TEG of 400 Ω. V PP regulation was successfully observed. The circuit system was also measured with a flexible-type TEG and a thermal source. The system converted thermal energy into power to 30 µW at 2.5 V. By adding a full-bridge rectifier between the energy transducer and the proposed converter, the control circuit would be able to work even with other energy transducers such as piezoelectric or electrostatic vibration energy transducers with an AC equivalent voltage source and high-output impedance.

Conflicts of Interest:
The authors declare no conflict of interest.