Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

: Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Further-more, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a sim-plified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness ( t fe ), intermediate insulator thickness ( t ox ), silicon channel radius ( R ), and interface trap densities ( N et ).


Introduction
When the MOSFET (metal-oxide semiconductor FET) technology was reduced to around a 20 nm technology node, the off current increase caused by the short-channel effect made it difficult to utilize any more planar-type MOSFET device structures. For this reason, the ultra-thin semiconductor-on-insulator (UTSOI) structure that can effectively reduce the effect of the source-drain region on the channel region and the FinFET structure using a three-dimensional (3D) channel structure to improve gate controllability has been proposed to enable continuous scaling down of CMOS (complementary metal-oxide semiconductor) technology. However, the FinFET, having a multi-gate structure, has a limitation in scaling down at a technology node of 5 nm or less, so the introduction of a GAA type MOSFET structure is being considered to improve the gate control capability [1,2]. As well as such a multi-gate architecture, various device structures using a junctionless transistor structure or a channel material other than silicon have been proposed for various applications [3][4][5][6].
In addition to the introduction of new transistor architectures, reducing power consumption of the transistor has become a very important issue [7,8]. This is because the density of power consumption inside the semiconductor chip increases exponentially as the number of semiconductor elements integrated in a unit area increases. Such an increase in temperature in semiconductor chips causes the clock frequency of the CPU to be stagnant beyond a certain frequency (~3 GHz), making it a big bottleneck for improving CPU performance [9]. In addition, energy-saving ultra-low-power semiconductor technology is urgently required for semiconductor technology for Internet of Things (IoT) applications to build an ultra-connected society [10]. So, various transistor technologies have been proposed to solve the problem of power consumption density, which increases exponentially as the number of semiconductor technology nodes decreases. Representative examples of low-power semiconductors are NC-FET [11][12][13] and tunneling-FET (T-FET) [14][15][16]. For transistor-level integrated circuit design, it is essential to develop a compact model based on transistor device physics to simulate electrical characteristics such as current-voltage of integrated circuits in electronic design automation (EDA) software such as SPICE. Compact models based on threshold voltage (Vth) of transistor devices have been widely used for a long time, but recently, compact models based on channel surface potential with improved convergence and linearity characteristics have been developed and widely used. Representative examples of Vth-based and surface potential-based models are the BSIM4 (Berkeley short-channel IGFET model) and BSIM-CMG (common multigate), respectively [17,18].
Recently, an NC GAA-FET having a metal-ferroelectric-insulator-semiconductor (MFIS) type has been investigated by introducing NC characteristics to a gate stack as a next-generation semiconductor in a GAA transistor [19,20]. In addition, it has been reported that interface traps at the Si-SiO2 interface can result in the degradation of transistor performance (e.g., sub-threshold swing) [21], the process-variable ∆Vth [22], and negative bias temperature instability (NBTI)-induced ∆Vth [23]. This interface trap effect has been considered important from before in silicon GAA-FET without ferroelectric material, and compact modeling methodologies have been proposed [24]. Therefore, as mentioned, an accurate physical-based model is required for the design of integrated circuits of NC GAA-FETs with consideration of interface traps. Amol D. Gaidhane et. al. presented a comprehensive current-voltage model of NC GAA-FET based on the channel surface potential [25]. The model proposed by Amol D. Gaidhane et. al. combines the previously presented GAA-MOSFET model [26][27][28][29][30] with a Landau-Devonshire (LD) Equation that describes the NC properties of ferroelectric materials to obtain the surface potential approximately, and solves the current Equation based on the surface potential. Although previous work [25] has accurate results, the complexity of formulas makes it difficult for semiconductor device and circuit designers to have an intuition to the electrical characteristics of NC GAA-FET through the derived model equation. In addition, the effect of interface traps was not considered.
In this work, simple and analytical current-voltage equations of NC GAA-FET in each operating region, such as linear, saturation, and sub-threshold regions, are derived, and the proposed model, for the first time, takes the interface traps at Si-SiO2 of NC GAA-FET. In addition, by using the proposed model, the device electrical behaviors according to the basic device design parameters such as tfe, tox, R, and Net were explored.

Method of Calculating Surface Potential of NC-GAA FET
The considered NC GAA-FET is shown in Figure 1 as an undoped channel and cylindrical GAA structure. Source and drain regions are highly doped, ignoring parasitic resistance effects in these regions. The gate stack consists of a metal gate-electrode/ferroelectric/bottom insulator/semiconductor where the bottom insulator layer is SiO2. Following the gradual channel approximation (GCA) and considering cylindrical coordinates, the general one-dimensional Poisson's Equation of the intrinsic channel region of NC GAA-FET can be expressed as where is the electron charge, is the permittivity of the silicon channel, and ( ) is the free carrier charge density, which is expressed as ( ) = ( ( − ) ⁄ ). In this density equation, is the intrinsic carrier concentration, is the electron quasi-Fermi potential, is the Boltzmann constant, and ( ) is the electrostatic potential. Equation (1) satisfies the following boundary conditions: is the surface potential. According to the GCA, Vn is constant along the r-direction, i.e., Vn = Vn(y). Equation (1) can be solved analytically as in Equation (2), which is the same as the result of the GAA FET presented in previous works [15,[26][27][28][29] without a ferroelectric layer.
where R is the radius of the silicon channel, and β is the dimensionless intermediate parameter related to through the secondary boundary condition. The voltage balance condition of NC-GAA FET is written as is voltage across the ferroelectric layer, and is voltage across the dielectric layer between the ferroelectric layer and silicon channel. According to Landau-Devonshire theory, can be expressed in terms of mobile charge density, Q, as where the coefficients a0 and b0 are related to the Landau parameters (a and b) of the ferroelectric material for a cylindrical gate, and they are expressed as [25] (a) (b) where tox is the thickness of intermediate insulator layer and tfe is the ferroelectric thickness. In addition, can be expressed as = / where = ( (1 + ⁄ )) ⁄ . Firstly, according to Gauss' law, the mobile charge density, Q, can be determined, using Equation (2) as an intermediate parameter. Then the voltage balance equation can be formulated as Equation (7). This modeling methodology of the surface potential was used in [25], and this work also utilizes it and tries to write it down repeatedly to avoid confusion.
Therefore, the formula for β related to the surface potential can be obtained as in Equation (8) by substituting Q of Equation (6) into Equation (7).
Since Equation (7) is not a closed form equation, it can be solved analytically through numerical calculation to obtain an accurate solution for β, or by using advanced mathematical techniques such as the Lambert-W function [30] and asymptotic equations [25]. In this work, β was obtained by introducing an asymptotic equation and a smoothing function. In this paper, we consider only acceptor-like trap states. Interface trap charge, , can be written as = − ⋅ ⋅ ( ), where ( ) is occupation probability of an acceptor-like trap with energy level, is energy of single interface charge trap, and is interface trap density per unit surface. By defining = − and using = −( − )/ , interface trap charge can be obtained as Equation (10), where is the intrinsic fermi level energy and is fermi level energy.
Finally, we can solve surface potential by using a self-consistent method, as shown in Figure 2, which is a similar method to previous papers of [24] that calculate the surface potential considering the interface trap in a device structure without a ferroelectric layer.

Analytical Drain Current Model for NC-GAA FET
We can obtain the current equation by using the drift-diffusion current equation: = (2 ) ⁄ . For convenience, we define = 1 − . Integrating this equation from the source to the drain and changing from the function of to the function of , we can obtain a different expression of the drift-diffusion current equation: where L is the channel length, μeff is the effective mobility, and and are solved from Equation (8) corresponding to = 0 and = , respectively. Note that / can be expressed as a function of by differentiating Equation (8). Substituting these factors in Equation (11), integration can be performed analytically to yield where new functions, f ( ), g ( ), are defined in Equation (10) as Following the approach of D. Jimenez [28], we can derive the analytical drain current Equation with closed-form by carefully checking the fluctuation of ℎ( ) and , which has different values at each operation region; ℎ( ) of Equation (8).
Finally, to obtain the unified current equations, we use the smoothing function as where A = 4 − ε and ε ∈ (0,1). In this work, a long-channel ideal characteristic model was developed using a channel length of 1 μm. By adding various short-channel effects (e.g., drain-induced barrier lowering, threshold voltage roll-off, velocity saturation, and so on) to the developed baseline model, it can be applied to devices with the channel length of several to tens of nanometers. Table 1 shows the key dimensions and material parameters of NC GAA-FET used in the experiments. By using these parameter values, we can validate the regional-based current-voltage model and investigate electrical behaviors of NC GAA-FET in this section. In Table 1, Nsd is the doping density in source and drain regions in Table 1. As the source and drain regions are assumed to be heavily doped with N + over 10 20 cm −3 , effects such as voltage drop due to parasitic resistance are neglected. Thus, 0 and Vds are applied to Vn (y) at the source end and drain end in Equations (1) and (2), respectively. This method is the same approach used for compact modeling intrinsic channel regions in previous papers [15,19,[24][25][26][27][28][29]31].  (5) which is corresponding coercive field Ec = 1.15 MV/cm and remnant polarization Pr = 5 μC/cm 2

Results and Discussion
The derived model is a surface potential ( )-based model, and it can be calculated from Equation (8) followed by asymptotic equations. Figure 3a-d show as a function of , , R, and . As shown in Figure 3a, the surface potential increases as tfe increases, which is due to the improved capacitance matching between the ferroelectric layer and the intermediate insulator. Similarly, when the capacitance between the ferroelectric layer and the intermediate insulator deviates due to tox variation from the wellmatched state, it can be seen that the voltage amplification characteristic decreases, as shown in Figure 3b. In addition, as shown in Figure 3c, although R also affects the surface potential, when 40% change based on R = 10 nm, only a slight change in the surface potential is observed. Therefore, the effects of tox and tfe are more important than R when designing the NC GAA-FET. Lastly, Figure 3d shows the effect of . The surface potential increases as increases, but if is smaller than a certain value, we can observe that small changes occur. These surface potential characteristics directly affect the channel current characteristics shown in Figures 4-7. In Figures 4-7, symbols are the results of applying the complicated current-voltage model from the surface potential by the numerical analysis method proposed in the previous work [25], and the line shows the regionalbased current-voltage model proposed in this work. As can be seen in Figures 4-7, it can be seen that the proposed model in the entire operating regions of the NC GAA-FET describes the complicated current-voltage model well. Figure 4a,b show the current-voltage characteristics in low drain bias (linear region) and high drain bias (saturation region) under various tfe conditions, respectively.
As with the surface potential characteristic, it can be seen that the sub-threshold swing is improved due to the voltage amplification characteristic when it is increased up to tfe = 8 nm. Therefore, lower off current and improved operating speed can be expected at the same power supply voltage (VDD). This can be clearly confirmed by comparing current-voltage behaviors of tfe = 0 nm (GAA FET characteristics without ferroelectric layer) and tfe = 8 nm. Figure 5 shows the current-voltage characteristic when tfe is fixed and tox is increased from 1 nm (a reference state well matched with a ferroelectric layer). As tox becomes thicker, as shown in Figure 3b, the voltage amplification effect due to the NC characteristic and the current characteristic decrease due to the increase in effective oxide thickness are observed. Figure 6 shows the current-voltage characteristics when tfe and tox are fixed with the voltage amplification optimized and R increased. As R increases (decreases), there is no significant change in surface potential, as shown in Figure 3c, but the current increases (decreases) due to the effect of increasing (decreasing) the total channel width (2πR). Figure 7 shows the current-voltage characteristics when tfe, tox, and R are fixed and is increased. As increases (decreases) the current increases (decreases) at low gate-to-source voltage and decreases (increases) at high gate-to-source voltage. Figure 8 is the result of comparing the model proposed in this paper with the model proposed in the previous paper of [25]. The previous result is a I-V model formula applicable to all operating regions based on surface potential calculation, and the proposed model has a complex form without considering the interface trap. On the other hand, in this work, the surface potential is calculated by considering the interface trap, and a simplified current equation is proposed according to the operating region, and an integrated model is developed by using a smoothing function. Therefore, I-V characteristics due to variations in tfe, tox, and R without interface traps can be compared with the previous results of [25]. However, the I-V characteristics according to the variation of the interface trap cannot be compared with the previous results of [25]. As shown in Figure 8, it was confirmed that the comparison result had an error of about 4-6% from that of the previous results of [25] according to the variation of various device geometries, and the computational efficiency was improved by about 13-24%. Figures 9 and 10 are the results of analyzing transconductance (gm) and transconductance generation factor (TGF) using the developed model by changing various geometry (tox, tfe, and R) and trap density (Net) characteristics of NC GAA-FET. It was confirmed that the developed model can predict the first-order differential characteristics through the gm simulation results shown in Figure  9. TGF emphasizes how effectively the drain current is used to achieve better transconductance, and the variation of TGF with VGS is shown in Figure 10. When VGS increases, the TGF characteristics decrease near the threshold voltage, then increase rapidly, and then decrease monotonically in the strong inversion region.

Conclusions
In this work, we proposed a method to obtain the surface potential and an analytical current-voltage model of NC GAA-FET. The proposed model considers GAA cylindrical coordinates, negative capacitive effect, and interface trap at the same time. It is a channel potential-based model that calculates the surface potential between the silicon channel and the intermediate insulator. Using the obtained channel potentials and the operation regional approach, a useful and simple drain current-voltage model equation is derived by taking the appropriate approximation in each transistor's operating region (linear, saturation, and sub-threshold regions). The proposed model shows high consistency when compared with the previous comprehensive model. In addition, the electrical properties of NC GAA-FET were investigated by varying key device parameters such as ferroelectric thickness, intermediate insulator thickness, silicon channel radius, and interface trap density per unit surface.