Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

: The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced ﬁnite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of ﬁnite DC gain on ultra-low voltage ∆Σ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ∆Σ modulator with reduced ﬁnite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and ﬂicker noise reduction; it also makes use of an ampliﬁer that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 µ m CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence TM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.


Introduction
Recent developments in the field of Internet of Things (IoT) applications have encouraged the research for systems that are capable of working with very low supply voltages consuming very little power [1][2][3]. The energy harvesting scenario is undoubtedly among the most interesting ones: It involves devices that are capable of gathering energy from the surrounding environment. The energy sources could be thermal jumps, radiations, vibrations, and biochemical reactions, just to mention a few. Among the most captivating harvesters we may find are biofuel cells, which can behave at the same time as an energy source, with power densities up to 1 mW/cm 2 , and a self-powered physiochemical sensor [4,5]. However, biofuel cells typically provide supply voltages in the range of 0.3-0.5 V. A DC-DC converter may be useful to enhance the supply voltage for the electronic interface, thus mitigating the design effort. Nevertheless, it does not represent the optimal choice in every scenario: The main reasons are the area occupied by the inductors in inductive boost converters or, alternatively, the limited efficiency of switched capacitor converters [6], besides the generation of a potential non-compatible with the human body [7]. Therefore,

Non-Idealities in ULV ∆Σ Modulators
Ultra-low voltage operation imposes severe limitations on the design of analog circuits. With the typical values of MOSFET threshold voltages Vth, working with supply voltages as low as a few hundred millivolts makes weak inversion and subthreshold region unavoidable. In these operating regions, MOSFETs show very low transition frequencies, despite the optimum current efficiency (g m /I D ) [30]. As a consequence, design of ULV amplifiers with target specifications of both bandwidth and DC gain may be very complex. In this scenario, the use of single-stage amplifiers in SC circuits (as the SC integrators in ∆Σ modulators) results in low accuracy, due to the low-voltage headroom that is not compatible with cascoded stages and gain boosting techniques, thus preventing to reach sufficiently high DC gain. On the other hand, multi-stage amplifiers represent a very popular choice due to the relaxation of DC gain requirements on each single stage [31]. Nevertheless, they require compensation networks [32] and higher power consumption, which in typical SC circuits are not justified by the need to drive large resistive loads.
In SC ∆Σ modulators, the DC gain may limit the converter accuracy and resolution through gain error, dead-zones, and degradation of the noise shaping function of the modulator. With conventional supply voltages, the DC gain of the integrators (tied to the amplifier DC gain) is generally high enough to make these adverse effects secondary. Conversely, in ultra-low voltage operating conditions, integrator gains may drop to just a few tens, making finite gain effects a real concern. For this reason, it is mandatory to estimate the required DC gain by means of preliminary behavioral simulations. Many works in the literature deal with high-level modeling of ∆Σ modulators, trying to describe as accurately as possible the non-idealities that most affect the bottom-level design [33][34][35][36]. In this section, we will describe some results closely related with the ULV design space, in particular concentrating on the effects of amplifier DC gain on the modulator performances.
A linearized model of a 2nd order Cascade of Integrator FeedBack (CIFB) modulator with no feedforward paths is depicted in Figure 1, where a 1 , a 2 , b 1 , and c 1 represent the coefficients of the specific modulator topology. V o1 and V o2 represent the state variables of the ∆Σ modulator, i.e., the output of the Discrete-Time (DT) integrators. V n1 and V n2 represent the referred-to-input noise and offset voltages of the two integrators, while V nq represents the quantization noise introduced by the single-bit ADC present in the modulator loop, here replaced by a constant gain k. DT integrators are modeled with their z-domain transfer functions, following the approach presented in [37], including the gain error (λ) and the phase error (p) of the integrator due to amplifier finite DC gain, respectively, evaluated for a common architecture of parasitic-insensitive SC integrator [38]: where A 1 and A 2 represent the finite DC gain of the amplifier employed in the first and the second SC integrator, respectively. An ad hoc discrete-time simulator of a 2nd order ∆Σ modulator was realized with the NumPy module for numerical computing of the Python language and used to evaluate the gain error, the dead-zone amplitude, and the increment of quantization noise due to the finite DC gain of the two integrators. DC performances have been evaluated by averaging the output bitstream over a large number of clock cycles such that the obtained resolution is finer than the DC errors that we want to estimate.

Gain Error
Among the well-known issues related to finite DC gain, gain error in ∆Σ ADCs has never been investigated, to the best of our knowledge. ∆Σ ADCs owe most of their popularity to audio and telecommunication applications, where gain errors do not represent a main concern. This may be the reason why a work that analyzes the gain error of a ∆Σ ADC has not been presented in the literature yet. However, different considerations must be argued for low-frequencies data acquisition systems. Whereas gain accuracy of instrumentation amplifiers represents a fundamental requirements, gain error of ∆Σ ADCs employed in sensor interfaces is often ignored, notwithstanding its contribute to the accuracy of the whole readout chain. For this reason, considering the relevance of this inaccuracy source in ultra-low voltage circuits, some insights on the gain error of ∆Σ converters are given in this Section.
Let us start considering the linearized block diagram depicted in Figure 1, from which the modulator Signal Transfer Function in the z domain STF(z) can be straightforwardly evaluated. We are interested in phenomena occurring in DC operations, therefore we need to consider the effects of the finite DC gain of the two integrators on the STF for z = 1. In particular, the gain error ε G is the difference between the STF(z = 1) for infinite gains A 1 and A 2 and the actual STF(z = 1). Considering that the former is unitary, we obtain the following relationship: In the final approximation given in Equation (2), we made the assumption that A 1 , A 2 1, which is reasonable even for inverter-based circuits. It is important to highlight that, by this approximation, ε G is a function of only A 1 and of coefficients a 2 and c 1 . Figure 2   The choice of these values is here briefly discussed. A first set (a 1 = b 1 = c 1 = 1, a 2 = 2) can be easily calculated from the linearized z-domain model of Figure 1 starting from the approximation of infinite DC gain (i.e., λ 1 = λ 2 = p 1 = p 2 = 1), in order to obtain a flat STF and a Noise Transfer Function (NTF) with two zeros at the origin. However, with this set of coefficients (from now on indicated as "Set 1"), the modulator state variables V o1 and V o2 are not bounded to remain within the full-scale range [−FS/2; FS/2] of the ADC, as shown in Figure 3. Since the full-scale range is typically equal or on the order of the supply voltage, this would imply large harmonic distortions due to the limited linear output ranges of the amplifiers employed in the integrators.
To overcome this issue, the modulator coefficients can be properly scaled in order to limit the state variables [39]. An example of scaled coefficients, here called "Set 2", is represented by a 1 = b 1 = a 2 = 0.047, c 1 = 0.493. It is worth mentioning that, working with low supply voltages and consequently low voltage headrooms, the attenuation introduced by the modulator coefficients becomes increasingly essential. The linear output range of an amplifier can be roughly considered to end at voltages where one of the output devices exits saturation region. Considering, for instance, a simple voltage amplifier as the CMOS inverter, the linear output range is limited by a saturation voltage V DSat from both rails. V DSat , which in strong inversion corresponds to the overdrive voltage (V GS − V th ), can be assumed around 4U t in weak inversion [40], where U t = kT/q is the equivalent thermal voltage, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. U t 25 mV at room temperature, then V DSat 100 mV in weak inversion. Outside the linear output range, the output resistance rapidly decreases and consequently also the DC gain, increasing also the distortion introduced by the amplifier. For supply voltages approaching 2V DSat , the linear output range becomes increasingly narrow, thus forcing a more aggressive scaling of the modulator coefficients. The Set 2 introduced before, for example, has been obtained in order to have a state variable swing equal to 15% of the full-scale range, as confirmed by the histograms in Figure 3. Actually, the coefficient sizing impacts not only on the converter linearity, but even on other parameters, for example on the gain error as shown in Figure 2. A lower ratio a 2 /c 1 as in the case of the scaled coefficients used here, involves a lower gain error, as described also by Equation (2). Nevertheless, in order to achieve a negligible gain error for an ADC with moderate resolution, thus avoiding expensive calibration procedures, a DC gain of the first integrator higher than 40-50 dB is still needed in even employing the second set of coefficients.

Dead-Zones
As is known, the integrator DC gain also affects the width of Dead-Zones (DZs). Differently from the gain error, DZs depend significantly on the DC gain of both integrators in a 2nd order ∆Σ modulator [39]. It is worth noting that, even in this case, the modulator coefficients have an influence on the DZs. Figure 4a shows the DC characteristics of the modulator with the first set of coefficients, for A 1 = 20 dB and different values of A 2 . For the curve with the lowest value of A 2 , dead-zones are visible for several DC inputs. In the inset, the scaling of the dead-zone amplitude for increasing value of A 2 is visible. Figure 4b shows the amplitude of the dead-zone located around the middle of the converter input range, which is the widest of all the other dead-zones present in the ADC characteristics. Two families of curves are plotted for the two sets of coefficients previously discussed. With Set 2, for the same values of A 1 and A 2 , the DZ is much smaller than in the case of Set 1. In both cases, however, the DZ is approximately inversely proportional to the product of A 1 and A 2 . For this reason, if large DC gains A 1 are employed for gain error issues, relative low A 2 gains are allowed without running into significant distortion due to DZs, especially employing the scaled coefficients.

Quantization Noise
A phase error in the integrators due to their limited DC gain causes the shifting of the two zeros in the NTF, thus increasing the overall quantization noise power. Figure 5 shows the SNDR of a 2nd order modulator, with a −2 dB FS input tone and an OverSampling Ratio (OSR) of 128 for the two different sets of coefficients already discussed.
Considering the curves obtained employing Set 1, the maximum values of SNDR are reached for values of DC gains A 1 and A 2 higher than 60 dB. Conversely, the scaled coefficients of Set 2 allows for achieving the same values, but with a lower DC gain of both integrators. It is worth mentioning that for the lowest values of A 1 and A 2 , especially with Set 1, dead-zones contribute to worsen the SNDR.
Even if the scaled coefficients guarantee better performances in terms of DC gain, dead-zones, and quantization noise suppression, mitigating the effect of finite DC gain of the amplifiers, it is not advisable to rely only on the values of the coefficients. Since the modulator coefficients are typically implemented as capacitive ratios in the SC integrators, too small values may be particularly detrimental for the modulator performances. When the converter resolution is limited by thermal noise, the absolute value of the input capacitors, responsible for the signal sampling, is sized according to kT/C noise specification. This is particularly critical in ULV scenarios, where the signal range is limited by the decreasing supply voltage and then, targetting the same resolution, the requirements on the converter noise becomes stricter. Consequently, small modulator coefficients enlarge the values of the feedback capacitors of the SC integrators, thus impacting on area and power consumption.

Low-Frequency Noise and Offset
Error sources V n1 and V n2 of Figure 1 affect the converter performances through two different NTFs, which can be evaluated analogously to the traditional NTF for the quantization noise V nq , considering the linearized block diagram of Figure 1 [41]. While offset and noise of the first integrator are not attenuated by the modulator response, the contributions of the second integrator are intrinsically high-pass filtered, thus giving negligible contributions in the signal bandwidth. For this reason, dynamic offset cancellation techniques, such as CHopper Stabilization (CHS) and correlated double sampling, are typically applied only to the first integrator. CHS represents a popular approach in ∆Σ modulators [12], thanks to the possibility of exploiting the digital low-pass decimator filter cascaded to the modulator, which also rejects to the offset ripple by proper choice of the chopping frequency and OSR. However, CHS modulation introduces several drawbacks, among which the worse settling time due to the parasitic capacitances of the demodulator switches. A typical solution is to place the chopper demodulator at non-dominant poles, as at the sources of the common-gate stage in the cascode structure [42]. In single-stage ULV and ULP amplifiers, where demodulation can be realized only at the output nodes, characterized by very high output resistance, CHS may have detrimental effects on the resulting DC gain of the amplifier. The SC integrator presented in [28] combines a CDS mechanism with a novel topology aimed at reducing the transfer function sensitivity to the amplifier DC gain, thus alleviating the above-mentioned issues related to ∆Σ modulators.

∆Σ Modulator Architecture
A block diagram of the modulator is depicted in Figure 6. It is a 2nd order, single-bit, inverter-based, fully-differential topology: There are two integrators (INT1 and INT2), a 1-bit ADC and a 1-bit Digital-to-Analog Converter (DAC). A second order architecture was chosen because it represents a good compromise among resolution increase and simplicity; in addition, it is intrinsically stable.
The modulator was designed for an ultra-low supply voltage V DD = 0.3 V. We will now analyze every single block in more detail.

Integrators
For the first integrator INT1, we adopted the topology of Figure 7 [28]. This architecture was already used in single-ended ULV ∆Σ modulators [9,29], but not yet in a FD implementation. Every switch is closed during the phase corresponding to the number near to it, while A 1 and A 2 are inverter-based FD amplifiers that will be described later.
Due to the symmetry of the circuit, it is possible to restrict the analysis to the lower half. The input capacitor C S samples V in+ and V f b+ , at the end of clock phases 2 and 1, respectively. A charge proportional to (V f b+ − V in+ ) flows into C T during phase 2. In the following, phase 1, the charge stored in C T is transferred to C F in the second stage, which behaves as an accumulator. This produces an increment of the output voltage V o1+ , so that an integration step is completed. Thanks to the C H contribution, which holds the voltage at the output of the first amplifier during phase 1 avoiding its reset, the charge transfer is a little sensitive to the DC gain of the first amplifier, as proposed in [43]. Considering also the second stage, the integrator produces an overall DC gain proportional to the cube of the gain of the single amplifier [28]. This aspect makes this SC topology particularly interesting for ULV ∆Σ modulators, thus relaxing the requirements on the DC gain of the employed amplifiers. Even single-stage inverter-like topologies with short channel lengths, with DC gain on the order of tens or lower, can be usefully exploited. Another advantage of the proposed integrator is the mentioned CDS technique, capable of rejecting the offset and reducing the flicker noise of both the amplifiers, improving low frequency accuracy and resolution.
As widely explained in the previous section, converter gain error depends almost exclusively on the first integrator. Moreover, since the dead-zone amplitudes and the zeros' shift in the NTF depend on the product of both A 1 and A 2 , the high-gain SC integrator has been employed only for the first integrator. Even noise and offset requirements for the second integrator are more relaxed, thus no dynamic offset cancellation techniques are needed. For all these reasons, it was possible to adopt a simpler topology for the second integrator, such as the parasitic-insensitive one [38] as depicted in Figure 8 in its FD version. Due to the different coefficients a 2 and c 1 implemented in the SC integrator, the number of input sampling capacitors is doubled. Finally, a simple diode-connected inverter (Inv 0 ) generates the constant bias voltage V inv depicted in Figure 7. This voltage is connected to C H during phase 2, in order to minimize the voltage excursion of C H bottom terminal in the transition between the two clock phases; it is also employed in the second integrator INT2 as a reference commonmode voltage.

ADC and DAC
The ADC and the DAC are 1-bit architectures, visible in Figure 9a,b, respectively. The 1-bit ADC internal to the modulator is simply a comparator. The input signal is pre-amplified by the input inverters, then the two inverters in a latch fashion exploit the positive feedback to take the decisions and regenerate the full-logical values for the output bitstream. The 1-bit DAC is simply the cascade of two inverters, where the first one acts as an inverting buffer and the second one provides the differential feedback voltages V f b+ and V f b− . V re f + and V re f − represent the differential reference voltages of the modulator. In this work, we opted for a ratiometric converter; in this way, V re f + and V re f − correspond to the supply voltage and ground, respectively.

Clock-Boosting Circuit
The switches of the circuit were mostly implemented as complementary pass-gates. The ULV domain is detrimental for the on-resistance of the MOSFETs in the triode region.
Increasing the aspect ratio to reduce the pass-gate on-resistances impacts the linearity performances of the circuit due to larger parasitic capacitances and charge injection issues. This design takes advantage from a clock-boosting technique capable of level-shifting both the high and the low levels of the clock signals driving the pass-gates. The circuit is visible in Figure 10 and a more detailed analysis is provided in [9].

Inverter-Based Amplifier
As already stated, the CMOS inverter may be used as a replacement of a voltage amplifier, as demonstrated in [9]. A FD version of the inverter-like amplifier requires that its output CM is stabilized, in order to prevent possible drifts and, consequently, a degradation of the output Differential-Mode (DM) range. A well-known solution is represented by the Nauta transconductor [44], but many others are available in the literature [45]. In this work, we adopted the amplifier recently proposed in [27], which has an increased output linear range with respect to other solutions. Its schematic view is shown in Figure 11. It was employed in both INT1 and INT2 for A 1 , A 2 , and A 3 . Inv 1 and Inv 2 are the inverters that process the input differential signal and are nominally identical. The other inverters Inv 3-9 are part of the stabilization loop. Again, for symmetry purposes, Inv 3 needs to match Inv 4 , and the same applies for Inv 5 and Inv 6 .
The CMSL was thoroughly analyzed in [27]; here, we will briefly summarize its principle of operation. Assuming ideal matching between the inverters, the loop does not affect the output DM, apart from an attenuation of the output resistance due to the presence of r o,5 and r o,6 . Inv 3 and Inv 4 produce a voltage V x that, as far as small signals are concerned, depends only on the output CM. Then, Inv 7 and Inv 5/6 close the loop. Even in the case of large output differential modes that are going to affect node V x , the feedback loop has a very small impact on the differential mode gain, since Inv 5/6 produce only common-mode effects. Inv 8 and Inv 9 , instead, act as load for Inv 3/4 and Inv 7 , respectively, in order to reduce the loop gain and avoid instability. This is needed because there are two loops formed by the cascade of three inverters, that are Inv 3-7-5 and Inv 4-7-6 . Figure 11. Schematic view of the inverter-based, fully-differential amplifier with the common-mode stabilization loop. Figure 12 shows the simulated Bode diagrams and the dc characteristics, with a supply voltage of 0.3 V and 0.15 V. The amplifier DC gain, already lower than 20 dB at V DD = 0.3 V, is around only 12 dB at V DD = 0.15 V. The Gain-BandWidth product (GBW) is also reduced by nearly a factor of 10, due to the exponential dependence of the quiescent current on V DD . The input-output differential characteristics at the two different supply voltages depicted in Figure 12 show that, besides the different gain around V id = 0 V, the linearity range of the amplifier is also obviously smaller at the lowest supply voltage.

Device Sizing
The modulator was designed with the 0.18-µm UMC CMOS process, with the device parameters shown in Table 1. Minimum channel lengths were adopted in order to improve speed performances. Body biasing for pMOS transistors of the inverter-like amplifiers was employed to enhance the maximum operating frequency; in particular, their bodies were connected to ground in order to reduce their threshold voltages and consequently moderate the request for high aspect ratios, typically larger than the nMOS to counteract the lower mobility. The same technique is not suitable for the nMOS devices, due to the absence of a p-well isolated from the substrate in the used technology. Thanks to the clock-boosting circuit, it was possible to assign a reasonably low width to the pass-gates, thus keeping under control charge injection issues, as well as the parasitic capacitances. As for the amplifier inverters Inv 1 and Inv 2 of Figure 11, instead, high aspect ratios are needed to reach a sufficient GBW. The other inverters Inv 3-9 were sized with the same strategy described in [27]. The diode-connected inverter Inv 0 , which provides the constant bias voltage V inv (close to V DD /2), is a scaled version of Inv 1,2 . The capacitors represent the main contribution to the estimated total area occupation of the modulator. We tried to keep them as small as possible, but with some limitations. The value of the sampling capacitors C S of the first integrator impact directly on the converter thermal noise. Another constraint is represented by the ratios C S /C F , C S2B /C F2 , and C S2A /C F2 , sized equal to b 1 = a 1 , a 2 , and c 1 , respectively. The coefficient set used in this design corresponds to the Set 2 discussed in Section 2. Their values are summarized in Table 2, resulting in an estimated area of 0.03 mm 2 , obtained by summing up the area occupied by all components, excluding the interconnections. Note that, in the technology used in this work, active devices can be placed below the Metal-Insulator-Metal (MIM) capacitors, which turn out to be the dominant factor. For this reason, the area estimation of the proposed ADC coincides with the capacitor area. C up and C down were not included in this area estimation, because they are not properly part of the modulator: The clock boosting circuit, in fact, may be shared among several blocks in a complete ULV data acquisition system. They are equal and were set to 1 pF.

Simulation Results and Discussion
The modulator was validated by means of electrical pre-layout simulations performed with Cadence Spectre TM ; in particular, transient noise simulations have been performed in order to also take into account electrical noise. In all simulations, the supply voltage and OSR were set to 0.3 V and 128, respectively, if not otherwise specified. The bitstream was processed by a VerilogA decimation filter to extract the output codes. We will call PI a modulator where, for the first integrator, a standard parasitic-insensitive architecture [38] is employed, with the amplifier, the sampling capacitor, and the capacitive ratios kept unchanged. The performances of the PI modulator will be compared with our proposed modulator, in order to highlight the benefits of the high-gain SC integrator depicted in Figure 7.
The spectrum of the output bitstream is plotted in Figure 13, where the input is a sinusoidal waveform with frequency 80 Hz and peak-to-peak (p-p) amplitude 450 mV. The clock frequency is set to 164 kHz. The SNR and SNDR resulted to be 76.7 dB and 73.1 dB, respectively. The Total Harmonic Distortion (THD), defined as the ratio between the distortion and the input signal power P THD /P IN , was about −75 dB. Excluding the clock-boosting circuit, the power consumption P D was equal to only 200.5 nW. The Schreier Figure of Merit (FoM) can be calculated as: which is among the best ones of ULV ∆Σ modulators. The DC transfer function was also extracted, in order to assess the gain error ε G : The results are visible in Figure 14. In the proposed architecture, ε G resulted to be 60 times lower than in the PI modulator, being equal to just 0.014%. The gain error improvement is consistent with the low DC gain sensitivity of the employed SC integrator, that is inversely proportional to the cube of the inverter-like amplifier DC gain. Furthermore, a temperature sweep was conducted and Figure 15 shows the results of this simulation. The dissipated power has an exponential dependence with the temperature, as expected by the weak inversion bias region of the inverter-based amplifiers. For the same reason, the amplifier bandwidth has a similar exponential behavior with temperature, explaining the worsening of the modulator dynamic performances at the lowest temperatures.
The Power Supply Rejection Ratio (PSRR) has been tested by superimposing a sinusoidal waveform with a 10-mV amplitude at different frequencies on the nominal supply voltage, not affecting the reference voltages V re f + and V re f − . Each point of the PSRR curve plotted in Figure 16 is evaluated by averaging over the PSRR values obtained from 200 Monte Carlo (MC) runs. Nominal simulations, in fact, are useless to estimate the actual PSRR of the circuit, due to the symmetry of the FD modulator. The error bars represent the minimum and the maximum PSRR values obtained from the 200 MC runs, for each ripple frequency. Moreover, considering the ratiometric operation of the ADC, we performed an additional test by feeding the input with a constant fraction (50%) of the supply voltage. In the ideal case, this should result in a constant output code (50% of full scale). The actual variation estimated by varying V DD across the interval 0.27-0.33 V was lower than 0.08% of full scale, proving that low sensitivity to supplies voltage variations.   MC simulations were also performed to evaluate the offset of the modulator. The offset mean value estimated over 200 MC runs is 16 µV, and the standard deviation σ is 0.47 mV. A histogram that describes this spread is depicted in Figure 17, where it is also shown how the offset changes for the PI modulator. In the latter case, the standard deviation increases by a factor greater than 5.7, demonstrating the effectiveness of the CDS technique intrinsically operated by the first integrator.  Table 3 summarizes the spread of the most relevant parameters over corner variations. Due to the sub-threshold operation of the devices, the amplifier bias current exhibits very large relative variations against process spread (mainly due to threshold voltage variations), strongly affecting the maximum operating frequency. For this reason, the frequencies at which the parameters in Table 3 have been determined are different for each corner. It is worth noting that, in the SS corner, the modulator dissipates less power but is capable of working with a sampling frequency around four times lower than in the typical corner. Analogous considerations explain the performances in the FF corner, while the condition of Slow NMOS/Fast PMOS represents the worst case in terms of distortion. The modulator was designed with the target supply voltage of 0.3 V, but it is interesting to check its performances with a much lower supply voltage. Figure 18 shows the output bitstream spectrum at V DD = 0.15 V, when the input is a sinusoidal waveform with frequency 1 Hz and p-p amplitude 112.5 mV. The clock frequency is set to 2 kHz. In these operating conditions, the modulator managed to achieve an SNR of 72.1 dB and an SNDR of 67.7 dB, with a power consumption of just 8.06 nW. The latter was reduced by nearly a factor of 25, but also the maximum clock frequency decreased (and thus the bandwidth). The resulting FoM was 158 dB, which is still a good value among ULV ∆Σ modulators. A temperature sweep was conducted also with V DD = 0.15 V and the results are shown in Figure 19. The modulator behaviour is similar to the one shown in Figure 15 up to 60 • C, where the dynamic performances start to drop due to the increase of the leakage currents, which disrupts correct operations of clock boosters. Concerning the effects of supply voltage variations, we fed the ADC input with a voltage equal to 50% V DD and varied V DD from 0.14 V to 0.16 V. The maximum variation of the output code across this V DD range was about 0.4% of full scale, revealing that reducing V DD to this extremely low value increases the sensitivity to supply voltage.
Investigating the effects of process variations showed that, at V DD = 0.15 V, it was impossible to find a sampling frequency where the ADC works properly, when SS, SNFP, and FNSP corners were considered. For these corners, correct operations of the modulator would require a further clock frequency reduction. Unfortunately, due to the leakage currents, the clock boosters are not capable of maintaining correct clock levels for such low frequencies. We focused on the worst case corner, the SS one, finding out that the lowest acceptable value of V DD was 0.18 V. In Figure 20, we show the sampling frequency for the four supply voltage points. For each supply voltage/sampling frequency combination, we indicated also the SNDR. We could not find a convincing reason for the increase of SNDR at lower supply voltages (and slower sampling frequencies).  In a similar way to the case of higher supply voltage, we performed MC simulations to evaluate the offset of the modulator at V DD = 0.15 V. The offset mean value estimated over 200 MC runs is −27.5 µV, and the standard deviation σ is 0.82 mV. Figure 21 shows the histogram of offset spread compared to the PI modulator, under the same supply voltage condition. As seen for V DD = 0.3 V, the proposed modulator shows better performances compared to the solution employing the traditional integrator topology.
In order to predict the possible advances that can be obtained by means of the proposed architecture in the field of ULV data converters, the simulation results obtained in this work have been compared in Table 4 with other state-of-the-art ULV ∆Σ ADCs. Table 4 includes previous works on ∆Σ modulators based on different approaches, namely DT, Continuous-Time (CT), Voltage-Controlled Oscillator (VCO)-based, and Current-Controlled Oscillator (ICO)-based.  From the comparison, it appears that the proposed architecture can produce values of the FoM very close to the best literature result [26], while being able to work with a considerably lower supply voltage. The total power consumption is also very close to the best figure [5] in Table 4, which makes the proposed modulator a promising solution for a large variety of energy harvesting applications and, in particular, for ultra-low voltage sources, as biofuel cells. It is worth highlighting that, while other works of Table 4 present measurement outcomes, our results are projections based on electrical simulations, aimed at assessing the modulator functionality and its robustness with respect to PVT variations.

Conclusions
Important modulator issues such as gain error, dead-zones, degradation of noiseshaping function, low-frequency noise, and offset introduce severe penalties on the overall performances of ∆Σ ADCs. By means of high-level simulations, we discussed the impact of these non-idealities especially when related to ultra-low voltage scenarios, focusing on the effect of the integrator finite DC gain and the modulator coefficients. In order to counteract some of the above mentioned issues, we designed a ∆Σ modulator capable of working with ultra-low supply voltages, which takes advantage of a high-DC gain switched-capacitor integrator and a fully-differential inverter-like amplifier, both recently proposed. In the nominal corner, it reached an SNDR of 73 dB, with a clock frequency of 164 kHz and a dissipated power of only 200.5 nW, at a supply voltage of 0.3 V: The Schreier's FoM reached 168.1 dB. Its gain error was also estimated and resulted in just 0.014%, while the offset had a standard deviation of 470 µV. The benefits introduced by the employed switchedcapacitor integrator topology with respect to a standard one were highlighted. Simulations over different process corners, temperatures, and supply voltage variations were used to estimate the spread of the main performance parameters, in particular showing some critical issues when coming to lower supply voltages, down to 0.15 V. The performances of this modulator make it extremely useful in the energy harvesting scenario, as, for example, in a biofuel cell-powered system.