Linear Active Disturbance Rejection Control Strategy with Known Disturbance Compensation for Voltage-Controlled Inverter

: When the linear active disturbance rejection control (LADRC) is applied for the voltage-controlled inverter, the discrete period and the measurement noise limits the observer bandwidth, which affects the anti-disturbance performance of the system. This results in a poor ability to deal with the output voltage ﬂuctuation under the load switch. In this paper, a novel LADRC strategy based on the known disturbance compensation is proposed for the voltage-controlled inverters. Firstly, the original LADRC scheme is designed. The dynamic performance and robustness of the system are analyzed by a root locus diagram, and the anti-disturbance ability is studied through amplitude-frequency characteristics. Then the partial model information and the load current are treated as the known disturbance and introduced to the linear extended state observer (LESO) to improve observation accuracy. The difference in anti-disturbance performance with the original scheme is compared and the stability of the LESO and LADRC is analyzed. Finally, the effectiveness of the proposed scheme is veriﬁed by the simulation and experimental results.


Introduction
Microgrids (MGs) can efficiently integrate the distributed energy resources (DERs) and improve the penetration of renewable energy sources (RES) [1]. RES is connected to the grid or load through an interface inverter, so the inverter control is critical [2,3]. In terms of the power converters operation, which is a vital part of MGs, interface inverters are generally categorized into three classes: grid-forming, grid-supporting, and grid-feeding inverter [4,5]. Among them, the grid-forming and grid-supporting inverters can act as the voltage-controlled inverter (VCI) and provide voltage and frequency support for the islanded MG, but they have different control strategies and purposes.
The grid-forming inverter usually operates with a fixed amplitude and frequency. In this case, the voltage control design focuses on rejecting the load disturbance and reducing voltage distortion under a nonlinear load. For grid-supporting applications, the voltage and the current loop are always regarded as the inner loop, and the outer power loop can control the power flow by adjusting the reference voltage of the inner voltage loop. Thus, the voltage tracking ability is important for the grid-supporting inverters [6].
The voltage control of the inverter plays a vital role in MG operation. Several control techniques have been implemented to achieve the high-performance voltage tracking of the inverters. The traditional dual-loop proportional-integral (PI) control with pulse width modulation (PWM) is widely applied because of the simple structure and easy implementation [7], but the performance of the PI controller is not always satisfactory under parameter perturbation. The dead-beat controller (DB) can realize a fast-transient response,

Modeling and Control of Inverters
A typical topology and control structure of the three-phase voltage-controlled MG inverter is shown in Figure 1. The application control layer realizes the droop control or VSG control, generates the amplitude reference, ref E , and frequency reference, ref ω , according to different control targets. The voltage control layer then tracks the instantaneous reference voltage rapidly in the SRF and adjusts the output impedance. The PWM algorithm is used to generate the driving signals of the switching devices. Fast and stable voltage control is the guarantee of reliable operation of the inverter. As the lower control layer, the inner voltage control should achieve a zero-dynamic voltage control [6]. This paper focuses on the inner voltage control; the application control layer is not discussed.
The direct current (DC) side is usually equipped with an energy storage system (ESS) or bus capacitors, and the voltage stabilization control algorithm is adopted to maintain a constant bus voltage,

Inverter Modelling in SRF
According to Figure 1, the mathematical model of the three-phase inverter with an LC filter is given in the SRF [3]: where d e , q The inverter model in the SRF is obtained by Laplace transformation of (1), as shown in Figure 2, where s represents the Laplace transform operator and the superscript * represents the reference value of the variable. Fast and stable voltage control is the guarantee of reliable operation of the inverter. As the lower control layer, the inner voltage control should achieve a zero-dynamic voltage control [6]. This paper focuses on the inner voltage control; the application control layer is not discussed.
The direct current (DC) side is usually equipped with an energy storage system (ESS) or bus capacitors, and the voltage stabilization control algorithm is adopted to maintain a constant bus voltage, V dc ; e a,b,c is the voltage of the inverter side; and u a,b,c and i oa,b,c are the output voltage and current of the inverter. The LC filter includes the filter inductor, L s , equivalent series resistance, R s , and the filter capacitor, C f ; i La,b,c and i Ca,b,c represent the current of the filter inductor and capacitor. L g and R g are line impedances; i * dq is the output of the voltage loop and e * dq is the output of the current loop; local loads are paralleled on the point of common coupling (PCC).

Inverter Modelling in SRF
According to Figure 1, the mathematical model of the three-phase inverter with an LC filter is given in the SRF [3]: where e d , e q , u d , and u q are the d-axis and q-axis components of e a,b,c and u a,b,c ; i Ld , i Lq , i od , and i oq are the d-axis and q-axis components of i La,b,c and i oa,b,c ; and ω 1 = 2π f 1 ( f 1 = 50 Hz in this study) is the fundamental frequency of the output voltage. The inverter model in the SRF is obtained by Laplace transformation of (1), as shown in Figure 2, where s represents the Laplace transform operator and the superscript * represents the reference value of the variable.  Figure 2. LADRC-based voltage control scheme.

Structure of LADRC-Based Voltage Loop
The voltage controller scheme based on LADRC is shown in Figure 2. A dual-loop control (DLC) structure is used. The inner current loop is utilized to control the inductor current with the PI-based regulator, and the outer voltage loop is used to control the capacitor voltage with the LADRC-based regulator.
To simplify the analysis, the delay caused by sampling and calculation is ignored.

Structure of LADRC-Based Voltage Loop
The voltage controller scheme based on LADRC is shown in Figure 2. A dual-loop control (DLC) structure is used. The inner current loop is utilized to control the inductor current with the PI-based regulator, and the outer voltage loop is used to control the capacitor voltage with the LADRC-based regulator.
To simplify the analysis, the delay caused by sampling and calculation is ignored. The PWM inverter gain K PWM = 1, so e * d,q ≈ e d,q . To improve the response speed, the current loop uses a proportional controller with a gain of K pi . The current loop regulator is: where e * d and e * q are the output of the current loop and are compared to the PWM carrier to generate the switching signal; i * Ld and i * Lq are the output of the voltage loop and the reference of the current loop.
The closed loop transfer function of the current loop is: Combined with Equations (1) and (3), the voltage loop is designed based on LADRC, as shown in Figure 2. Ignoring R s , the controlled object of the outer voltage loop is obtained: where, f d and f q are the defined disturbance of dq axis respectively, i oq .
From Figure 2 and Equation (5), the controlled object of the outer voltage loop is a second-order system, so two second-order LADRC controllers with third-order LESO need to be designed in the dq axis. The coupling between the dq axis can be regarded as a part of the total disturbance. Decoupling can be performed through feedforward compensation, so the controllers of the dq axis can be designed as separate channels with the same structure as LADRC. Simply take the d axis as an example.
An LADRC comprises LESO and LSEF. Wherein, the total disturbance is expanded into a new state. Then LESO is adopted to estimate the total disturbance and other state information. Finally, LSEF integrates all the state information obtained from LESO and reconstructs the system state equation.
From Equation (5), the state variables and output are defined as: Then, the following state-space equation can be derived: where u = i * Ld is the system input and b = K pi /(L s C f ) is the system control gain (CG). Considering the uncertainty of b, its estimated value b 0 is used, which is generally b 0 ≈ b; b 0 is often called the compensation factor (CF); f d denotes the total disturbance, which includes external disturbance, internal dynamics, and the estimation error between CG and CF [29].
By extending f d as a separate state, x 3 , of the system, and assuming that x 3 is differentiable with h = .
x 3 , then the system model can be represented in state space: The third-order LESO of the system can be designed as: where z 1 , z 2 , and z 3 are the state variables of LESO. β 1 , β 2 , and β 3 are the observer gain. By choosing the appropriate observer gain, the state variables of the system can be tracked quickly by the LESO in Equation (9), which is Through taking the Laplace transformation of Equation (9), we have: To achieve good disturbance rejection, the estimation variable is added into the control input; LSEF can be designed as: where k p and k d are gains of LSEF, u 0 is the intermediate variable, and r = u * d is the reference input.
If the LESO is reliable and the estimation error of CG is negligible, then z 1 → y , z 2 → . y , z 3 → f d , and b 0 = b. According to Equations (7) and (11), the closed-loop transfer function of the system can be deduced: Combining Equations (10) and (12), the characteristic Equation of LESO and the closed-loop transfer function are: According to the parameterization technique proposed [18], the eigenvalues of the LESO and the closed-loop transfer function can be located at −ω o and −ω c . Then, ω o is the bandwidth of the LESO and ω c is the bandwidth of the controller in LADRC. The tuning details are given by: With the above configuration, the dynamic performance of the system is dependent on only two parameters, which are the controller bandwidth, ω c , and the observer bandwidth, ω o . With appropriate bandwidth parameters, the system can track the reference input without overshoot.
The design process of the outer voltage loop controller based on LADRC in the d-axis is completed, including Equations (9), (11), and (14). The simplified structure of the original LADRC-based controller is shown in Figure 3. The controller in the q axis can be designed regarding the d axis and will not be described in detail.
Combining Equations (10) and (12), the characteristic Equation of LESO and the closed-loop transfer function are: According to the parameterization technique proposed [18], the eigenvalues of the LESO and the closed-loop transfer function can be located at ω is the bandwidth of the controller in LADRC. The tuning details are given by: With the above configuration, the dynamic performance of the system is dependent on only two parameters, which are the controller bandwidth, c ω , and the observer bandwidth, o ω . With appropriate bandwidth parameters, the system can track the reference input without overshoot.
The design process of the outer voltage loop controller based on LADRC in the d-axis is completed, including Equations (9), (11), and (14). The simplified structure of the original LADRC-based controller is shown in Figure 3. The controller in the q axis can be designed regarding the d axis and will not be described in detail. Figure 3. Structure of original LADRC-based voltage control scheme.

Influence of Observer Bandwidth and Compensation Factor
After designing the LADRC-based voltage loop completely, the next step is tuning the parameters to satisfy the requirements of stability and dynamic performance in the system; ω c is chosen by the requirements of dynamic performance and is generally not an adjustable parameter.
Affected by discrete period and measurement noise, there exists a trade-off between observation accuracy and noise rejection ability when choosing ω o . Furthermore, CG in the actual system is hard to obtain. It can be seen from Equation (7) that the selection of K pi and the perturbation of some parameters, such as inductance and capacitance, will also lead to deviation from the theoretical value, resulting in b 0 = b. Therefore, it is essential and important to study the influence of CF and ω o on system stability, anti-disturbance, and noise rejection ability.
According to Equations (10) and (14), and considering the system model (7) and the measurement noise n(t), the control structure of LADRC can be simplified, as shown in Figure 4. The control input of the system is: where R(s), Y(s), and N(s) are the Laplace transformation of r, y, and n, and Electronics 2021, 10, 1137 where ( ) R s , ( ) Y s , and ( ) N s are the Laplace transformation of r, y, and n, and 2 d d 2 , which represents the ratio of CF to CG. The output of the system is: From Equation (16), the system output consists of a tracking term, a disturbance term, and a measurement noise term; o ω , c ω , and ρ are related to the system's stability, dynamic performance, anti-disturbance, and noise rejection ability. In order to study the observer bandwidth constraints and the influence of CF, the amplitude-frequency characteristics (called Bode diagram) and root locus diagram are adopted respectively in this subsection.
The Bode diagram of the transfer function r Φ ( ) s with different c ω has been studied in [19][20][21][22]25,26], so they are not mentioned in this paper. The Bode diagrams of the transfer function  Let ρ = b 0 /b, which represents the ratio of CF to CG. The output of the system is: (16), the system output consists of a tracking term, a disturbance term, and a measurement noise term; ω o , ω c , and ρ are related to the system's stability, dynamic performance, anti-disturbance, and noise rejection ability. In order to study the observer bandwidth constraints and the influence of CF, the amplitude-frequency characteristics (called Bode diagram) and root locus diagram are adopted respectively in this subsection.
The Bode diagram of the transfer function Φ r (s) with different ω c has been studied in [19][20][21][22]25,26], so they are not mentioned in this paper. The Bode diagrams of the transfer function Φ d (s) and Φ n (s) are given in Figure 5, where ρ = 1 and ω c = 2000 rad/s. It can be seen that increasing ω o can reduce the low-frequency gain of Φ d (s), which can enhance the system's anti-disturbance ability. On the contrary, the high-frequency gain of Φ n (s) is increased, so the system becomes more sensitive to the measurement noise. Thus, there is a trade-off between anti-disturbance and noise rejection ability when choosing ω o .  Figure 6. The yellow area represents the unstable regions caused by the right-half-plane poles. The solid arrow represents the pole change when ρ increases from 0 to 1, while the dashed arrow represents the situation when ρ increases from 1 to infinity. In Equation (16), ρ does not affect the closed-loop zero position; only affecting the pole position, so a root locus diagram is adopted to analyze the dynamic performance and robustness of ρ. To obtain better observation accuracy, ω o is generally chosen between 2 ω c to 10 ω c [30]. Let ω o = 4ω c = 8000 rad/s; the root locus with different ρ is shown in Figure 6. The yellow area represents the unstable regions caused by the right-half-plane poles. The solid arrow represents the pole change when ρ increases from 0 to 1, while the dashed arrow represents the situation when ρ increases from 1 to infinity.
In Figure 6, it can be seen that: 1.
When ρ = 1, the poles are located at points A and C on the real axis, corresponding to ω o and ω c , and the system has no overshoot and a short settling time; 2.
When ρ changes from 0 to infinite, if ρ is smaller than 1.02 (point D), or greater than 5.24 (point E), the system will be unstable. The range of ρ that makes the system stable is listed in Table 1. As ω o increases, the stable range of ρ is expanded.

3.
When ρ increases from 0 to 1, poles enter the stable regions and approach point A and C. Poles λ 1 , λ 2 , and λ 3 are closer to the imaginary axis, so are marked as dominant poles. With ρ increasing, λ 1 and λ 2 gradually move away from the imaginary axis and approach the real axis, so the response time and overshoot decreases and the damping increases.

4.
When ρ increases from 1 to 1.02 (point B), λ 1 , λ 2 , and λ 3 are on the real axis and there is no overshoot in response. When they continue to increase, poles approach the imaginary axis, and the damping becomes smaller. This shows that the response becomes slower, and there is both overshoot and damped oscillation, then poles cross the negative half axis, and the system becomes unstable. In Equation (16), ρ does not affect the closed-loop zero position; only affecting the pole position, so a root locus diagram is adopted to analyze the dynamic performance and robustness of ρ . To obtain better observation accuracy, o ω is generally chosen between 2 c ω to 10 c ω [30]. Let o c 4 8000 ω ω = = rad/s; the root locus with different ρ is shown in Figure 6. The yellow area represents the unstable regions caused by the right-half-plane poles. The solid arrow represents the pole change when ρ increases from 0 to 1, while the dashed arrow represents the situation when ρ increases from 1 to infinity. In Figure 6, it can be seen that: 1. When 1 ρ = , the poles are located at points A and C on the real axis, corresponding to o ω and c ω , and the system has no overshoot and a short settling time; 2. When ρ changes from 0 to infinite, if ρ is smaller than 1.02 (point D), or greater than 5.24 (point E), the system will be unstable. The range of ρ that makes the system stable is listed in Table 1. As o ω increases, the stable range of ρ is expanded. 3. When ρ increases from 0 to 1, poles enter the stable regions and approach point A and C. Poles 1 λ , 2 λ , and 3 λ are closer to the imaginary axis, so are marked as dominant poles. With ρ increasing, 1 λ and 2 λ gradually move away from the

Known Disturbance Compensation Scheme
The observation accuracy of LESO directly affects the performance of LADRC. To enhance the anti-disturbance ability of the inverter system, a simple way is to increase the bandwidth of the LESO. Consequently, a better ability will be obtained to deal with the voltage fluctuation under the load switch. However, ω o is limited by the discrete period and measurement noise.

Design of Proposed Scheme
An improved LADRC scheme based on the known disturbance compensation is proposed in this paper, as shown in Figure 7. The known disturbance consists of model information and load current.
According to Equation (7), the d-axis component of the plant can be rewritten as: ..
where m 0 = K pi /L s and −m 0 . y is the model information; −b 0 i od represents load current disturbance. The remaining disturbances,

Design of Proposed Scheme
An improved LADRC scheme based on the known disturbance compensation is proposed in this paper, as shown in Figure 7. The known disturbance consists of model information and load current. According to Equation (7), the d-axis component of the plant can be rewritten as: The system model (8) can be rewritten as Figure 7. Proposed LADRC scheme based on known disturbance compensation.
The system model (8) can be rewritten as where h is the differential of g d . Different from the original LADRC, the system state matrix is changed because of introducing model information, and the LESO is designed as: where u = u − i od . Note that z 3 is the estimated value of g d instead of f d . Then, taking the Laplace transformation of Equation (19), we have: So the closed-loop poles of the observer (20) are at the roots of: After parameterization, the poles are allocated at the same position, −ω o . Then LESO gains are, respectively: The load current can be compensated by feedforward, then the LSEF is changed to:

Analysis of the Proposed Scheme
According to Equations (20) and (23), the control structure of LADRC can be simplified, as shown in Figure 8, in which f ld = f d − bi od . The control input of the system is: where Electronics So the output of the system is: As seen in Figure 9a, the proposed LADRC scheme has a smaller low-frequency gain than the original LADRC scheme, so the proposed LADRC has better anti-disturbance performance and a stronger ability to restraint input disturbance than the original LADRC in the low-frequency band. Similarly, the proposed LADRC has better noise rejection performance because of the lower high-frequency gain in Figure 9b.

Stability Analysis
Let ( )  (18) and (19), the estimation error is: So the output of the system is: where Φ r (s) = Figure 9a, the proposed LADRC scheme has a smaller low-frequency gain than the original LADRC scheme, so the proposed LADRC has better anti-disturbance performance and a stronger ability to restraint input disturbance than the original LADRC in the low-frequency band. Similarly, the proposed LADRC has better noise rejection performance because of the lower high-frequency gain in Figure 9b. So the output of the system is:

As seen in
As seen in Figure 9a, the proposed LADRC scheme has a smaller low-frequency gain than the original LADRC scheme, so the proposed LADRC has better anti-disturbance performance and a stronger ability to restraint input disturbance than the original LADRC in the low-frequency band. Similarly, the proposed LADRC has better noise rejection performance because of the lower high-frequency gain in Figure 9b.

Theorem 1.
Assuming that h is bounded, namely |h | ≤ M 1 (M 1 > 0), such that there exists a LESO that can make the estimation error boundary and e ≤ M 2 (M 2 > 0).
Proof. Choosing 0 < λ 1 < λ 2 < λ 3 to make: Then there exists a reversible real matrix T that makes: And ∀t > 0, · m ∞ is used in Equation (29), so: where δ is a constant. Solving Equation (26), the: Considering the compatibility of · m ∞ and · 2 in the complex field, then: This shows that the estimation error of LESO can converge to a small boundary without an accurate mathematical model. As the observer bandwidth increases, the boundary decreases, and the estimation accuracy improves.
From Figure 8 and Equations (22) and (24), the closed-loop transfer function of the system is: The Lienard-Chipard criterion can be applied to judge whether the system is stable or not. The necessary and sufficient condition for stability is that the coefficients of the characteristic equation and each odd (or even) order Hurwitz determinant are greater than zero separately. Therefore, the stability condition of the system can be simplified as: In Equations (22) and (33), β 1 , β 2 , β 3 , m 0 are related to ω o , and k p , k d are related to ω c . Thus, the stability of the system can be guaranteed by selecting an appropriate ω o and ω c according to the restriction conditions in Equation (34).

Load Current Estimator
By introducing load current information, the influence of load current disturbance can be decreased. Therefore, the voltage drops during the load switch can be reduced. Consequently, the anti-disturbance ability of inverters can be significantly improved. However, the load current sensors undoubtedly increase the cost. As an alternate method, a load current estimation method is proposed that does not require current sensors.
In practice, the derivation of capacitor voltage with a low-pass filter (LPF) is used to estimate the load current, but it needs the differential signals of the voltage. The observer, such as a disturbance observer [31] or sliding mode observer [32], is also an effective method to obtain the load current, but it needs to be designed separately, increasing the system complexity. In this paper, the LESO observation state is used to simplify the design of load current observation.
According to Equations (1) and (9), observation values of load currentî od (s) can be obtained by: where, i Ld can be obtained from current sensors; z 1d , z 1q , z 2d , and z 2q are the output of the LESO in Equation (20). From the analysis in reference [33], the state matrix of LESO in Equation (20) can be Hurwitz when the appropriate observer bandwidth is taken. Therefore, the estimation error can converge to zero in a finite time, T 1 > 0. That is z 1d → u d , z 1q → u q , z 2d → . u d , and z 2q → . u q . Hence, the load current can be estimated by (35). In addition, the estimated load current is introduced to LESO and subtracted in LESF. After simplification, the estimated load current can be regarded as perturbations outside the forward channel, as shown in Figure 8. Then the estimation error of the load current will be reflected in the total disturbance and does not affect the stability of the system.

Simulation and Experimental Verification
In the proposed scheme, the model information belongs to internal disturbance and cannot be changed independently, while the load disturbance belongs to external disturbance and can be controlled by increasing or decreasing the load. Thus the reference step simulation and experiment of capacitor voltage under no-load condition has been carried out to validate the feasibility of the model information compensation scheme. The voltage tracking capability is compared with the original LADRC scheme, in which the load current is 0, so only the model information compensation scheme works. During load switching, the load current dominates the total disturbance and the proportion of the model information disturbance is small. Thus the load switch simulation and experiment have been carried out to validate the feasibility of the load current compensation scheme, and the voltage drop is used to evaluate the ability to suppress the load disturbance.

Discretization of LESO
In simulation and experiment, the proposed scheme was discretized with the bilinear transformation method (BTM), and the discrete period equals the sampling period, T s . In the system model (18), let: So the LESO with the proposed scheme (19) can be rewritten as: For the convenience of digital implementation, only the LESO is discretized using BTM, and we have:  3 (39) So the observer gain L can be derived: Then the discrete form of LESO can be obtained by substituting Formula (40) into Formula (38). The discrete implementation of LSEF (23) is:

Simulation Results
The simulation model was first established through MATLAB/Simulink. Table 2 lists the key parameters of the inverter and controller in simulation. To verify the feasibility of the proposed scheme, the original LADRC (marked as OL) scheme, the only model information compensation (marked as MC) scheme, the only load current compensation (marked as LC) scheme, the proposed (MC and LC, marked as PS) scheme, and the estimated load current scheme with model information (marked as ES) were studied. The simulation process is as follows: 0-0.1 s; the reference voltage linearly increases from 0 to 60 V and remains 60 V until 0.1 s, then steps to 120 V at 0.185 s and remains 120 V until the end of the simulation. The resistive loads (20 Ω per phase) are added at 0.305 s. The deviation of 5 ms is to ensure that the reference change and load switch are at the approximately maximum of the A-phase voltage.
The simulation results of the OL, MC, LC, and PS schemes are shown in Figure 10. Under the no-load condition, the load current is 0, so the LC scheme did not work. Therefore, the OL and LC curves are approximately coincident, the same as theMC and PS curves. In Figure 10a, four schemes can track the reference voltage well, but the OL and LC schemes have obvious voltage overshoot (132.04 V) when the reference voltage steps at 0.185 s. The MC scheme can effectively improve the dynamic performance at the reference tracking, and the voltage overshoot is reduced to 123.18 V. The simulation process is as follows: 0-0.1 s; the reference voltage linearly increases from 0 to 60 V and remains 60 V until 0.1 s, then steps to 120 V at 0.185 s and remains 120 V until the end of the simulation. The resistive loads (20 Ω per phase) are added at 0.305 s. The deviation of 5 ms is to ensure that the reference change and load switch are at the approximately maximum of the A-phase voltage.
The simulation results of the OL, MC, LC, and PS schemes are shown in Figure 10. Under the no-load condition, the load current is 0, so the LC scheme did not work. Therefore, the OL and LC curves are approximately coincident, the same as theMC and PS curves. In Figure 10a, four schemes can track the reference voltage well, but the OL and LC schemes have obvious voltage overshoot (132.04 V) when the reference voltage steps at 0.185 s. The MC scheme can effectively improve the dynamic performance at the reference tracking, and the voltage overshoot is reduced to 123.18 V. During load switching, load current disturbance is dominant in the total disturbance, so the LC scheme has better anti-disturbance performance than the MC scheme, as shown in Figure 10b. The comparison of the voltage drop and settling time between different schemes is listed in Table 3. The MC scheme has little effect on the load switch. On the other hand, the LC scheme can effectively reduce voltage drops and settling time when the load switches. Therefore, the proposed scheme can well combine the advantages of the two schemes. The simulation results of the PS and ES schemes are shown in Figure 11. Both schemes can reduce voltage drop when loads switch. The voltage error between the ES and PS schemes is less than 6 V, and is less than 0.4 V at the steady-state. The d-axis load During load switching, load current disturbance is dominant in the total disturbance, so the LC scheme has better anti-disturbance performance than the MC scheme, as shown in Figure 10b. The comparison of the voltage drop and settling time between different schemes is listed in Table 3. The MC scheme has little effect on the load switch. On the other hand, the LC scheme can effectively reduce voltage drops and settling time when the load switches. Therefore, the proposed scheme can well combine the advantages of the two schemes. The simulation results of the PS and ES schemes are shown in Figure 11. Both schemes can reduce voltage drop when loads switch. The voltage error between the ES and PS schemes is less than 6 V, and is less than 0.4 V at the steady-state. The d-axis load current can be estimated in real time and stabilized in 2 ms, as shown in Figure 11b. The maximum estimation error is lower than 2.6 A when the loadis switched, and is less than 0.02 A at the steady-state. THD (%) values under different schemes in the simulation are listed in Table 4. Under no-load conditions, the MC, PS, and ES schemes can reduce the THD to 0.23% and 0.35%, while LC has little effects because there is no load current. Under full load conditions, although the voltage drop decreases because of the load current feedforward, the voltage THD in the steady-state increases because delays caused by sampling and filtering result in incomplete compensation of the load current. The THD values of the ES scheme are close to the PS scheme because of the small estimation error, as shown in Figure 11. current can be estimated in real time and stabilized in 2 ms, as shown in Figure 11b. The maximum estimation error is lower than 2.6 A when the loadis switched, and is less than 0.02 A at the steady-state.  Table 4. Under no-load conditions, the MC, PS, and ES schemes can reduce the THD to 0.23% and 0.35%, while LC has little effects because there is no load current. Under full load conditions, although the voltage drop decreases because of the load current feedforward, the voltage THD in the steady-state increases because delays caused by sampling and filtering result in incomplete compensation of the load current. The THD values of the ES scheme are close to the PS scheme because of the small estimation error, as shown in Figure 11.

Experiment Results
The experimental platform is shown in Figure 12. It is comprised of an LC-filtered three-phase inverter, the DC power supply, and linear load. The DC bus is replaced by a 300 V/20 A DC power supply. A TI LaunchPad 28379D board was used to implement the control algorithm. The switching frequency of the IGBT module is set to 10 kHz, and the dead time is 2.6 μs. The sampling period is 100 μs. TBC10SYW and TBV10/25A are applied to measure the three-phase current and voltage. A Tektronix A622 current probe is used to measure the A-phase load current. In the actual system, the measurement noise is worse, so o 7854 ω = rad/s and c 2094 ω = rad/s, less than the values in the simulation.
Other parameters are listed in Table 2.

Experiment Results
The experimental platform is shown in Figure 12. It is comprised of an LC-filtered three-phase inverter, the DC power supply, and linear load. The DC bus is replaced by a 300 V/20 A DC power supply. A TI LaunchPad 28379D board was used to implement the control algorithm. The switching frequency of the IGBT module is set to 10 kHz, and the dead time is 2.6 µs. The sampling period is 100 µs. TBC10SYW and TBV10/25A are applied to measure the three-phase current and voltage. A Tektronix A622 current probe is used to measure the A-phase load current. In the actual system, the measurement noise is worse, so ω o = 7854 rad/s and ω c = 2094 rad/s, less than the values in the simulation. Other parameters are listed in Table 2.  Figure 13 shows the experimental results of the capacitor voltage with different schemes under no load, in which the amplitude of the reference voltage rises to 120 V from 60 V. The load current is 0, so only MC works. LC and ES schemes are not presented here. The system can remain stable before and after the reference steps with both schemes.  Figure 13 shows the experimental results of the capacitor voltage with different schemes under no load, in which the amplitude of the reference voltage rises to 120 V from 60 V. The load current is 0, so only MC works. LC and ES schemes are not presented here. The system can remain stable before and after the reference steps with both schemes.  Figure 13 shows the experimental results of the capacitor voltage with different schemes under no load, in which the amplitude of the reference voltage rises to 120 V from 60 V. The load current is 0, so only MC works. LC and ES schemes are not presented here. The system can remain stable before and after the reference steps with both schemes. As shown in Figure 14, the voltage of the OL and PS schemes track well the reference voltage, 60 V and 120 V, and can recover within 4 ms, but the overshoot of the OL scheme is up to 134 V, which is greater than the PS scheme. The amplitude of the capacitor voltage is calculated from represents the i-phase voltage sampled by the oscilloscope.  As shown in Figure 14, the voltage of the OL and PS schemes track well the reference voltage, 60 V and 120 V, and can recover within 4 ms, but the overshoot of the OL scheme is up to 134 V, which is greater than the PS scheme. The amplitude of the capacitor voltage is calculated from −4(   Figure 13 shows the experimental results of the capacitor voltage with different schemes under no load, in which the amplitude of the reference voltage rises to 120 V from 60 V. The load current is 0, so only MC works. LC and ES schemes are not presented here. The system can remain stable before and after the reference steps with both schemes. As shown in Figure 14, the voltage of the OL and PS schemes track well the reference voltage, 60 V and 120 V, and can recover within 4 ms, but the overshoot of the OL scheme is up to 134 V, which is greater than the PS scheme. The amplitude of the capacitor voltage is calculated from represents the i-phase voltage sampled by the oscilloscope.  In the case of load switching (adding 20 Ω resistor per phase), the load current changes dramatically, so the instantaneous total disturbance is too large. In order to avoid the system divergence caused by control saturation, a saturation module is added after z 2 and z 3 . The experimental results of the capacitor voltage and the A-phase load current are shown in Figure 15. Due to a lack of known disturbance compensation, the observation accuracy is limited. After adding the load, the voltage cannot be recovered within one period with the OL scheme, and the voltage drops to 74.4 V when the load switches. With the PS scheme, the voltage drops to 89.6 V and can recover within 4 ms with no overshoot. Similar to the PS scheme, the voltage drops to 90.2 V and recovers within 10 ms with the ES scheme, which is slower than the PS scheme.
In the experiment, THD (%) values under different schemes are calculated by the FFT Analysis Tool in Matlab/Simulink, and they are listed in Table 5. Under no-load conditions, the PS scheme can reduce the THD to 0.85% and 0.89% with model information compensation. Similar to the simulation results, the output voltage quality was worse with the PS scheme, and the THD was 1.86%, higher than the OL scheme, 1.67%. Additionally, the voltage THD under full load conditions was 1.67%, higher than the no-load conditions (1.25% and 1.38%); this may be caused by control saturation because of the slower response, as shown in Figure 15a. Under full-load conditions, the THD value with the ES scheme is 1.96%, which is 0.1% different from the PS scheme, and the difference under no-load conditions is 0.05%. So the estimation error of the load current affects the voltage quality. z and 3 z . The experimental results of the capacitor voltage and the A-phase load current are shown in Figure 15. Due to a lack of known disturbance compensation, the observation accuracy is limited. After adding the load, the voltage cannot be recovered within one period with the OL scheme, and the voltage drops to 74.4 V when the load switches. With the PS scheme, the voltage drops to 89.6 V and can recover within 4 ms with no overshoot. Similar to the PS scheme, the voltage drops to 90.2 V and recovers within 10 ms with the ES scheme, which is slower than the PS scheme. In the experiment, THD (%) values under different schemes are calculated by the FFT Analysis Tool in Matlab/Simulink, and they are listed in Table 5. Under no-load conditions, the PS scheme can reduce the THD to 0.85% and 0.89% with model information compensation. Similar to the simulation results, the output voltage quality was worse with the PS scheme, and the THD was 1.86%, higher than the OL scheme, 1.67%. Additionally, the voltage THD under full load conditions was 1.67%, higher than the no-load conditions (1.25% and 1.38%); this may be caused by control saturation because of the slower response, as shown in Figure 15a. Under full-load conditions, the THD value with the ES scheme is 1.96%, which is 0.1% different from the PS scheme, and the difference under no-load conditions is 0.05%. So the estimation error of the load current affects the voltage quality.

Conclusions
A LADRC-based voltage control strategy with known disturbance compensation is proposed for voltage-controlled inverters based on a dual-loop structure. The compromise between the anti-disturbance and noise rejection ability is studied. The constraint of the observer bandwidth affects the anti-disturbance ability, so the model information and load current are regarded as the known disturbance and introduced into the LESO to further enhance the anti-disturbance ability. The comparison between original and proposed LADRC schemes is then provided by the frequency domain response. Furthermore, the stability of the proposed LESO and LADRC is analyzed. For saving the current sensors, an estimated load current feedforward scheme is also mentioned. The theoretical analysis, simulation, and experimental results show that: (1) The model information can effectively improve the system's dynamic performance. The overshoot and settling time of the voltage dynamics is reduced, the same as THD values. (2) The load current compensation can reduce the voltage drop under the load switch and enhance the anti-disturbance ability. However, the voltage THD is increased due to the delays introduced by sampling and filtering. Moreover, as an alternate method, the estimated load current feedforward scheme does not need load current sensors and has a similar dynamic performance and ability of voltage drop suppression as the proposed scheme.
Power quality issues, such as harmonics and unbalanced voltage, have not been discussed in this paper. In future work, the LADRC strategy will be designed for positivesequence, negative-sequence, and selected harmonic voltage controller to improve power quality. Furthermore, the compensation factor will be designed adaptively according to the voltage drop or estimation error to further enhance the anti-disturbance ability of the system.

Conflicts of Interest:
The authors declare no conflict of interest.