A High Efficiency Linear Power Supply with Pure Sine Wave for High Voltage Test

The input part of the high-voltage test power supply is usually composed of switching devices; however, the pulse-type periodic interference caused by the switching devices makes the monitoring of the test power supply partial discharge more difficult. Therefore, this paper proposes a high-efficiency and distortion-free linear power supply based on piecewise-linearization with all N-type transistor. Under the same DC input, multiple power transistors are connected to different taps of the same transformer. By controlling the period of linear conduction of each power transistor in turn, we ensure that the power transistor works on the linear side (biased towards saturation) to reduce its conduction voltage drop and the output realizes sinusoidal piecewise linearization, so that the converter can greatly improve the system efficiency. After that, from the perspective of the lowest sum of the transistor loss, an optimization method for the design of the multi-winding transformer ratio at each stage is proposed. Finally, a power supply prototype based on four-piece linear converter with an output voltage of 220 V was built. The experimental efficiency reaches 87.03%, and, additionally, if the linear amplification is divided into more sections, the efficiency can be further improved.


Introduction
The construction of Ultra-High Voltage (UHV) power grids is inseparable from UHV electrical equipment, which must undergo various insulation detection tests before being put into operation in the grid system. To successfully carry out various high-voltage tests of electrical equipment, high-voltage test power supplies are required to supply high-voltage. Determining the insulation status of the test power supply and accurately pre-warning the insulation failure can effectively improve the safety and stability of its operation, and it is necessary to carry out the partial discharge test [1].
One of the types of high-voltage test power supplies is power transformers, among which step-up transformers are often used as intermediate transformers to match the voltage of the power supply and the voltage required for the test. At present, power electronic switching devices are widely used to generate high-power sine waves as the energy source input of the high-voltage test power supply, but at the same time, the use of switching devices will also increase the difficulty of measuring the partial discharge of the transformer. When the switching device is turned on or off, it will emit a pulse interference signal. If the interference cannot be effectively suppressed, this pulse-type periodic interference makes the signal-to-noise ratio and sensitivity of the online detection low, so it is impossible to effectively and accurately perform real-time partial discharge online monitoring. The commonly used methods of partial discharge interference suppression can improve the accuracy of measurement to a certain extent, but if the pulse-shaped periodic interference caused by switching devices is fundamentally avoided, the problem of difficult partial discharge detection can be solved. There is no pulse signal when the input power Linear amplification workspace · · · · · · · · · · This paper presents a high-efficiency and distortion-free converter based on wise-linearization with all N-type transistors (HDCPLN), which can be applied to power supply. The linear voltage drop of the novel topology can also be reduced greatest extent without switching the converter part, and the power conversion eff can be improved. There is no need for the structure of multiple triodes in paralle relatively simple structure can achieve greater power output. Based on a single-st ear converter topology with all-N transistors, multiple power transistors are conne different taps of the same transformer. By controlling the linear conduction angle power transistor in turn, the conduction transistor voltage drop is reduced, so t converter can greatly improve the system efficiency. In addition, the third part of per proposes an optimization method for the design of the multi-winding trans ratio at each stage from the perspective of the lowest sum of the transistor loss. F the experimental results of a power supply prototype based on the principle of fou linear converter are given.

Single-Stage Linear Power Converter Topology
A single-stage linear converter topology with all-N transistor is shown in Fi When the control signal vs. is a standard sine, T1 and T ' 1 work complementarily an metrically. Tf and T ' f are used for energy feedback, and their control signals are th as T1 and T ' 1 . The difference from the traditional Class-B power amplifier is that it ered by the same DC power supply and is controlled by two voltage signals with difference of 180°. The circuit uses the same type of power transistor and integra primary output through a double winding transformer, thereby the secondary si puts a complete positive and negative half-cycle voltage waveform. This paper presents a high-efficiency and distortion-free converter based on piecewiselinearization with all N-type transistors (HDCPLN), which can be applied to a linear power supply. The linear voltage drop of the novel topology can also be reduced to the greatest extent without switching the converter part, and the power conversion efficiency can be improved. There is no need for the structure of multiple triodes in parallel, and a relatively simple structure can achieve greater power output. Based on a single-stage linear converter topology with all-N transistors, multiple power transistors are connected to different taps of the same transformer. By controlling the linear conduction angle of each power transistor in turn, the conduction transistor voltage drop is reduced, so that the converter can greatly improve the system efficiency. In addition, the third part of this paper proposes an optimization method for the design of the multi-winding transformer ratio at each stage from the perspective of the lowest sum of the transistor loss. Finally, the experimental results of a power supply prototype based on the principle of four-piece linear converter are given.

Single-Stage Linear Power Converter Topology
A single-stage linear converter topology with all-N transistor is shown in Figure 2. When the control signal vs. is a standard sine, T 1 and T 1 work complementarily and symmetrically. T f and T f are used for energy feedback, and their control signals are the same as T 1 and T 1 . The difference from the traditional Class-B power amplifier is that it is powered by the same DC power supply and is controlled by two voltage signals with a phase difference of 180 • . The circuit uses the same type of power transistor and integrates the primary output through a double winding transformer, thereby the secondary side outputs a complete positive and negative half-cycle voltage waveform. The converter has four working phases in a cycle, and the conduction of the power transistor are shown in Table 1. Figure 3 shows the control signals and system output waveforms. The solid lines of vs. and −vs are actual T1 and T ' 1 driving waveforms, and the dotted lines are actual Tf and T ' f driving waveforms.

Working Principle
When the driving signals vs, −vs are sine waves with equal amplitude and 180° phase difference, and the circuit works in a stable state, it is known from Table 1 that the output of the power converter has 4 working phases. The current path in each working stage is shown in Figure 4. The converter has four working phases in a cycle, and the conduction of the power transistor are shown in Table 1. Figure 3 shows the control signals and system output waveforms. The solid lines of vs. and −v s are actual T 1 and T 1 driving waveforms, and the dotted lines are actual T f and T f driving waveforms.  The converter has four working phases in a cycle, and the conduction of the power transistor are shown in Table 1. Figure 3 shows the control signals and system output waveforms. The solid lines of vs. and −vs are actual T1 and T

Working Principle
When the driving signals vs, −vs are sine waves with equal amplitude and 180° phase difference, and the circuit works in a stable state, it is known from Table 1 that the output of the power converter has 4 working phases. The current path in each working stage is shown in Figure 4.

Working Principle
When the driving signals v s , −v s are sine waves with equal amplitude and 180 • phase difference, and the circuit works in a stable state, it is known from Table 1 that the output of the power converter has 4 working phases. The current path in each working stage is shown in Figure 4.  (1) When the load voltage is positive and the current is negative, only the T ' f works, and the current path is shown in Figure 4a. Load voltage commutates, and T ' 1 without driving signal is in the off state. The input signal −vs is connected to the gate of T ' f , and T ' f is linearly conductive. T1 and Tf are cut off without a current path. The negative half-cycle waveform of -vs when the load current is negative is obtained without distortion on the primary winding Np2, All the "·" are positive, and the load RL bears positive voltage (Ns/Np2)·−vs through the transformer coupling.
(2) When the load voltage is positive and the current is positive, only the T1 works, and the current path is shown in Figure 4b. Load current commutes, and the driving signals vs. is greater than zero potential and connected to the gate of T1. Tf is in the off state due to the opposite voltage and T1 is linearly conductive. T ' 1 and T ' f are cut off without a current path. The positive half-cycle waveform of −vs when the load current is positive is obtained without distortion on the primary winding Np1, All the "·" are positive, and the load RL bears positive voltage (Ns/Np1)·vs through the transformer coupling.
(3) When the load voltage is negative and the current is positive, only the Tf works, and the current path is shown in Figure 4c. Load voltage commutes, and T1 without driving signal is in the off state. The input signal vs. is connected to the gate of Tf, and Tf is linearly conductive. T ' 1 and T ' f are cut off without a current path. The negative halfcycle waveform of vs. when the load current is positive is obtained without distortion on the primary winding Np2, All the "·" are negative, and the load RL bears negative voltage (Ns/Np1)·vs through the transformer coupling. (1) When the load voltage is positive and the current is negative, only the T f works, and the current path is shown in Figure 4a. Load voltage commutates, and T 1 without driving signal is in the off state. The input signal −v s is connected to the gate of T f , and T f is linearly conductive. T 1 and T f are cut off without a current path. The negative half-cycle waveform of −v s when the load current is negative is obtained without distortion on the primary winding N p2 , All the "·" are positive, and the load R L bears positive voltage (N s /N p2 )·−v s through the transformer coupling. (2) When the load voltage is positive and the current is positive, only the T 1 works, and the current path is shown in Figure 4b. Load current commutes, and the driving signals vs. is greater than zero potential and connected to the gate of T 1 . T f is in the off state due to the opposite voltage and T 1 is linearly conductive. T 1 and T f are cut off without a current path. The positive half-cycle waveform of −v s when the load current is positive is obtained without distortion on the primary winding N p1 , All the "·" are positive, and the load R L bears positive voltage (N s /N p1 )·v s through the transformer coupling. (3) When the load voltage is negative and the current is positive, only the T f works, and the current path is shown in Figure 4c. Load voltage commutes, and T 1 without driving signal is in the off state. The input signal vs. is connected to the gate of T f , and T f is linearly conductive. T 1 and T f are cut off without a current path. The negative half-cycle waveform of vs. when the load current is positive is obtained without distortion on the primary winding N p2 , All the "·" are negative, and the load R L bears negative voltage (N s /N p1 )·v s through the transformer coupling.
(4) When the load voltage is negative and the current is negative, only the T 1 works, and the current path is shown in Figure 4d. Load current commutes, and the driving signals −v s is greater than zero potential and connected to the gate of T 1 . T f is in the off state due to the opposite voltage and T 1 is linearly conductive. T 1 and T f are cut off without a current path. The positive half-cycle waveform of −v s when the load current is negative is obtained without distortion on the primary winding N p2 , All the "·" are positive, and the load R L bears negative voltage (N s /N p2 )·−v s through the transformer coupling.
In order to obtain the expected output and avoid the occurrence of bias magnetism, generally take N p1 = N p2 = N p , and the output voltage The transformer is amplitude-second balance throughout the process, and the system reaches a stable state. However, due to the inherent shortcomings of push-pull linear power amplification, the ideal efficiency of A single-stage linear converter with all-N transistor is only 78.5% [17], which limits its application range.

Reasons for Improving HDCPLN Efficiency
Although the single-stage converter structure proposed above avoids the P-type transistor, it still belongs to the traditional class-B power amplifier in essence and the efficiency is still very low. Therefore, the idea of piecewise linearization is proposed in this paper. At each stage, different power transistors are controlled to be turned on linearly, so that the working transistor withstands very low voltage drop, which can greatly reduce losses.
On the basis of the structure proposed in the previous section, a multistage converter topology is proposed to achieve an all-N transistor high-efficiency converter. The two-stage circuit structure is taken as an example to explain the principle of HDCPLN efficiency improvement and the circuit working process.
The multistage signal sources are connected to the gates of the corresponding transistors via the on-off control circuit shown in Figure 5a according to the transformer ratio relationship. Figure 5b is the main circuit topology of the two-stage HDCPLN. On the basis of the single-stage linear converter structure, another input branch is added. Figure 5c shows the detailed control circuit block diagram. The multi-stage low-voltage signals are first amplified to the preset value, and then compared with each threshold potential. Then the signals are connected to the gates of the multi-stage power transistors to control its linear conduction. The low-voltage DC voltage is input through the collector, and the target waveform is finally output on the secondary side of the transformer.
As shown in Figure 5d, v s1 and v s2 are multistage driving signal sources, which input through the gates of T 1 , T 2 , and T f respectively (the same can be seen, −v s1 , −v s2 input through T 1 , T 2 and T f ), where the dotted line indicates that the signal has not passed through the control circuit, the brown part is the actual driving waveform and the primary winding voltage is equal to the driving voltage. v o is the final output voltage waveform of the secondary side of the transformer, i o is the load current, and the DC voltage is E. It can be known that the commutation angles of the two-stage linear converter are respectively θ, π − θ, π + θ, and 2π − θ.
During the period from 0 to θ, the T 1 conducts linearly and the voltage drop is kept to a minimum among all transistors, and the other transistors are in a natural cutoff state. When the instantaneous voltage value of T 1 emitter reaches E, it automatically cut off. From θ to π − θ, T 2 automatically turns on when it meets the optimal turn-on condition, and then iterates back and forth. The timing relationship of the linear turn-on is shown  Table 2. T 1 and T 2 conduct linearly in steps within the positive half cycle of the output current. Similarly, T 1 , T 2 conduct linearly in steps within the negative half cycle.      Figure 5e is a schematic diagram of the traditional power amplifier operation. The shaded part is the transistor voltage drop, and the integral with the current is the transistor loss. In the positive and negative half cycles of the output current, the loss is borne by the same transistor respectively. HDCPLN always controls the voltage drop to a lower value, and the total power consumption is distributed to different transistors, which can improve the working efficiency to a certain extent.

HDCPLN Topology
The method of piecewise-linearization can improve the working efficiency as much as possible under the premise of transmitting the input waveform with high fidelity. The idea of this method is that multiple transistors are linearly conducted in a hierarchical manner, and only one transistor is on at any time and its voltage drop is minimal. Based on this principle, the topology of HDCPLN is shown in Figure 6. The n-stage HDCPLN is mainly composed of 2n-stage signal sources, piecewise-linearization control module, and n parallel single-stage linear converters based on all-N transistor and multi-winding transformer.
is a schematic diagram of the traditional power amplifier operation. The shaded part is the transistor voltage drop, and the integral with the current is the transistor loss. In the positive and negative half cycles of the output current, the loss is borne by the same transistor respectively. HDCPLN always controls the voltage drop to a lower value, and the total power consumption is distributed to different transistors, which can improve the working efficiency to a certain extent.

HDCPLN Topology
The method of piecewise-linearization can improve the working efficiency as much as possible under the premise of transmitting the input waveform with high fidelity. The idea of this method is that multiple transistors are linearly conducted in a hierarchical manner, and only one transistor is on at any time and its voltage drop is minimal. Based on this principle, the topology of HDCPLN is shown in Figure 6. The n-stage HDCPLN is mainly composed of 2n-stage signal sources, piecewise-linearization control module, and n parallel single-stage linear converters based on all-N transistor and multi-winding transformer. The primary side of the multi-winding transformer has 2n windings with consistent directions, and they are connected end to end. Each connection point is used as the tap of the primary winding, and the center tap of the primary winding is used as the potential reference point of the power input on that side. The number of single-stage linear converters is the same as the number of taps of the multi-winding transformer. It can be known from the winding relationship that the taps (1, 2, ..., n) above the center tap and the taps The primary side of the multi-winding transformer has 2n windings with consistent directions, and they are connected end to end. Each connection point is used as the tap of the primary winding, and the center tap of the primary winding is used as the potential reference point of the power input on that side. The number of single-stage linear converters is the same as the number of taps of the multi-winding transformer. It can be known from the winding relationship that the taps (1, 2, . . . , n) above the center tap and the taps (1', 2', . . . , n') are mutually different ends. During a cycle of output current, the transistor connected to the upper tap and the transistor connected to the lower tap are alternately conductive to form a push-pull circuit. The transistors connected to the taps with the same name end conduct linearly in stage in a half cycle of the output current, so as to ensure that the primary output voltage and the DC voltage E always maintain a small difference. By reducing the voltage drop during the linear conduction of the transistors at each stage, the loss during the energy transmission is reduced. The function of the piecewise-linearization control module is to change the point in time when the signal source at each stage is connected to the gate of the transistor.
Let the turns of the primary winding in circuit from stage 1 to stage n be N p11 , N p12 , . . . N p1i , . . . N p1n ; N p21 , N p22 , . . . N p2i , . . . N p2n (N p1i = N p2i = N pi , i = 1, 2, . . . , n), the turns of the secondary winding is N s , then the transformation ratio k i is: The multistage sine wave signal sources are v si (i = 1, 2, . . . , n). The multi-winding transformer superimposes the waveform of the output voltage on the primary side through different transformation ratios, thereby high voltage sine wave output from the secondary side of the transformer, v si needs to satisfy the following equation: In the conduction control module, v si needs to be greater than the comparison potential U i so that it can be added to the gate of the corresponding IGBT. The setting of U i directly determines the turn-on time of the IGBT in the number i converter. To ensure that each transistor can switch linearly on and off according to the timing, the expression of U i is shown in Equation (4), where U 1 = 0 V.

Efficiency Analysis and Optimization of HDCPLN
When HDCPLN is piecewise linearly conductive, the voltage drop and loss of the transistor can be further obtained in the case of obtaining the on-time period in each stage power converter. When the DC supply voltage E is constant, if the linear conduction angle of each transistor is infinitely small, the IGBT conduction voltage drop approaches the critical value of the linear working area. The consumption is almost negligible, then the efficiency of HDCPLN can be approximately equal to 1. The way for the linear conduction time to be infinitely small is to increase the number of stages to infinite, which is obviously impossible to achieve. It is only possible to use the HDCPLN structure with a limited number of stages to obtain higher efficiency. This section takes pure resistive load as an example, calculates the working efficiency of HDCPLN, and optimizes the efficiency with the ratio k i of the multi-winding transformer as a variable.

Efficiency Calculation of HDCPLN
If the time function of the target output voltage v o is known to be f (t) and the cycle is T, the relationship f (t) = −f (t + 0.5 × T) is satisfied, the load is R L , and the DC supply voltage is E. The ratio of a multi-winding transformer can be expressed as: Then the multistage driving signal sources v si (i = 1, 2 , . . . , n) are respectively: In addition, Equations (9) and (10) satisfy the following relationship: The current i of the number i transistor when it is turned on linearly is: In Equation (12), i o represents the current on the load. The total output power of HDCPLN is P o .
Furthermore, the transistor losses P T i and P T i of each stage can be obtained.
Since the conduction state of T i in the negative half cycle of the output current is exactly the same as T i , P T i is equal to P T i , then the total loss P T is: Then the theoretical working efficiency of HDCPLN can be found.

Ratio Optimal Design
The expected output voltage waveform is the standard sine of the amplitude V om . Set the transformer ratio k i as the variable. With the maximum efficiency of HDCPLN as the goal, the optimal objective function under theoretical conditions can be obtained according to Equation (16).
In the Equation (17): the first and second constraints are equality constraints, and the upper and lower limits of the integral and the value of the number n ratio k n of the transformer are given when solving the loss at each stage; The third is the ratio constraint between the primary and secondary windings at all stages.
Set the amplitude of the output voltage V om equal to 310 V and the DC voltage E to 50 V. In the Matlab software environment, set different transformer winding numbers (i = 2, 3, . . . . . . ) in turn, and use genetic algorithm programming to solve the multivariate optimization problem of formula 17 with a single objective in consideration of constraints which include equal constraints and unequal constraints [18][19][20]. We can obtain the design strategy and corresponding optimal efficiency. As shown in Table 3, the efficiency of HDCPLN increases as the number of transformer ratios increases. The conventional design of multi-winding transformer ratio refers to that the voltages of the primary side tap are distributed at equal interval. Compared with the efficiency with the conventional transformer ratio design, the optimized results are significantly improved. The optimized three-segment power converter can reach the efficiency level of the conventional four-segment conversion. The efficiency of a four-stage HDCPLN using an optimized transformation ratio distribution can reach 91.49%, which is a 12.95% improvement over traditional class-B amplifiers. In addition, if you want to further improve the working efficiency, you can increase the number of the windings and use more power converters in parallel. Analysis shows that variation of HDCPLN working efficiency with the number of transformation ratios is shown in Figure 7. It is necessary to make a trade-off between design cost and work efficiency. Although the efficiency increases with the increase in the number of power converters, the cost will undoubtedly increase as a result. This will also have some effects, such as the design cost and difficulty of multi-winding transformers, the cost of power transistors and the layout of radiators, the design of multiple independent control signals, and the internal layout design of the power supply. From Figure 7, it is easy to know that when the number of converters increases to a certain value, and the cost increases in proportion, but the efficiency increase is no longer obvious. When 8-stage converters are connected in parallel, a very high theoretical efficiency (95.24%) has been reached. After calculation analysis and comprehensive consideration, this is the best choice for large-scale applications of the novel linear power supply. Electronics 2021, 10, x FOR PEER REVIEW 12 of 17 Figure 7. Variation of HDCPLN working efficiency with the number of transformation ratios.

Experimental Verification
In order to verify the correctness of theoretical research, a four-stage HDCPLN experimental prototype is designed and built in this paper. Figure 8 is a photo of the experimental platform, and the circuit parameters are shown in Table 4. Figure 9 shows the experimental results of the output voltage and current waveforms. The peak value of the load voltage is 310 V and the average power is 1 kW. Analysis of the data in Figure 9a shows that the total harmonic distortion coefficient (THD) of the load voltage and current are less than 1.5%, which achieves high-fidelity power amplification. In Figure 9b, ii represents the current flowing through the center tap of the primary side of the multi-winding transformer. It is a continuous DC waveform, which is consistent with the theoretical analysis. Figure 9c shows the results obtained from the no-load test. if and i

Experimental Verification
In order to verify the correctness of theoretical research, a four-stage HDCPLN experimental prototype is designed and built in this paper. Figure 8 is a photo of the experimental platform, and the circuit parameters are shown in Table 4. Figure 9 shows the experimental results of the output voltage and current waveforms. The peak value of the load voltage is 310 V and the average power is 1 kW. Analysis of the data in Figure 9a shows that the total harmonic distortion coefficient (THD) of the load voltage and current are less than 1.5%, which achieves high-fidelity power amplification. In Figure 9b, i i represents the current flowing through the center tap of the primary side of the multi-winding transformer. It is a continuous DC waveform, which is consistent with the theoretical analysis. Figure 9c shows the results obtained from the no-load test. i f and i f represent the excitation current flowing through the T f and T f branches of the transformer. Figures 10 and 11 show the waveforms of the current and the output voltage of the primary side of the four-stage HDCPLN experimental prototype. i oi and i oi represent the current flowing through the i-th power branch when the load current is positive and negative. v oi and v oi respectively represent the output voltage of the i-th stage power converter on the primary side when the load current is positive and negative. It can be seen from Figure 10 that the output voltage of the primary side of each stage of the power converter satisfies the turns ratio relationship between the windings. It superimposes the waveforms output on the secondary side in sections to accurately output the expected load voltage.         Figure 11 shows the current waveform of the transistor in each period of time in the HDCPLN. It can be seen that the power transistors (IGBTs) at various stages can switch the on and off states according to the control strategy, and the multistage converter circuit is linearly conducted in sections according to the timing. However, there is an overlapping part in the power-on period of each stage. When two IGBTs are turned on linearly, there are two-stage power converters working in parallel. This parallel operation can ensure  Figure 11 shows the current waveform of the transistor in each period of time in the HDCPLN. It can be seen that the power transistors (IGBTs) at various stages can switch the on and off states according to the control strategy, and the multistage converter circuit is linearly conducted in sections according to the timing. However, there is an overlapping part in the power-on period of each stage. When two IGBTs are turned on linearly, there are two-stage power converters working in parallel. This parallel operation can ensure that the output waveform is not distorted during the switching time and reduce the current change rate of the transistor, but the disadvantage is that the loss is slightly increased.
The waveforms of the transistor voltage drops v cei and v cei at all stages and the currents i oi and i oi flowing through the transistor are shown in Figure12. It can be seen that when each stage of IGBT is turned on linearly, its transistor voltage drop is in a low state, and the minimum value is close to the IGBT's saturation voltage drop. According to the waveform data in Figure 12, the transistor consumption of each stage can be obtained. The comparison result with the theoretical calculation is shown in Table 5. When calculating the theoretical value of the transistor loss, the default minimum value of the dynamic transistor voltage drop can reach zero. However, when the actual IGBT is turned on linearly, its turn-on voltage is greater than the saturation voltage drop. Therefore, the loss of each stage must be slightly larger than the theoretical data, and the experimental results meet the above rules. There are other losses with slight effects which cause difference between the working efficiency of the prototype and the theoretical value.
The current mainstream solutions for power supplies without partial discharge are linear power supplies, and so are the novel high-efficiency power supplies we proposed. After experimental analysis, the output waveform is almost pure sine wave without complex interference signals, which obviously meets the necessary conditions for no partial discharge. We have done a comparative analysis through series resonance experiments, and the output voltage is 200 kV. One of the experiments is a series resonance experiment on the proposed linear power supply. The second experiment is exactly the same as the first experiment, except that it uses the traditional mechanical contact voltage regulator to draw electricity directly from the grid, which is the control group. The two experimental processes are exactly the same, and the partial discharges during the two experimental processes are measured by a detector. In the two cases, the partial discharge measured by the detector is almost the same, one is 71.7 pC and the other is 71.8 pC, which shows that the linear power supply body does not cause additional partial discharge effects.
comparison result with the theoretical calculation is shown in Table 5. When calculating the theoretical value of the transistor loss, the default minimum value of the dynamic transistor voltage drop can reach zero. However, when the actual IGBT is turned on linearly, its turn-on voltage is greater than the saturation voltage drop. Therefore, the loss of each stage must be slightly larger than the theoretical data, and the experimental results meet the above rules. There are other losses with slight effects which cause difference between the working efficiency of the prototype and the theoretical value. The current mainstream solutions for power supplies without partial discharge are linear power supplies, and so are the novel high-efficiency power supplies we proposed. After experimental analysis, the output waveform is almost pure sine wave without complex interference signals, which obviously meets the necessary conditions for no partial discharge. We have done a comparative analysis through series resonance experiments, and the output voltage is 200 kV. One of the experiments is a series resonance experiment on the proposed linear power supply. The second experiment is exactly the same as the

Conclusions
The paper proposes a kind of high-efficiency linear power supply, whose power device works in the linear state. There is no pulse interference problem so that it can be used as the input part of high voltage test power supply. In application, the transformer in HDCPLN can replace the step-up transformer in the high-voltage test power supply, which can further reduce the volume of the test equipment. In addition, the novel power amplifier topology also solves the problem that traditional power conversion has low working efficiency and cannot achieve high power output due to the limitation of P-type transistor parameters. The converter input by a plurality of power amplifier modules connected in parallel, which are linearly conducted in a hierarchical manner. Only one transistor is on at any time and its voltage drop is minimal.
(1) The topology based on above principle can achieve efficient power amplification.
(2) The optimized multi-winding transformer ratio of the same number can further reduce transistor consumption, thereby improving efficiency. (3) The increase in efficiency increases with the number of segments.
In addition, the analysis of the experimental results found that there is a large difference between the transistor loss at each stage. A method of making it evenly distributed among the transistors with the lowest total consumption is worth further exploration.