An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/μs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.


Introduction
One of the most significant and critical elements of analog integrated circuits are comparators [1,2].Comparators play a pivotal role in regulating the decisive parameters of many imperative analog and digital circuits [3].Data converters are one such kind of circuit as their speed of conversion, resolution, and power consumption, along with other prominent parameters, depends directly on it [4][5][6].The CMOS fabrication technologies have entered the submicron domain, and transistor sizing is scaling down to nano-dimension levels.This, in turn, restrains the maximum power supply voltage in ICs eventually allowing an audit of the fidelity of these MOS transistors [6][7][8].This effect is positive for digital ICs, but has an adverse impact on analog ICs.The primary consequences of this scaling are reduced output conductance and small output voltage swing and, hence, led to decreased DC gains [9].Thus, the op-amp comparators designed under such CMOS technologies with restrained supply voltage will not be able to comply with the designer requisites and, thus, adversely affect the performance parameters of abstract circuits that employ these comparators as their core element [10].Data converters, such as ADC and DAC conversion speed and accuracy, sturdily depend upon the comparator's capability to detect the smallest voltage levels [11,12].The op-amp comparators with a high slew rate and high gain with high accuracy are to be designed in order to attain these excellent parameters in data converters [13,14].
A modified architecture is proposed in this paper, which suggests useful data information in understanding the performance of op-amp comparators.Better optimization for providing an accurate differential mode gain and high slew rate is achieved through this design [14].Thus, to meet the requirement of gain in the op-amp comparator modified architecture with gain a boosting block is used.Common mode feedback (current feedback) is used in the circuit of the op-amp comparator to maintain the output node at constant DC [15].Current biasing of the modified design is done by using current mirrors [16].The common mode feedback with modified architecture and gain boosting block provides a very high gain with an improved gain error by more than 95% [17].The use of the cascode current mirror structure in the current feedback amplifier, in addition to the high gain, also provides a very high slew rate [18].
This manuscript is further assembled as follows: Section 2 dispenses a quick overview of the modified circuit description in the form of a circuit.Section 3 provides details about the simulation results and explanations of the analysis of the modified architecture.Section 4 contains comparisons of the modified architecture with existing op-amp comparators, like DCFIA, SCFIA [19], and CMFD [20][21][22][23], which utilize common mode current feedback through tables and graphs.The paper concludes with Section 5.

Circuit Description
Figure 1 depicts the block architecture for common-mode feedback structure [20].It incorporates three major blocks.First, there is a fully differential pair amplifier that works in balanced mode.Next, there is a sensing circuit stage which senses common mode output signal.In the final stage, there is a comparator which compares this output common mode signal with a reference voltage and feeds the rectified signal back to the fully differential pair that, in turn, adjusts according to this signal [21].The reference voltage ideally equals 0 V. Thus, a rectified signal is formed and applied to the fully differential pair, such that, finally, the alteration signal becomes near to zero.The rectified signal is a subtracted value taken by subtracting the reference voltage and the common-mode signal [22,24].and accuracy, sturdily depend upon the comparator's capability to detect the smallest voltage levels [11,12].The op-amp comparators with a high slew rate and high gain with high accuracy are to be designed in order to attain these excellent parameters in data converters [13,14].A modified architecture is proposed in this paper, which suggests useful data information in understanding the performance of op-amp comparators.Better optimization for providing an accurate differential mode gain and high slew rate is achieved through this design [14].Thus, to meet the requirement of gain in the op-amp comparator modified architecture with gain a boosting block is used.Common mode feedback (current feedback) is used in the circuit of the op-amp comparator to maintain the output node at constant DC [15].Current biasing of the modified design is done by using current mirrors [16].The common mode feedback with modified architecture and gain boosting block provides a very high gain with an improved gain error by more than 95% [17].The use of the cascode current mirror structure in the current feedback amplifier, in addition to the high gain, also provides a very high slew rate [18].
This manuscript is further assembled as follows: Section 2 dispenses a quick overview of the modified circuit description in the form of a circuit.Section 3 provides details about the simulation results and explanations of the analysis of the modified architecture.Section 4 contains comparisons of the modified architecture with existing op-amp comparators, like DCFIA, SCFIA [19], and CMFD [20][21][22][23], which utilize common mode current feedback through tables and graphs.The paper concludes with Section 5.

Circuit Description
Figure 1 depicts the block architecture for common-mode feedback structure [20].It incorporates three major blocks.First, there is a fully differential pair amplifier that works in balanced mode.Next, there is a sensing circuit stage which senses common mode output signal.In the final stage, there is a comparator which compares this output common mode signal with a reference voltage and feeds the rectified signal back to the fully differential pair that, in turn, adjusts according to this signal [21].The reference voltage ideally equals 0 V. Thus, a rectified signal is formed and applied to the fully differential pair, such that, finally, the alteration signal becomes near to zero.The rectified signal is a subtracted value taken by subtracting the reference voltage and the common-mode signal [22,24].Figure 2 shows the entire architecture of the modified op-amp comparator (GB-CMFD) with gain boosting and common mode current feedback [23][24][25].Inputs are given to the dual input fully differential pair that comprises of M1 and M2 MOSFETS.The output of this differential pair is taken from the output node which incorporates folded cascode current mirrors as source and sink.M4, M5, M6, and M7 form a current source while, on the other hand, M8, M9, M10, and M11 forms a current sink [26].The sensing circuit comprises Ms1 and Ms2, which sense the common mode signal from the output node.Next, this signal is compared with the reference voltage through a comparator circuit through M3 and M12. Figure 2 shows the entire architecture of the modified op-amp comparator (GB-CMFD) with gain boosting and common mode current feedback [23][24][25].Inputs are given to the dual input fully differential pair that comprises of M1 and M2 MOSFETS.The output of this differential pair is taken from the output node which incorporates folded cascode current mirrors as source and sink.M4, M5, M6, and M7 form a current source while, on the other hand, M8, M9, M10, and M11 forms a current sink [26].The sensing circuit comprises Ms1 and Ms2, which sense the common mode signal from the output node.Next, this signal is compared with the reference voltage through a comparator circuit through M3 and M12.The difference signal taken from the differential pair M1 and M2 is amplified further by the next stage, which comprises of eight MOS devices.RA and RB are the output resistances at output nodes vout(+) and vout(−), respectively.These output resistances are responsible for the high output gain of the op-amp comparator circuit as the gain of any amplifier is estimated by the product of its transconductance and output resistance.M8, M9, M10, and M11 MOS devices are arranged and biased in such a manner as to provide high resistance to the output nodes.
In the final segment of the operational amplifier comparator, the gain booster block interacts with the M8 and M9 MOS devices.The output from the drain terminal of M8 and M9 NMOS devices is fed into the gate terminal of MG4 and MG3 MOSFET devices, respectively, which are working in a common source amplifier configuration.The MOS devices MG2 and MG1 are biased with a voltage vb3 and connected to the drain terminal of MG4 and MG3 devices to increase the resistance at the output terminal.Thus, the output of the op-amp comparator gets enhanced by the gain of the gain booster block and is again fed back to the gate terminal of M8 and M9 devices and, thus, the overall output gain of operational amplifier comparator gets boosted.
Major differences in this modified schematic with respect to the general CMFD topology [23][24][25] are the less complicated structure by utilizing fewer MOS devices, which ultimately reduces power consumption of this modified structure.For gain boosting this structure employs only one gain boosting block in the pull-down section.As there are fewer MOS devices in the pull-up section, it results in the fast charging of the output node, which eventually leads to a high slew rate.

Mathematical Analysis
Gain for the differential pair is given as: where, gm is the effective trans-conductance and Rout is the effective output resistance [1,13].Looking at the output node Vout the resistance RB can be calculated as given in Equation ( 1): Additionally, the current I7 that flows through this output node can be calculated as: The difference signal taken from the differential pair M1 and M2 is amplified further by the next stage, which comprises of eight MOS devices.R A and R B are the output resistances at output nodes vout(+) and vout(−), respectively.These output resistances are responsible for the high output gain of the op-amp comparator circuit as the gain of any amplifier is estimated by the product of its transconductance and output resistance.M8, M9, M10, and M11 MOS devices are arranged and biased in such a manner as to provide high resistance to the output nodes.
In the final segment of the operational amplifier comparator, the gain booster block interacts with the M8 and M9 MOS devices.The output from the drain terminal of M8 and M9 NMOS devices is fed into the gate terminal of MG4 and MG3 MOSFET devices, respectively, which are working in a common source amplifier configuration.The MOS devices MG2 and MG1 are biased with a voltage vb3 and connected to the drain terminal of MG4 and MG3 devices to increase the resistance at the output terminal.Thus, the output of the op-amp comparator gets enhanced by the gain of the gain booster block and is again fed back to the gate terminal of M8 and M9 devices and, thus, the overall output gain of operational amplifier comparator gets boosted.
Major differences in this modified schematic with respect to the general CMFD topology [23][24][25] are the less complicated structure by utilizing fewer MOS devices, which ultimately reduces power consumption of this modified structure.For gain boosting this structure employs only one gain boosting block in the pull-down section.As there are fewer MOS devices in the pull-up section, it results in the fast charging of the output node, which eventually leads to a high slew rate.

Mathematical Analysis
Gain for the differential pair is given as: where, g m is the effective trans-conductance and R out is the effective output resistance [1,13].Looking at the output node V out the resistance R B can be calculated as given in Equation ( 1): Additionally, the current I 7 that flows through this output node can be calculated as: .
(gds 2 + gds 5 ) where R out is given as: R out = [g m9 .ro 9 .ro 11 ] [g m7 ro 7 (ro 2 ro 5 )] Rearranging and solving the Equation ( 4) by assuming trans-conductance and output resistance of all mirrors as g m and ro: Now, solving for the gain boosting circuit, R out can be calculated as: Again, solving for gain: Comparing Equations ( 5) and ( 6) it can be easily concluded that with the modified architecture the gain improves in comparison to the general common feedback structure [23][24][25].

Results
In this segment, all the required simulations, such as transient, AC analysis, along with parameter variations of the modified circuit using a closed loop configuration is demonstrated.Monte Carlo simulations have been performed by using SPICE in 90 nm CMOS technology.At least 20 iterations are performed by utilizing the Monte Carlo simulation methods for concluding the final results.
An op-amp with a feedback circuit is designed to have a gain of 20.The design schematic blocks of that are shown in Figure 3 [15,27].
parameter variations of the modified circuit using a closed loop configuration is demonstrated.Monte Carlo simulations have been performed by using SPICE in 90 nm CMOS technology.At least 20 iterations are performed by utilizing the Monte Carlo simulation methods for concluding the final results.
An op-amp with a feedback circuit is designed to have a gain of 20.The design schematic blocks of that are shown in Figure 3 [15,27].Table 1 shows the power consumption, maximum current drawn, and the rise time and fall time of the modified op-amp (GB-CMFD) comparator.Simulation is done on a supply voltage of 0.7 V at 25 °C.Variations in the parameters when the channel width is varied from 1 μm to 5 μm are also included in Table 1.This circuit draws a maximum current of 517 μA by consuming the power of 362 μW at 1 μm channel width.The values of power consumption and current drawn are increased by 44% when the channel width is increased to 5 μm. Figure 5a,b shows these variations graphically.
Table 1 also gives the details regarding the rising and falling duration for the output pulse and Table 1 shows the power consumption, maximum current drawn, and the rise time and fall time of the modified op-amp (GB-CMFD) comparator.Simulation is done on a supply voltage of 0.7 V at 25 • C. Variations in the parameters when the channel width is varied from 1 µm to 5 µm are also included in Table 1.This circuit draws a maximum current of 517 µA by consuming the power of 362 µW at 1 µm channel width.The values of power consumption and current drawn are increased by 44% when the channel width is increased to 5 µm.Figure 5a,b shows these variations graphically.
Table 1 also gives the details regarding the rising and falling duration for the output pulse and its variation with channel width.Rise and fall times of 7 ps are observed for both rising and falling edges.The variations in these values are negligible with the variation in channel width.
Figure 6 gives details regarding the output waveforms that are recorded with respect to the input waves for the modified structure (CMFD-GB).The input voltage at the negative terminal is kept constant at 350 millivolts and then a varying voltage is applied at the positive terminal.The output waveform at the non-inverting terminal, which is recorded, is shown in Figure 6 J. Low    Table 2 shows power consumption, observed closed loop gain, open loop gain, gain error, and slew rate of the modified GB-CMFD comparator.Simulation is done at a supply voltage of 0.7 V by varying the temperature from −5 °C to 55 °C.Table 2 shows power consumption, observed closed loop gain, open loop gain, gain error, and slew rate of the modified GB-CMFD comparator.Simulation is done at a supply voltage of 0.7 V by varying the temperature from −5 °C to 55 °C.In Table 2 the variations in the power consumption are detailed.The modified circuit consumes 362 µW at 25 • C.This value increases marginally but remains close to 362 µW when the temperature is raised to 55 • C. On the other hand, when the temperature was reduced to −5 • C the power consumption increased further and attained the value of 365 µW at −5 • C. Figure 7a shows the variations of power consumption with temperature.In Table 2 the variations in the power consumption are detailed.The modified circuit consumes 362 μW at 25 °C.This value increases marginally but remains close to 362 μW when the temperature is raised to 55 °C.On the other hand, when the temperature was reduced to −5 °C the power consumption increased further and attained the value of 365 μW at −5 °C. Figure 7a shows the variations of power consumption with temperature.The gain error variations with temperature are shown in Table 2. Though the circuit is designed in a closed loop configuration for the power gain of 20, which equals 13.01 dB, the values that are obtained from the magnitude plot are marginally different at different temperatures.The gain error is almost constant for the temperature range of −5 to 25 °C and has an error of 0.1% from the expected value, which is relatively acceptable.Figure 7d shows the variations of gain error with temperature.The gain error variations with temperature are shown in Table 2. Though the circuit is designed in a closed loop configuration for the power gain of 20, which equals 13.01 dB, the values that are obtained from the magnitude plot are marginally different at different temperatures.The gain error is almost constant for the temperature range of −5 to 25 • C and has an error of 0.1% from the expected value, which is relatively acceptable.Figure 7d shows the variations of gain error with temperature.
Figure 8 represents the frequency response of the closed loop CMFD-GB structure.The variations in the closed loop gain with respect to temperature can be easily observed from this response.

𝑆𝐿𝐸𝑊 𝑅𝐴𝑇𝐸 = 𝑉𝑂𝐿𝑇𝐴𝐺𝐸 𝐿𝐸𝑉𝐸𝐿 (𝑉) 𝑅𝐼𝑆𝐸 𝑇𝐼𝑀𝐸 (µs) 𝑜𝑟 𝐹𝐴𝐿𝐿 𝑇𝐼𝑀𝐸 (µs)
Thus, from the above relation, if a circuit has a very small value of rising time and fall time then it will eventually have a very high slew rate.
From Table 1 the rise time and fall time for this modified GB-CMFD circuit are seven picoseconds and the maximum minus minimum voltage range that is observed after the simulation is 0.006 V for both the rising and falling edge.Thus, using these values, a slew rate of 839 V/μs is obtained for the circuit, which is quite a high value as compared to the other comparators.Figure 9a,b shows the variations of the slew rate for charging and discharging edge with temperature.
It can be seen that this variation is very minute and, thus, this circuit has a high slew rate which is almost stable with temperature variations.Table 3 summarizes the performance of the modified gain boosting CMFD comparator.CMOS technology is used to design this circuit with the channel length of 90 nm and channel width of 1 μm.A supply voltage of 0.7 V is deployed for the simulations.Twenty-four MOS transistors are used for designing the circuit, along with four capacitors and two resistors.The value of power consumption at 25 °C is 362 μW while drawing a current of 517 μA, both having a variation of approximately 2%.A total of 12.93 decibels of closed loop gain is observed at 25 °C, which is quite close to the calculated gain of 13.01 decibels.
The open loop gain of 1075 is attained by this structure at 25 °C, which is large, compared to normal comparator structures.A gain error of 0.6% is obtained after simulation of this circuit at 25 °C, which is relatively acceptable.A very high slew rate is achieved by this modified design that is In the end Table 2 gives the details regarding the slew rate of the modified gain boosting CMFD comparator and its variations with temperature.Slew rate is the measure of the rate at which the output voltage rises with respect to time [28].Thus, if a comparator has a high slew rate, it will lead to the high speed of comparison [29].

SLEW RATE =
VOLTAGE LEVEL (V) RISE TI ME (µs) or FALL TI ME (µs) Thus, from the above relation, if a circuit has a very small value of rising time and fall time then it will eventually have a very high slew rate.
From Table 1 the rise time and fall time for this modified GB-CMFD circuit are seven picoseconds and the maximum minus minimum voltage range that is observed after the simulation is 0.006 V for both the rising and falling edge.Thus, using these values, a slew rate of 839 V/µs is obtained for the circuit, which is quite a high value as compared to the other comparators.Figure 9a,b shows the variations of the slew rate for charging and discharging edge with temperature.
It can be seen that this variation is very minute and, thus, this circuit has a high slew rate which is almost stable with temperature variations.

𝑆𝐿𝐸𝑊 𝑅𝐴𝑇𝐸 = 𝑉𝑂𝐿𝑇𝐴𝐺𝐸 𝐿𝐸𝑉𝐸𝐿 (𝑉) 𝑅𝐼𝑆𝐸 𝑇𝐼𝑀𝐸 (µs) 𝑜𝑟 𝐹𝐴𝐿𝐿 𝑇𝐼𝑀𝐸 (µs)
Thus, from the above relation, if a circuit has a very small value of rising time and fall time then it will eventually have a very high slew rate.
From Table 1 the rise time and fall time for this modified GB-CMFD circuit are seven picoseconds and the maximum minus minimum voltage range that is observed after the simulation is 0.006 V for both the rising and falling edge.Thus, using these values, a slew rate of 839 V/μs is obtained for the circuit, which is quite a high value as compared to the other comparators.Figure 9a,b shows the variations of the slew rate for charging and discharging edge with temperature.
It can be seen that this variation is very minute and, thus, this circuit has a high slew rate which is almost stable with temperature variations.Table 3 summarizes the performance of the modified gain boosting CMFD comparator.CMOS technology is used to design this circuit with the channel length of 90 nm and channel width of 1 μm.A supply voltage of 0.7 V is deployed for the simulations.Twenty-four MOS transistors are used for designing the circuit, along with four capacitors and two resistors.The value of power consumption Table 3 summarizes the performance of the modified gain boosting CMFD comparator.CMOS technology is used to design this circuit with the channel length of 90 nm and channel width of 1 µm.A supply voltage of 0.7 V is deployed for the simulations.Twenty-four MOS transistors are used for designing the circuit, along with four capacitors and two resistors.The value of power consumption at 25 • C is 362 µW while drawing a current of 517 µA, both having a variation of approximately 2%.A total of 12.93 decibels of closed loop gain is observed at 25 • C, which is quite close to the calculated gain of 13.01 decibels.
The open loop gain of 1075 is attained by this structure at 25 • C, which is large, compared to normal comparator structures.A gain error of 0.6% is obtained after simulation of this circuit at 25 • C, which is relatively acceptable.A very high slew rate is achieved by this modified design that is 839 V/µs that will eventually lead to a very high speed of comparison and, thus, this comparator can be utilized in designing high-speed analog circuits, such as ADCs and DACs [30][31][32].4 summarizes the percentage variation of these parameters with temperature.Power consumption varies substantially with the decrease in temperature.A total of 0.07% of marginal variations are recorded for observed closed loop gain, which almost equals zero and is acceptable.Open loop gain variations are then shown in the table, which varies from 12% at −5 • C and 14% at 55 • C. Significant variations in the gain error are recorded when the temperature scales down to −5 • C on the other hand, when the temperature increased to 55 • C the variations are minimal.Almost null variations are observed for the slew rate.

Comparison
To evaluate the proposed modified architecture of the op-amp comparator (GB-CMFD) three more structures of the op-amp comparator are utilized for analyses and comparison.These three structures are DCFIA, SCFIA [19], and CMFD [23,24].The structural design of these three architectures are depicted in Appendix A (Figures A1-A3).DCFIA and SCFIA are the amplifiers which employ common mode current feedback from drain and source terminals [10].CMFD is a common mode current feedback with conventional cascode amplifier [23,24].
These three structures are again simulated in 90 nm CMOS technology.Results that are obtained after Monte Carlo simulation are shown in Table 5. Figure 10 shows the variations in the power consumptions for all four comparators structures when the temperature is varied from −5 to +55 • C. The proposed modified architecture, despite using 24 MOS transistors, consumes power at a moderate level, which is approximately in the range of 360 µW.It also shows marginal variations with temperature variations.Figure 10 shows the variations in the power consumptions for all four comparators structures when the temperature is varied from −5 to +55 °C.The proposed modified architecture, despite using 24 MOS transistors, consumes power at a moderate level, which is approximately in the range of 360 μW.It also shows marginal variations with temperature variations.Figure 11 shows the comparison of the gain error value for all four structures.It can be observed from the curves that GB-CMFD has the least value of the percentage gain error.Maximum variations in the gain error is shown by DCFIA and CMFD structures which increased substantially when temperature varies from −5 to +55 °C.SCFIA show the least variation with temperature but has more gain error value than GB-CMFD.Figure 11 shows the comparison of the gain error value for all four structures.It can be observed from the curves that GB-CMFD has the least value of the percentage gain error.Maximum variations in the gain error is shown by DCFIA and CMFD structures which increased substantially when temperature varies from −5 to +55 • C. SCFIA show the least variation with temperature but has more gain error value than GB-CMFD.Table 7 gives details regarding the comparison on the basis of power consumption of this comparator with other pertinent associated studies.

Conclusions
A modified architecture of an op-amp comparator to achieve a high slew rate and boosted gain with an improvement in gain design error is proposed and investigated in this manuscript.Deploying the gain booster block and common-mode current feedback structure, the modified Table 6 summarizes these parametric variations of all four structures at different temperatures.The modified op-amp comparator (GB-CMFD) shows the least variation in comparison to others in all six parameters which are taken into consideration for comparison.Table 7 gives details regarding the comparison on the basis of power consumption of this comparator with other pertinent associated studies.

Conclusions
A modified architecture of an op-amp comparator to achieve a high slew rate and boosted gain with an improvement in gain design error is proposed and investigated in this manuscript.Deploying the gain booster block and common-mode current feedback structure, the modified architecture of the op-amp comparator (CMFD-GB) achieves an improvement in the overall gain and slew rate with the reduction in gain error and power consumption.An overall gain of 1075 is attained by implementing an additional gain booster block at the end segment of the op-amp comparator that is approximately a 34% improvement as compared to the general common-mode current feedback structure.The rise and fall time also get reduced due to this boosted gain which, in turn, leads to the very high slew rate for this modified op-amp comparator structure.A slew rate of 839 V/µs is observed for this modified op-amp comparator structure, which is quite high and which makes this comparator a prominent contender for high-speed data converters circuits.Closed loop analysis of the modified op-amp comparator structure is done by utilizing this structure for designing a closed feedback amplifier with a gain of 13.01 dB.Results from the simulations depict that the observed and design gain is almost equal for the CMFD-GB comparator with the value of 12.93 decibels.Comparing it to the general CMFD structure, this is an approximately 27% reduction.Considerable reduction in power consumption is also attained through this modified op-amp comparator structure.In spite of using more MOS devices, the power consumption observed for this modified architecture is 362.29 µW, which almost equals a 70% reduction as compared to general CMFD structure.The modified architecture of the op-amp comparator along with high slew rate also shows symmetry for charging and discharging output edges which makes it perfect for the designing of accurate and linear data converter circuits.Temperature sensitivity of these parameters is also observed for the modified comparator architecture by simulating this circuit at different temperatures.The results show an optimum variation of these critical parameters with varying temperature for the modified op-amp comparator architecture (CMFD-GB) as compared to three other architectures.Boosted gain and a large slew rate with optimum power consumption of this modified op-amp comparator structure (CMFD-GB) increases its applicability in high-speed analog and digital circuits, which are designed in ultra deep submicron technologies where high-speed and low-power consumption are the essential design constraints.

Figure 1 .
Figure 1.Block structure of current mode feedback op-amp.

Figure 1 .
Figure 1.Block structure of current mode feedback op-amp.

Figure 3 .
Figure 3.An operational amplifier with feedback.Figure 3.An operational amplifier with feedback.

Figure 3 .
Figure 3.An operational amplifier with feedback.Figure 3.An operational amplifier with feedback.

Figure 4 16 Figure 4
Figure 4 represents the modified circuit of the op-amp comparator employing common mode current feedback with folded cascoded current mirrors along with gain-boosting circuit.The channel length of 90 nm and the channel width of 1 µm is used as the dimension of MOS devices in the proposed op-amp comparator modified architecture.J. Low Power Electron.Appl.2018, 8, x FOR PEER REVIEW 5 of 16

Figure 4 .
Figure 4. Comparator with modified gain boosting current feedback.

Figure 4 .
Figure 4. Comparator with modified gain boosting current feedback.

Figure 6 .
Figure 6.Output waveforms of CMFD-gain boosting comparator (transient analysis).Table 2 shows power consumption, observed closed loop gain, open loop gain, gain error, and slew rate of the modified GB-CMFD comparator.Simulation is done at a supply voltage of 0.7 V by varying the temperature from −5 • C to 55 • C.

Figure 7b ,
Figure 7b,c exhibit the observed closed loop gain and open loop gain variations with temperature.An observed closed loop gain of 12.93 decibels at 25 °C is recorded, which is very close to the designed closed loop gain of 13.01 decibels.Diminutive level variations are recorded when the temperature varied from −5 to 55 °C.Open loop gain is then detailed with its variations with temperature.The open loop gain of 1075 is observed for the GB-CMFD structure at 25 °C, which is quite large as compared to standard comparator structures.The open loop gain of 1075 is recorded for the modified architecture at 25 °C, which increases to 1229 when the temperature is raised to 55 °C.However, the open loop gain reduced to 953 when the temperature is reduced to −5 °C.Overall, the percentage variations of the open loop gain are 11% to 14% with the variations in temperature.The gain error variations with temperature are shown in Table2.Though the circuit is designed in a closed loop configuration for the power gain of 20, which equals 13.01 dB, the values that are obtained from the magnitude plot are marginally different at different temperatures.The gain error is almost constant for the temperature range of −5 to 25 °C and has an error of 0.1% from the expected value, which is relatively acceptable.Figure7dshows the variations of gain error with temperature.

Figure 7b ,
Figure 7b,c exhibit the observed closed loop gain and open loop gain variations with temperature.An observed closed loop gain of 12.93 decibels at 25 • C is recorded, which is very close to the designed closed loop gain of 13.01 decibels.Diminutive level variations are recorded when the temperature varied from −5 to 55 • C. Open loop gain is then detailed with its variations with temperature.The open loop gain of 1075 is observed for the GB-CMFD structure at 25 • C, which is quite large as compared to standard comparator structures.The open loop gain of 1075 is recorded for the modified architecture at 25 • C, which increases to 1229 when the temperature is raised to 55 • C.However, the open loop gain reduced to 953 when the temperature is reduced to −5 • C. Overall, the percentage variations of the open loop gain are 11% to 14% with the variations in temperature.

Figure 8 .
Figure 8. Variations in closed loop gain with temperature (AC analysis).

Figure 8 .
Figure 8. Variations in closed loop gain with temperature (AC analysis).

Figure 8 .
Figure 8. Variations in closed loop gain with temperature (AC analysis).

Figure 12
Figure12illustrates the variations of observed closed loop gain for all four comparator structures.All four structures are employed in the circuit shown in Figure3, which is designed for a closed loop gain of 13.01 decibel.The values of actual closed-loop gain that are observed at different temperatures in the simulations are then plotted in Figure12.The magnitude of the observed closed loop gain for GB-CMFD is almost constant and very close to the designed closed loop value.The magnitude of observed closed loop gain for DCFIA decreases with the increase in temperature opposite to that of the observed CMFD closed loop gain value, which increases with the increase in temperature.The observed SCFIA closed loop gain values are small as compared to DCFIA and CMFD, but substantially large as compared to GB-CMFD.

Figure 13
Figure 13 depicts the variations in open loop gain with temperature.The GB-CMFD structure again shows the maximum magnitude of the open loop gain at different temperatures in comparison to other structures.

Figure 12
Figure12illustrates the variations of observed closed loop gain for all four comparator structures.All four structures are employed in the circuit shown in Figure3, which is designed for a closed loop gain of 13.01 decibel.The values of actual closed-loop gain that are observed at different temperatures in the simulations are then plotted in Figure12.The magnitude of the observed closed loop gain for GB-CMFD is almost constant and very close to the designed closed loop value.The magnitude of observed closed loop gain for DCFIA decreases with the increase in temperature opposite to that of the observed CMFD closed loop gain value, which increases with the increase in temperature.The observed SCFIA closed loop gain values are small as compared to DCFIA and CMFD, but substantially large as compared to GB-CMFD.

Figure 12
Figure12illustrates the variations of observed closed loop gain for all four comparator structures.All four structures are employed in the circuit shown in Figure3, which is designed for a closed loop gain of 13.01 decibel.The values of actual closed-loop gain that are observed at different temperatures in the simulations are then plotted in Figure12.The magnitude of the observed closed loop gain for GB-CMFD is almost constant and very close to the designed closed loop value.The magnitude of observed closed loop gain for DCFIA decreases with the increase in temperature opposite to that of the observed CMFD closed loop gain value, which increases with the increase in temperature.The observed SCFIA closed loop gain values are small as compared to DCFIA and CMFD, but substantially large as compared to GB-CMFD.

Figure 13
Figure 13 depicts the variations in open loop gain with temperature.The GB-CMFD structure again shows the maximum magnitude of the open loop gain at different temperatures in comparison to other structures.

Figure 13
Figure 13 depicts the variations in open loop gain with temperature.The GB-CMFD structure again shows the maximum magnitude of the open loop gain at different temperatures in comparison to other structures.

Table 1 .
Power consumption, current drawn, and rise and fall times of the modified GB-CMFD.

Table 1 .
Power consumption, current drawn, and rise and fall times of the modified GB-CMFD.

Table 2 .
Power consumption, gain error, slew rate, and closed and open loop gain of the modified GB-CMFD at different temperatures.

Table 2 .
Power consumption, gain error, slew rate, and closed and open loop gain of the modified GB-CMFD at different temperatures.

Table 2 .
Power consumption, gain error, slew rate, and closed and open loop gain of the modified GB-CMFD at different temperatures.

Table 3 .
Comparison of results at 25 • C.

Table 4 .
Percentage variation with temperature.

Table 5 .
Comparison of simulations results at 25 • C.

Table 5 .
Comparison of simulations results at 25 °C.

Table 6 .
Percentage variations in parameters when the temperature changes from −5 to 55 °C.

Table 7 .
Comparison with other associated studies.

Table 6 .
Percentage variations in parameters when the temperature changes from −5 to 55 • C.

Table 7 .
Comparison with other associated studies.