Low Power Electronics and Applications Sotb Implementation of a Field Programmable Gate Array with Fine-grained Vt Programmability †

Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB 189 (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.


Introduction
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories.By this reconfigurability, various applications, such as prototyping, automotive, consumer products, mobile devices, industrial equipment, military equipment, aerospace applications, video/picture processing and telecommunication, can be performed on FPGAs.Another attractive point of FPGA is that the logic implementation on FPGAs needs no mask production for front-end design in ASICs.The system embedding FPGAs, promising an overall lower non-recurring engineering (NRE) cost, has cost benefits in comparison with ASIC-based systems.Moreover, FPGAs can be fabricated by advanced semiconductor process technologies, resulting in the reduction of chip costs and the improvement of device performance by rapidly shrinking the silicon die area, because FPGAs ensure a high-volume production capability, due to the implementability of many types of applications.However, the silicon area of FPGAs becomes lager than that of ASICs generally because FPGAs integrate many silicon resources, e.g., programmable interconnects, logic elements and configuration memories, to maintain the feasibility of many types of applications.While the increase of the silicon area, which lengthens interconnection wires, reduces the operating speed of mapped circuits on FPGAs, longer interconnection wires consume more dynamic power.This is one of the reasons why FPGAs are applied to advanced semiconductor process technologies aggressively.
One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption [1].Static leakage is a serious problem in FPGAs, partly because of the rich and redundant circuit resources provided for flexible programmability and partly because of the lack of a multi-threshold voltage (Vt) optimization capability for the sake of its field-programmability.Previously, techniques to reduce the static leakage current in FPGAs were aggressively examined.It is shown in [2] that the look-up-table (LUT) leakage is reduced by setting a higher threshold voltage (Vt) to static random access memories (SRAMs).In [3], various low-leakage techniques, such as redundant SRAM design, dual Vt design, body biasing and gate biasing, are evaluated.As described in [4], cutting off the power supply of an unused region by sleep transistors aims at reducing the logic slice leakage, which occupies 45% of the total leakage in their FPGA, while the assignment of a higher Vt to the configuration SRAM reduces 98% of the SRAM leakage, while increasing the configuration time by 20%.A routing switch in [5] can reduce the leakage current by 40% and 61% in low-power mode and sleep mode, respectively.The interconnection with fine-grained power-gating technique reduces the total power by 38% in [6].It is shown in [7] that the heterogeneous routing architecture reduces standby power by 33% without any area penalty and at the cost of less than a 5% performance degradation.A standby power reduction by 99% by using low-leakage memories and the power-gating technique is presented in [8].On the other hand, our Flex Power FPGA technique [9] uses a body biasing technique to implement the fine-grained programmability of the Vt of the FPGA building block circuits, such as LUT and multiplexer (MUX).A low-Vt state is assigned only to the building blocks along the critical path of the user application design based on the analysis of the design, while the high-Vt state is assigned to the greater part of the FPGA.As a result, a drastic reduction of the static power consumption can be expected.The key factors to attain good static leakage power reduction performance are: (1) a higher sensitivity of the Vt in the transistor to the back gate bias; (2) a fine grain size of the Vt control domain; and (3) the nature of the critical path of the application design.
The SOTB (silicon on thin buried oxide) transistor [10] has an excellent Vt controllability.Compared with the bulk MOS transistor, a wider variation range of the threshold voltage is promised in principle, because it is formed using a thinner buried oxide under a lightly-doped and fully-depleted body region.The SOTB structure is ideal for Flex Power FPGA to attain better static power reduction performance than bulk technology.
After the development of generations of the conventional bulk transistor implementation of Flex Power FPGA test chips [11], the SOTB version of the Flex Power FPGA test chip is fabricated, and its functional test and performance evaluation are performed successfully by mapping the 32-bit binary counter circuit on the test chip.This paper is organized as follows.Section 2 gives overviews of the SOTB and Flex Power FPGA architecture.In Section 3, evaluation results of the operating speed, static leakage current and area-overhead in the fabricated chip are shown.Finally, in Section 4, this paper is concluded.

Silicon on Thin Buried Oxide (SOTB) Transistor
SOTB transistors, as shown in Figure 1a, have some advantages compared with the bulk MOS transistors.SOTB transistors allow a wide back-bias control range for low-power and high-performance applications, because a thinner buried oxide under the lightly-doped and fully-depleted body region is formed as an SOI structure.As a result, by applying this to the SRAM cells, the static noise margins (SNMs) are improved by adding back feedback from the back gate to the front gate [10].Moreover, SOTB has the smallest threshold voltage variability among bulk MOS, due to its low-dose channel [12].
Figure 1b shows the SPICE simulation results of on-currents and off-currents to the back-bias voltage for the range from 0 V to −1.0 V in a bulk NMOS transistor and an SOTB NMOS transistor in 65-nm technology.Each on-current value is normalized by the on-current value in the case that a back-bias voltage of 0 V is applied.The same manner holds for off-currents.The off-current of the SOTB transistor shifts more than an order of magnitude by applying −1 V to the back gate, while that  ower FPGA shows the here is a di [11] to the th 11 × 11 self via wire   placer and router.GGEN generates a routing resource graph that reflects the FPGA architecture.Then, logic synthesis and packing need to be performed beforehand for a target circuit.CNV translates and generates information for placement and routing phases.Next, placement and routing are subsequently performed by VP and VR, respectively.After that, VTM analyzes all signal paths and obtains the timing slack information in the user application design mapped on the Flex Power FPGA.Following this, timing slack is reduced on non-critical paths by slowing down the blocks in those paths.This is achieved by assigning the HVT state to as many Vt control domains as possible, while assigning the LVT state to the Vt control domains along the critical signal paths to keep the operation speed constant.Figure 9 shows an example of the VTM behavior [9].As shown in Figure 9a, the Vt of all nodes is set to LVT at the initial state.Then, the first step of the back tracing algorism in VTM is done, as shown in Figure 9b.The Vt of node on the critical path remains LVT, while unused DFF is set to HVT.Next, HVT is assigned to nodes having a large slack in Figure 9c.Finally, the VTM algorism is completed, as shown in Figure 9d.memory is only 3%.The Vt configuration memory, body bias circuit and separation margin occupies 1%, 26% and 16% of an FPGA tile area, respectively.An area overhead to control the Vt of an elemental circuit with a fine granularity becomes 43% of an FPGA tile area.The grain resolution for the Vt control is necessary to examine, because it directly affects the FPGA tile area.Figure 12b shows the breakdown of the static leakage current.The elemental circuits are applied to a zero body bias, resulting in the threshold voltage of the built-in state.The elemental circuits and configuration memory consume 93% of the static leakage current in an FPGA tile.On the other hand, the extra leakage current caused by the Vt configuration memory and body bias circuit is only 7%.This is because the body bias circuit is always applied to the reverse body bias, resulting in the higher Vt state, while the bias voltage selector is designed by a high-voltage transistor.

Conclusions
The field programmable gate array (FPGA) is a promising target for advanced semiconductor technologies.However, static leakage is a serious problem in FPGAs.We have proposed an FPGA with fine-grained programmable body biasing, called the Flex Power FPGA, for static leakage power reduction.For further static power reduction, an excellent Vt controllability of the SOTB transistors can help a lot.The SOTB implementation of the Flex Power FPGA test chip is reported in this paper.The maximum operating frequency measurement results show that the operating speed can be widely controlled by the LVT bias, while the operating speed remains constant against the change in the HVT bias.Moreover, in the static leakage current measurement, the three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors.A 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.The huge improvement of the static leakage reduction over 10× to 20× with the bulk version is obtained.The effectiveness of the Flex Power FPGA and the excellent Vt controllability of the SOTB transistor are clearly shown.The Flex Power FPGA is an important application target for this novel device.
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Figure 12 .
Figure 12.The breakdown of (a) the area and (b) the static leakage current in an FPGA tile.