A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology

: In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 µ m CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm 2 , excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from − 80.7 to − 84.5 dBc/Hz at a 1 MHz offset frequency.


Introduction
Multi-band and multi-standard systems have recently drawn much attention because of their capability for high-data-rate transmission.To achieve advanced communication systems such as the Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz bands, a wideband solution is more flexible and less complex than a combination of multiple narrow-band ones.The demand for voltage-controlled oscillators (VCOs) capable of operating at several frequency bands to provide pure sinusoidal signals with compact size, low DC power consumption, and low phase noise at the same time has been constantly increasing [1][2][3].Some VCOs used switched-capacitor arrays to increase their frequency tuning range [4,5].However, their improved tuning ranges were less than 55%, and they occupied large chip areas due to the purely passive inductors in the LC tank.On the other hand, the use of active inductors in differential CMOS VCOs not only increases the tuning range and quality (Q) factors but also achieves compact designs [6][7][8][9][10].Active inductors based on gyrators use an additive capacitor [6] or CMOS inverters [7] to further increase their Q factors and inductances.Nevertheless, their frequency tuning ranges were still limited to 81%.Another technique used fixed feedback resistors and grounded capacitors in the gyrators of the VCO to obtain 127% frequency tuning with good phase noise [8].However, it required a moderate DC consumption and a large core area because of the grounded capacitors.Other techniques include a high-Q differential active inductor (DAI) with negative resistance realized by using a cascode structure with feedback resistance or current-mirror feedback networks [8,9].Although post-layout simulation of the high-Q DAI required low power dissipation, it did not propose any practical circuit with the DAI, and the design feasibility was not validated by practical measurement either [8].A gyrator-based active inductor for the single-ended Hartley VCO was also proposed [11].Still, its frequency tuning range and power dissipation was moderate compared with others in the literature.As mentioned above, most of the previously reported active and tunable inductors utilized gyrator-based inductors to achieve high-Q performances.
In this paper, a wideband CMOS VCO using an active-inductor topology in an NMOS cross-coupled pair is presented.The active inductor with a tunable resistor in the series feedback path can further increase the equivalent inductance and decrease the equivalent resistance.Therefore, a compact, wideband, and low-DC-dissipation VCO can be obtained.The derivation and analysis of the proposed active inductor are also detailed.The paper is organized as follows.Section 2 provides the details of the design method and simulations of the VCO.Section 3 describes the implementation and measurement of the design.Finally, Section 4 concludes this work.

Circuit Design and Simulation
An active resistor (AR) is mainly used in the application of large signal circuits and attenuators because it allows for very subtle adjustments.The proposed active inductor (AI) circuit has a feedback resistor, which is used to enhance the inductance and improve the Q factors.If one of the feedback resistors is replaced by the AR, the inductance-tuning range can also be increased.Figure 1a shows the proposed active resistor, which consists of an NMOS transistor (M R ) and a purely passive resistor (R f ).Different channel widths (W) of the transistor result in different resistances.With a V tune of 2.2 V and a channel width from 4 µm to 36 µm, the simulated variations of the AR range from 16 Ω to 123 Ω, as shown in Figure 1b.Typically, a transistor with a smaller channel width achieves a higher resistance.The channel width of 4 µm is used because it can provide up to more than 120 Ω feedback resistance, which translates into a high quality factor of the proposed active inductor at the frequencies of interest.Figure 1c plots the simulated frequency responses of the resistances of the NMOS with a 4 µm channel width subjected to different tuning voltages, V tune .It is noted that the resistances can be tuned from 118 Ω to 138 Ω by controlling V tune from 2.7 V to 1.7 V.
ended Hartley VCO was also proposed [11].Still, its frequency tuning range and power dissipation was moderate compared with others in the literature.As mentioned above, most of the previously reported active and tunable inductors utilized gyrator-based inductors to achieve high-Q performances.
In this paper, a wideband CMOS VCO using an active-inductor topology in an NMOS cross-coupled pair is presented.The active inductor with a tunable resistor in the series feedback path can further increase the equivalent inductance and decrease the equivalent resistance.Therefore, a compact, wideband, and low-DC-dissipation VCO can be obtained.The derivation and analysis of the proposed active inductor are also detailed.The paper is organized as follows.Section 2 provides the details of the design method and simulations of the VCO.Section 3 describes the implementation and measurement of the design.Finally, Section 4 concludes this work.
Figure 2b,c show the simulated inductances and Q factors of the proposed AI under different V DD3 and V DD4 bias conditions.Comparing a V DD3 of 1.6 V to a V DD3 of 1.9 V with the same V DD4 of 1.53 V in Figure 2b, the small V DD3 of 1.6 V will lead to a larger peak inductance, which corresponds to the results of Figure 1c and Equation (1).Moreover, a high DC power consumption or a large V DD4 value results in a large g m2 , a lower inductance and a higher self-resonance frequency.Typically, peak Q factors of a purely passive inductor in standard CMOS processes are about 10. Meanwhile the simulated peak Q factors of the AI are up to several hundred from 0.8 GHz to 3.4 GHz.In addition, the circuit demonstrates adjustable capabilities in inductances and quality factors.Figure 3 shows the proposed CMOS VCO based on the active-inductor and activeresistor topology.The NMOS cross-coupled pair consists of transistors M 11 and M 12 ; this provides a negative resistance so that the circuit can achieve stable oscillation conditions.The LC tank is formed by the two active inductors, two varactors (C var ) and the control voltage V ctrl for controlling the varactors.Transistors M 13 and M 14 are used to stabilize the current of the circuit.Capacitors C 4 and C 5 block the direct current between the core circuit and the output buffers.The buffers are the inverting amplifiers consisting of the feedback resistors (R 3 and R 4 ).The two AIs are directly connected to the cross-coupled pairs which form a current-reuse topology.Furthermore, to reduce power consumption, smaller transistors M 7 and M 10 are preferred.All the circuit parameters in Figure 3 are tabulated in Table 1.
J. Low Power Electron.Appl.2024, 14, x FOR PEER REVIEW 5 of 9 Figure 3 shows the proposed CMOS VCO based on the active-inductor and active-resistor topology.The NMOS cross-coupled pair consists of transistors M11 and M12; this provides a negative resistance so that the circuit can achieve stable oscillation conditions.The LC tank is formed by the two active inductors, two varactors (Cvar) and the control voltage Vctrl for controlling the varactors.Transistors M13 and M14 are used to stabilize the current of the circuit.Capacitors C4 and C5 block the direct current between the core circuit and the output buffers.The buffers are the inverting amplifiers consisting of the feedback resistors (R3 and R4).The two AIs are directly connected to the cross-coupled pairs which form a current-reuse topology.Furthermore, to reduce power consumption, smaller transistors M7 and M10 are preferred.All the circuit parameters in Figure 3 are tabulated in Table 1.

Implementation and Measurement
The chip is implemented in a standard mixed-signal/RF bulk 0.18 µm CMOS process that is provided by TSMC (Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan).The process provides one poly and six metal layers (1P6M), and all the implemented capacitors are metal-insulator-metal (MIM) capacitors.To avoid the IR drop effect and minimize resistive losses, wide power lines of 30 µm are used.In addition, the lines are realized on the top metal layer (M6), which is made up of 2.3 µm thick AlCu.Moreover, on-chip bypass capacitors for reducing low-frequency noises are also placed around the power lines.The circuit features differential outputs; therefore, a symmetrical layout is adopted.Figure 4 shows the chip photo of the fabricated VCO with a chip area of 0.81 mm 2 , including all testing pads, and its core area is merely 0.046 mm 2 .On-wafer measurements were conducted on a probing station MPITS200, along with a Three Agilent Table 1.Design parameters of the proposed CMOS VCO.

Implementation and Measurement
The chip is implemented in a standard mixed-signal/RF bulk 0.18 µm CMOS process that is provided by TSMC (Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan).The process provides one poly and six metal layers (1P6M), and all the implemented capacitors are metal-insulator-metal (MIM) capacitors.To avoid the IR drop effect and minimize resistive losses, wide power lines of 30 µm are used.In addition, the lines are realized on the top metal layer (M6), which is made up of 2.3 µm thick AlCu.Moreover, on-chip bypass capacitors for reducing low-frequency noises are also placed around the power lines.The circuit features differential outputs; therefore, a symmetrical layout is adopted.Figure 4 shows the chip photo of the fabricated VCO with a chip area of 0.81 mm 2 , including all testing pads, and its core area is merely 0.046 mm 2 .On-wafer measurements were conducted on a probing station MPITS200, along with a Three Agilent E3617A DC power supply and an Agilent E5052B signal-source analyzer.The Agilent power supply can offer precise two-decimal-place voltage; therefore, the tuning range of the VCO can be measured correctly.Two groups of 9-pin DC probes and RF probes were also used to characterize the circuit performances.Since VCO is differential, only one output port was measured.Therefore, one output port was connected to the analyzer for measurements with the other output port terminated by a 50 Ω load.The undesired parasitics of the pads and interconnections were calibrated by a de-embedding procedure.
J. Low Power Electron.Appl.2024, 14, x FOR PEER REVIEW E3617A DC power supply and an Agilent E5052B signal-source analyzer.The power supply can offer precise two-decimal-place voltage; therefore, the tuning the VCO can be measured correctly.Two groups of 9-pin DC probes and RF prob also used to characterize the circuit performances.Since VCO is differential, only put port was measured.Therefore, one output port was connected to the anal measurements with the other output port terminated by a 50 Ω load.The undesi asitics of the pads and interconnections were calibrated by a de-embedding proce While operating at the supply voltage (VDD1) of 1.6 V and a VDD2 of 0.53 V, th tuned from 0.53 V to 3.53 V, and VDD3 is tuned from 1.4 to 2.7 V. In this condition, t consumes around 6.8~10.1 mW, excluding the two output buffers.Figure 5 pres measured frequency tuning range of the VCO.In general, the oscillation frequenc from 0.73 GHz to 3.1 GHz by adjusting the two control voltages (VDD4 and VDD3) of th inductors and active resistors.It is also noted that the VCO consumes high DC p high oscillation frequencies; namely, the DC power consumption of the line with VD V and VDD3 = 2.7 V in Figure 5 is 10.1 mW.As shown in Figure 6, the measured outpu is −15.5 dBm at 2.23 GHz, and the resolution bandwidth, video bandwidth, and spa spectrum analyzer are 1 MHz, 10 MHz, and 100 MHz, respectively.Under a fixed 1 and different VDD3,4 values as shown in Figure 5, the measured phase noise at differe lating frequencies from 1 kHz to 10 MHz offset frequency are plotted in Figure 7. Th ured phase noise from the 0.82 GHz, 2.23 GHz, and 2.49 GHz oscillating signals a −84.5, and −83 dBc/Hz at a 1 MHz offset from the carriers, respectively.It is noted measured phase noise does not follow the conventional 1/f 3 and 1/f 2 decade, espec tween the 1 kHz and 100 kHz offset frequencies.This poor phase noise below the offset frequency could have resulted from the coupling effect between the intercon and noise from the active inductors.Besides flicker noise, the induced noise in the also includes shot noise and thermal noise.Therefore, the measured output spec Figure 6 features some fluctuations.Table 2 summarizes the performances of the p VCO and other previously reported CMOS VCOs based on the active-inductor top As shown in the Table 2, the two 130 nm CMOS VCOs feature a lower PDC and tuning range since the advanced process offers better trans-conductance (gm), whic the active and tunable inductor directly.The common FOM and FOMT are also fairly compare these VCOs [12].It is observed that this work achieves lower DC pow While operating at the supply voltage (V DD1 ) of 1.6 V and a V DD2 of 0.53 V, the V DD4 is tuned from 0.53 V to 3.53 V, and V DD3 is tuned from 1.4 to 2.7 V. this condition, the VCO consumes around 6.8~10.1 mW, excluding the two output buffers.Figure 5 presents the measured frequency tuning range of the VCO.In general, the oscillation frequencies vary from 0.73 GHz to 3.1 GHz by adjusting the two control voltages (V DD4 and V DD3 ) of the active inductors and active resistors.It is also noted that the VCO consumes high DC power at high oscillation frequencies; namely, the DC power consumption of the line with V DD4 = 2.53 V and V DD3 = 2.7 V in Figure 5 is 10.1 mW.As shown in Figure 6, the measured output power is −15.5 dBm at 2.23 GHz, and the resolution bandwidth, video bandwidth, and span of the spectrum analyzer are 1 MHz, 10 MHz, and 100 MHz, respectively.Under a fixed 1 V of V ctrl and different V DD3,4 values as shown in Figure 5, the measured phase noise at different oscillating frequencies from 1 kHz to 10 MHz offset frequency are plotted in Figure 7.The measured phase noise from the 0.82 GHz, 2.23 GHz, and 2.49 GHz oscillating signals are −80.7,−84.5, and −83 dBc/Hz at a 1 MHz offset from the carriers, respectively.It is noted that the measured phase noise does not follow the conventional 1/f 3 and 1/f 2 decade, especially between the 1 kHz and 100 kHz offset frequencies.This poor phase noise below the 1 MHz offset frequency could have resulted from the coupling effect between the interconnections and noise from the active inductors.Besides flicker noise, the induced noise in the LC tank also includes shot noise and thermal noise.Therefore, the measured output spectrum in Figure 6 features some fluctuations.Table 2 summarizes the performances of the presented VCO and other previously reported CMOS VCOs based on the active-inductor topologies.As shown in the Table 2, the two 130 nm CMOS VCOs feature a lower P DC and a wider tuning range since the advanced process offers better trans-conductance (g m ), which affects the active and tunable inductor directly.The common FOM and FOM T are also listed to fairly compare these VCOs [12].

2 . 7 RFigure 1 .
Figure 1.(a) The tunable active-resistor topology.(b) The resistance versus different sizes (channel width) with a Vtune of 2.2 V. (c) The resistance versus different tuning voltages of Vtune with a channel width of 4 µm.

Figure 1 .
Figure 1.(a) The tunable active-resistor topology.(b) The resistance versus different sizes (channel width) with a V tune of 2.2 V. (c) The resistance versus different tuning voltages of Vtune with a channel width of 4 µm.

Figure 2 .
Figure 2. (a) The proposed active inductor with a built-in active resistor.(b) Simulated inductances of the AI with a VDD1 of 1.6 V and a VDD2 of 0.53 V. (c) Simulated Q factors of the AI.

Figure 2 .
Figure 2. (a) The proposed active inductor with a built-in active resistor.(b) Simulated inductances of the AI with a V DD1 of 1.6 V and a V DD2 of 0.53 V. (c) Simulated Q factors of the AI.

Figure 3 .
Figure 3. Complete schematic of the proposed CMOS VCO.

Figure 4 .
Figure 4.The photograph of the CMOS VCO.

Figure 4 .
Figure 4.The photograph of the CMOS VCO.

Figure 7 .
Figure 7. Measured phase noise of different oscillating frequencies under a fixed 1 V of V ctrl and different V DD3,4 , as shown in Figure 5.