Design of Current Equalization Circuit in Dual Ethernet Power Supply System

: A current-balancing circuit for a dual-channel Ethernet power supply system is designed in this paper, which can be used to solve the mismatch between the two channels caused by unavoidable factors, such as mismatched resistances, temperatures and voltages. Based on the design, the mismatch of the currents between the two power transmission paths can be controlled to be less than 1% of the original ones. It can be operated under these conditions with the changes of the load current and the PSE output voltage. The maximum output power of the dual-channel power supply can reach up to 96.5 W. When the DC–DC conversion efﬁciency is less than 75%, it can still provide 72 W for the PD end, meeting the requirements of the PoE power system. The current-balancing circuit designed in the paper has potential application value to improve the dual PoE power supply system.


Introduction
Power over Ethernet (PoE) is an advanced technology that utilizes an Ethernet cable to realize the dual transmission of power and data.It is compatible with the existing Ethernet cabling infrastructure.The power system can be installed easily, which can reduce the cost required for equipment installation and maintenance [1].
The PoE system consists of power supply equipment (PSE) and power receiving equipment (PD) [2] to realize real-time monitoring of various power consumption in the power grid.PSE is a device composed of Ethernet switches and hubs, which transmits power and data signals to the twisted pair of the LAN through the hub.The PSE equipment undertakes the important responsibilities of PD query, power supply and power planning management.The PD control chips that meets IEEE802.3af/atstandards have been promoted by Texas Instruments, Linear Technology and Maxim [3][4][5][6][7][8].Compared to [3][4][5][6][7], a power MOSFET is integrated in the design proposed in Ref. [8].However, because it only supports a low output power (6.49W), the application range is limited.In order to meet various performance requirements of PD, Li Yongyuan et al. proposed an integrated PoE interface and DC-DC controller, which was optimized for the isolated converter to achieve a precise current limitation, a high power efficiency, a high voltage accuracy and a fast load step response [9].
In 2003, the IEEE 802.3af standard was formulated by the PoE Group of the Institute of Electrical and Electronics Engineers (IEEE) and includes two linear power supply modes [10].The first mode is to supply power to the idle pair, in which 4|5 and 7|8 are two pairs of cable lines for power transmission, with the provision of 4|5 for the positive pole and 7|8 for the negative pole.The other mode is to supply power to the data pair.The 1|2 and 3|6 twisted pairs are used for power transmission.The power supply polarity of the mode is arbitrary [10].With the wide application of wireless LAN in offices and homes, Zargari, M et al. proposed a single-chip dual-band three-mode CMOS transceiver that supports IEEE 802.11a/b/gWLAN standard [11].
The IEEE 802.3af standard can provide the maximum available power of 12.95 W to the RJ45 socket at the input end of the receiving device.This limitation prevents PoE from powering large power application scenarios.Since industrial products require greater power and higher conversion efficiency [12], it is necessary to provide higher power levels.On the basis of a compatibility with IEEE 802.3af, the IEEE 802.3at standard was proposed in 2009, which increased the maximum usable power from 12.95 W to 25.5 W [13].
To meet the demand for higher power in applications such as Wi-Fi access points, surveillance cameras and connected LED lighting, the industry has published a new IEEE 802.3bt standard [14,15], as shown in Figure 1.At the same time, non-IEEE standard methods such as CISCO's [16] or LTPOE++ [17] of UPOE Linear Technology have been published [18].and homes, Zargari, M et al. proposed a single-chip dual-band th transceiver that supports IEEE 802.11a/b/gWLAN standard [11].
The IEEE 802.3af standard can provide the maximum available pow the RJ45 socket at the input end of the receiving device.This limitati from powering large power application scenarios.Since industrial greater power and higher conversion efficiency [12], it is necessary t power levels.On the basis of a compatibility with IEEE 802.3af, the IEEE was proposed in 2009, which increased the maximum usable power from W [13].
To meet the demand for higher power in applications such as Wi surveillance cameras and connected LED lighting, the industry has IEEE 802.3bt standard [14,15], as shown in Figure 1.At the same time, no methods such as CISCO's [16] or LTPOE++ [17] of UPOE Linear Techn published [18].[22] between the cables, connectors and compo power conduction paths causes the maximum available power to be de rent may flow backward from one pair of cables to the other.Therefore the two currents [23,24] is the problem that needs to be solved for the d system.
A new two-channel current-balancing circuit is designed in the pap obvious effect on improving the reliability of a two-channel PoE powe The contents of the paper is organized as follows: the second part fo al-power supply Ethernet network modeling analysis, the third part m the design of the dual equalizer circuit and simulation results, the fourt the overall simulation results and experimental results.The fifth par conclusions.

Steady-State Modeling and Analysis of PoE System
The schematic of the PSE-PD interface is shown in Figure 2a.The p transformers T1-T4, Ethernet cables P12-P78, two rectifier bridges for adj  In 2012, Wu Jiande's team of Zhejiang University proposed a method to add loops in PoE infrastructure and use two DC-DC converters to achieve current balance [19].Huang Jianyu et al. proposed a 90 W high-power Ethernet power supply system [20].In 2017, Xiao Zhiming et al. proposed a balancing circuit based on MOS rectifier diodes [21].In practice, a mismatch [22] between the cables, connectors and components of the two power conduction paths causes the maximum available power to be derated, or the current may flow backward from one pair of cables to the other.Therefore, how to balance the two currents [23,24] is the problem that needs to be solved for the dual-channel PoE system.
A new two-channel current-balancing circuit is designed in the paper, which has an obvious effect on improving the reliability of a two-channel PoE power supply system.The contents of the paper is organized as follows: the second part focuses on the dual-power supply Ethernet network modeling analysis, the third part mainly introduces the design of the dual equalizer circuit and simulation results, the fourth part introduces the overall simulation results and experimental results.The fifth part gives the main conclusions.

Steady-State Modeling and Analysis of PoE System
The schematic of the PSE-PD interface is shown in Figure 2a.The ports include four transformers T1-T4, Ethernet cables P 12 -P 78 , two rectifier bridges for adjusting the power polarity of the Ethernet cable, and two for the PD connection to the PoE system.According to the IEEE 802.3af/at standard, the information data are transmitted through the transformer T1-T4 of the data pair P 12 and P 36 , and PSE can use the same data pair or spare P 45 and P 78 to provide power to the load through the diode bridge [25].For the dual power supply structure [19], its equivalent circuit, including the parasitic resistances, is shown in Figure 2c.In the figure, R12 and R36 denote the cable resistances from data to P12 and P36, respectively.R45 and R78 denote the cable resistances of spare data to P45 and P78, respectively.RT1-RT4 are the transformer resistances.RBR1 and RBR2 are diode bridge resistors.Rw1 and Rw2 are resistors on switches Sw1 and Sw2 in the PSE.Rw3 and Rw4 are on-resistors on switches Sw3 and Sw4.VBR1 and VBR2 are the forward voltage drops on the two diode bridges.VPSE is the voltage on the PSE.
If the sum of the two currents is IP, and the currents on path 1 and path 2 are IP1 and IP2, respectively, we obtain: In order to simplify the analysis, the resistance of the two paths is represented by RA and RB, respectively, and the specific expression is as follows: From Equations ( 1) and (2), the expressions of IP1 and IP2 can be obtained as follows: In order to reduce the transmission energy consumption and packet delay [26] to increase the power capability, the method of dual power supply is adopted to connect ports A, B, C and D to ports a2, b2, c2 and d2 corresponding to the PD interface structure in Figure 2b.
For the dual power supply structure [19], its equivalent circuit, including the parasitic resistances, is shown in Figure 2c.In the figure, R 12 and R 36 denote the cable resistances from data to P 12 and P 36 , respectively.R 45 and R 78 denote the cable resistances of spare data to P 45 and P 78 , respectively.R T1 -R T4 are the transformer resistances.R BR1 and R BR2 are diode bridge resistors.R w1 and R w2 are resistors on switches S w1 and S w2 in the PSE.R w3 and R w4 are on-resistors on switches S w3 and S w4 .V BR1 and V BR2 are the forward voltage drops on the two diode bridges.V PSE is the voltage on the PSE.
If the sum of the two currents is IP, and the currents on path 1 and path 2 are IP1 and IP2, respectively, we obtain: In order to simplify the analysis, the resistance of the two paths is represented by RA and RB, respectively, and the specific expression is as follows: From Equations ( 1) and ( 2), the expressions of IP1 and IP2 can be obtained as follows: According to the IEEE standard, the maximum value of the cable resistance mismatch is 3% [27].In the circuit shown in Figure 2c, V BR1 = 0.65 V, V BR2 = 1 V, R A = 9.84 Ω, R B = 7.71 Ω and the maximum current difference under different load conditions can be calculated.The relationship between the loop current and the input power is shown in Figure 2d.The results show that the average current per path is about 700 mA, and in the worst case, the maximum current difference can be up to 200 mA.The imbalance current may cause one of the paths to have an overcurrent, which would be shut down by the interface circuit.Eventually, the other path may also exceed the current limit.The PD may be shut down under the influence of the imbalance current.

PD Interface Structure
Based on the traditional PD interface structure, MOSFET transistors were used to replace the rectifier diode in the rectifier bridge in the designed interface system proposed in this paper [28].Its schematic is shown in Figure 3a, including the RJ45 interface, bridge rectifier current, current balancing module, bias and bridge control module and signature and classification module.The signature and classification modules are built according to IEEE 802.3at standard [13].The power transmission path of P 12 and P 36 (data pair) is called channel 1, while the power transmission path through P 45 and P 78 (idle pair) is called channel 2.
According to the IEEE standard, the maximum value of the cable resistance match is 3% [27].In the circuit shown in Figure 2c, VBR1 = 0.65 V, VBR2 = 1 V, RA = 9.84 Ω = 7.71 Ω and the maximum current difference under different load conditions ca calculated.The relationship between the loop current and the input power is show Figure 2d.The results show that the average current per path is about 700 mA, and i worst case, the maximum current difference can be up to 200 mA.The imbalance cu may cause one of the paths to have an overcurrent, which would be shut down by interface circuit.Eventually, the other path may also exceed the current limit.The may be shut down under the influence of the imbalance current.

PD Interface Structure
Based on the traditional PD interface structure, MOSFET transistors were use replace the rectifier diode in the rectifier bridge in the designed interface system posed in this paper [28].Its schematic is shown in Figure 3a, including the RJ45 inter bridge rectifier current, current balancing module, bias and bridge control module signature and classification module.The signature and classification modules are according to IEEE 802.3at standard [13].The power transmission path of P12 and P36 ( pair) is called channel 1, while the power transmission path through P45 and P78 pair) is called channel 2. The schematic diagram of the MOSFET acting as a rectifier device is shown in Fi 3b.In order to ensure the reliable initial starting of the circuit, the parasitic body dio the MOSFET is placed in the same direction as the conventional diode rectifier br [29].The gate voltage of PMOSFETs is regulated, and their channel resistance ca regulated by a current balancing module.Thus, the active PMOSFETs in the diode br module are modeled by the parallel adjustable resistors and body diodes in Figur The on-resistance of the MOSFET can be adjusted by changing the gate voltage in current balancing module.The schematic diagram of the MOSFET acting as a rectifier device is shown in Figure 3b.In order to ensure the reliable initial starting of the circuit, the parasitic body diode of the MOSFET is placed in the same direction as the conventional diode rectifier bridge [29].The gate voltage of PMOSFETs is regulated, and their channel resistance can be regulated by a current balancing module.Thus, the active PMOSFETs in the diode bridge module are modeled by the parallel adjustable resistors and body diodes in Figure 3b.The on-resistance of the MOSFET can be adjusted by changing the gate voltage in the current balancing module.
In the traditional rectifier bridge circuit, each diode has a certain voltage drop, which could increase the power loss.However, the MOSFET rectifier bridge shows a lower onresistance value compared with the rectifier diode, which can effectively reduce the power loss of the circuit [28].

Circuit Stability Analysis
In circuit design, power supply, process and temperature (PVT) are important factors that need to be paid attention to.In circuit design, the variations of the factors should be considered and be dealt with [30].
The power supply voltage sensitivity represents the degree to which the current source is affected by the change in the power supply voltage, denoted by S(I 0 , V P ) [31].I 0 is the output current of the current source, and V P is the power supply voltage.The parameter S(I 0 , V P ) represents the relative rate of change and can be written as: where ∂I 0 /I 0 is the relative change in output current, ∂V p /V p is the relative change in supply voltage, and ∂I 0 /∂V p is the partial derivative of I 0 with respect to V P .When V DD >> V GS , the output current of the current mirror I 0 is proportional to the supply voltage V DD .The power supply sensitivity can be changed to: In the traditional current mirror, the relative change in the output current is almost equal to the relative change in the supply voltage.The traditional current mirror cannot be used in the designed circuit because of its relative low sensitivity.Therefore, a reference current source with S(I 0 , V DD ) ≈ 0.06 used as threshold voltage was adopted in this paper.As shown in Figure 4, this current source was used to generate a reference current for the whole circuit; the specific principle is introduced in detail in Section 3.
lower on-resistance value compared with the rectifier diode, which can the power loss of the circuit [28].

Circuit Stability Analysis
In circuit design, power supply, process and temperature (PVT) tors that need to be paid attention to.In circuit design, the variations o be considered and be dealt with [30].
The power supply voltage sensitivity represents the degree to source is affected by the change in the power supply voltage, denote  is the output current of the current source, and V is the power s parameter ( ,  ) represents the relative rate of change and can be w ( ) where ∂ / is the relative change in output current, ∂ / is the supply voltage, and ∂ / ∂ is the partial derivative of  with respe When VDD >> VGS, the output current of the current mirror I is supply voltage VDD.The power supply sensitivity can be changed to: ( ) In the traditional current mirror, the relative change in the outpu equal to the relative change in the supply voltage.The traditional cur be used in the designed circuit because of its relative low sensitivity.ence current source with ( ,  ) ≈ 0.06 used as threshold voltage w paper.As shown in Figure 4, this current source was used to generate for the whole circuit; the specific principle is introduced in detail in Se In addition to the voltage sensitivity of the power supply, anoth cator of the current source is the temperature sensitivity.The small sensitivity, the less the circuit is affected by temperature in practical ap The temperature sensitivity of a current source is expressed as th the output current caused by each degree change in temperature.Th the relative temperature coefficient, which can be expressed as: In addition to the voltage sensitivity of the power supply, another important indicator of the current source is the temperature sensitivity.The smaller the temperature sensitivity, the less the circuit is affected by temperature in practical applications [22].
The temperature sensitivity of a current source is expressed as the relative change in the output current caused by each degree change in temperature.This change is called the relative temperature coefficient, which can be expressed as:

Design of Current-Balancing Circuit in Dual Ethernet Power Supply System
The control circuit of the rectifier bridge is used to control the switching of the rectifier MOSFETs in the rectifier bridge according to the power polarity of the output of the PSE end to ensure the normal operation of the PD end load.With the sampling of the two currents, the sampling resistance transmits the voltage difference to the current balancing module.The current balancing module and the finishing bridge control module can work together to control the gate voltage of the PMOS in the rectifier bridge with a high current and then change its on-resistance to balance the currents of the two channels.

Design of Bias Circuit Module
As shown in Figure 5a, a voltage V Z of 5 V and a stable reference current I O of 1.5 µA can be generated by the bias module for the entire current equalization circuit.According to the analysis in Section 2.3, the circuit uses a current mirror to replicate I1, and the copied current is only related to the width-to-length ratio of the MOS and is not sensitive to the interference of external factors such as temperature, which is conducive to the stable operation of the circuit in practical applications.The breakdown voltage of the regulator diode D Z is 5.6 V. Thus, the gate voltage of M N5 is clamped at 5.6 V.A voltage V Z of 5 V can be produced based on M N5 and Dz.M N6 , M N7 , R 1 and R 2 constitute the reference current source using the threshold voltage, and the current generated by it can be expressed as: w Power Electron.Appl.2023, 13, x FOR PEER REVIEW 6 of

Design of Current-Balancing Circuit in Dual Ethernet Power Supply System
The control circuit of the rectifier bridge is used to control the switching of the r tifier MOSFETs in the rectifier bridge according to the power polarity of the output of PSE end to ensure the normal operation of the PD end load.With the sampling of the t currents, the sampling resistance transmits the voltage difference to the current balanc module.The current balancing module and the finishing bridge control module can wo together to control the gate voltage of the PMOS in the rectifier bridge with a high curr and then change its on-resistance to balance the currents of the two channels.

Design of Bias Circuit Module
As shown in Figure 5a, a voltage VZ of 5 V and a stable reference current IO of 1.5 can be generated by the bias module for the entire current equalization circuit.Accord to the analysis in Section 2.3, the circuit uses a current mirror to replicate I1, and copied current is only related to the width-to-length ratio of the MOS and is not sensit to the interference of external factors such as temperature, which is conducive to the s ble operation of the circuit in practical applications.The breakdown voltage of the reg lator diode DZ is 5.6 V. Thus, the gate voltage of MN5 is clamped at 5.6 V.A voltage VZ o V can be produced based on MN5 and Dz.MN6, MN7, R1 and R2 constitute the referen current source using the threshold voltage, and the current generated by it can be pressed as: When the MN6 overdrive voltage V is small relative to the threshold voltage the output current is mainly determined by the threshold voltage V and R1.In order obtain a more stable output current, the aspect ratio of MN6 is set to be 16:1, R1 =500 k and the output current IO ≈ 1.5 µA.When the M N6 overdrive voltage V OV6 is small relative to the threshold voltage V t , the output current is mainly determined by the threshold voltage V t and R 1 .In order to obtain a more stable output current, the aspect ratio of M N6 is set to be 16:1, R 1 = 500 kΩ, and the output current I O ≈ 1.5 µA.
The bias V Z in Equation ( 7) can be calculated.According to the MOSFET overdrive voltage Equation (8) (Kn6 is the conductivity coefficient), Equation ( 9) can be obtained: I D6 is the source leakage current of M N6 .
Combining Equation (9) with Equation ( 5), the power sensitivity of the current source with the threshold voltage can be expressed as: The threshold voltage V T of M N6 is 794 mV, and the overdrive voltage V OV6 is 70 mV.
The power sensitivity is: The stability of the circuit was verified by a simulation.Figure 5b shows the simulation results.With V Z changing from 4.7 V to 5.1 V, the variation in the output current is within 0.01 µA.The key parameters of the bias circuit (Figure 5a) are listed in Table 1.

Design of Rectifier Bridge and Control Circuit Module
As shown in Figure 6a, a control circuit of a MOSFET rectifier bridge was designed.V TX and V SPARE+ are the voltages used by the Ethernet cable to transmit power to the two power transmission paths.The control signals V TX_HI , V RX_HI , V SP_HI and V SP+_HI are used to control M P6A-D and M N11A-D .The output currents I N1-4 and I P1-4 can be used to change the gate voltages of the MOSFETs in the bridge.The PMOS on the high-voltage side and the NMOS on the low-voltage side can be switched on to achieve the effect of rectification.
The voltage regulator diode D Z stabilizes the gate voltages of M N10A and M N10B at 5.6 V.When V TX and V SPARE+ have a high voltage, the two NMOS are turned on and the voltage of the input inverter is about 5 V.The threshold voltage of the inverter should be about 2.5 V.The voltage regulator diode DZ stabilizes the gate voltages of MN10A and MN10B at 5 V.When VTX and VSPARE+ have a high voltage, the two NMOS are turned on and t voltage of the input inverter is about 5 V.The threshold voltage of the inverter should about 2.5 V.
When (W/L)p = 4(W/L)N, r ≈ 1, the switching threshold of the inverter is set to be 2 V.The simulation waveform of the inverter is shown in Figure 6b.
The MOSFET rectifier bridge circuit [32] is shown in Figure 7a.VTX, VRX, VSPARE+ an VSPARE-represent the power transmitted by the cable.IP1-4 and IN1-4 are the control curren of the finishing bridge control module.The on-gate source voltage of the MOSFET in t rectifier bridge can be expressed as: (1 It can be seen that the VGS of the conducting MOSFET in the rectifier bridge When (W/L) p = 4(W/L) N , r ≈ 1, the switching threshold of the inverter is set to be 2.5 V.The simulation waveform of the inverter is shown in Figure 6b.
The MOSFET rectifier bridge circuit [32] is shown in Figure 7a.V TX , V RX , V SPARE+ and V SPARE-represent the power transmitted by the cable.I P1-4 and I N1-4 are the control currents of the finishing bridge control module.The on-gate source voltage of the MOSFET in the rectifier bridge can be expressed as: I , is the regulating current output of the current balancing module, which is used to balance the current in the two transmission paths.In order to reduce the power loss of the rectifier bridge, the on-conducting MOSFETs should be operated in the deep triode region to reduce their on-resistance (except for PMOS used to regulate the current imbalance).MP5A-D consists of a current mirror to replicate the current.The current value of each path in the current mirror is determined by the resistance value of the resistor.R3A,B is 500 Ω and R3A,B is 250 Ω.The source leakage current of MP5C,D is 3 µA.The current through the 4.8 MΩ resistance can produce a voltage drop of about 15 V, which shows enough margin to balance the current of the two paths.
When VTX is high, MP1 and MN2 are on-conduction, while MP2 and MN1 are cut off.When VRX is high, MP2 and MN1 are on, while MP1 and MN2 are off.As shown in Figure 7b, the input is AC and the output is DC, which ensures that the load side can be operated normally.Based on the simulation results, the maximum input voltage is 42 V.The maximum output voltage is 41.98 V.With the 0.02 V difference, the power loss can be obviously reduced compared with the traditional diode rectifier bridge.
The key parameters in Figure 6a and Figure 7a are listed in Table .2.

Design of Current Balancing Module
Figure 8a shows the working principle of the current-balancing circuit in a dual power-over-Ethernet system.Assuming that the inputs of VTX and VPSARE+ are high, and VTX > VSPARE+, one of the four PMOSs in the bridge rectifier circuit is used to adjust the two currents.The remaining on-conducting MOSFETs operate in the deep transistor region to reduce the power loss of the bridge.According to the input voltage polarity, MP1, MP3, MN2 and MN4 in the rectifier bridge are turned on, while MP2, MP4, MN1 and MN2 remain off.All MOSFETs except MP1 operate in the deep transistor region, and they can be equivalent to resistors.
In the case of an unexpected condition, assuming the current in channel 1 is greater than that in channel 2, the channel 1 is closed by the current limiting protection device in the Ethernet power supply system due to excessive current, resulting in a significant reduction in output power.In order to equalize the two currents, the resistors RS1 and RS2 sample the currents of the two paths and convert the current difference into a voltage difference.The voltage difference is transmitted into the current equalization module.The current equalization module outputs the corresponding regulation current IBN1 through the resistance RP1.The gate voltage of MP1 is reduced to convert it from the deep It can be seen that the V GS of the conducting MOSFET in the rectifier bridge is changed with the V GS of M N6 .It is not sensitive to the change in temperature anymore.I BN1,2 is the regulating current output of the current balancing module, which is used to balance the current in the two transmission paths.In order to reduce the power loss of the rectifier bridge, the on-conducting MOSFETs should be operated in the deep triode region to reduce their on-resistance (except for PMOS used to regulate the current imbalance).M P5A-D consists of a current mirror to replicate the current.The current value of each path in the current mirror is determined by the resistance value of the resistor.R 3A,B is 500 Ω and R 3A,B is 250 Ω.The source leakage current of M P5C,D is 3 µA.The current through the 4.8 MΩ resistance can produce a voltage drop of about 15 V, which shows enough margin to balance the current of the two paths.
When V TX is high, M P1 and M N2 are on-conduction, while M P2 and M N1 are cut off.When V RX is high, M P2 and M N1 are on, while M P1 and M N2 are off.As shown in Figure 7b, the input is AC and the output is DC, which ensures that the load side can be operated normally.Based on the simulation results, the maximum input voltage is 42 V.The maximum output voltage is 41.98 V.With the 0.02 V difference, the power loss can be obviously reduced compared with the traditional diode rectifier bridge.
The key parameters in Figures 6a and 7a are listed in Table 2.
Table 2. Key parameters in the rectifier bridge and bridge control circuit.

Design of Current Balancing Module
Figure 8a shows the working principle of the current-balancing circuit in a dual power-over-Ethernet system.Assuming that the inputs of V TX and V PSARE+ are high, and V TX > V SPARE+ , one of the four PMOSs in the bridge rectifier circuit is used to adjust the two currents.The remaining on-conducting MOSFETs operate in the deep transistor region to reduce the power loss of the bridge.According to the input voltage polarity, M P1 , M P3 , M N2 and M N4 in the rectifier bridge are turned on, while M P2 , M P4 , M N1 and M N2 remain off.All MOSFETs except MP1 operate in the deep transistor region, and they can be equivalent to resistors.circuits used in the device, a comprehensive consideration leads to a deviation of abo 0.4 V in the two paths.The on-voltage of the MP1-4 body diode used in the bridge rectifi circuit in this design is about 0.7 V, which can change the current mismatch caused by maximum 0.7 V voltage in the two paths and has enough ability to change the 0.4 V d viation in a practical application.The schematic diagram of the current-balancing circuit is shown in Figure 8b.and RS2 perceive the current difference in the two channels and convert the current in voltage.The currents are transmitted to the VS1 and VS2 ports of the current balanci circuit, respectively.Q1 and Q3 are common base amplifier circuits, which have c rent-following and good high-frequency characteristics.A bipolar transistor shows In the case of an unexpected condition, assuming the current in channel 1 is greater than that in channel 2, the channel 1 is closed by the current limiting protection device in the Ethernet power supply system due to excessive current, resulting in a significant reduction in output power.In order to equalize the two currents, the resistors R S1 and R S2 sample the currents of the two paths and convert the current difference into a voltage difference.The voltage difference is transmitted into the current equalization module.The current equalization module outputs the corresponding regulation current I BN1 through the resistance R P1 .The gate voltage of M P1 is reduced to convert it from the deep triode region to the triode region or the saturation region.The on-resistance is increased, and the V DS of M P1 is changed to balance the two currents.
According to the IEEE 802.3at standard, the maximum length of the cable is 100 m, the maximum resistance tolerance is ±3% [23], and the maximum current value of each transmission path is 1 A, so the maximum voltage difference between the PSE cable and the PSE-PD's two interfaces is about 250 mV.Due to the actual application of the two circuits used in the device, a comprehensive consideration leads to a deviation of about 0.4 V in the two paths.The on-voltage of the M P1-4 body diode used in the bridge rectifier circuit in this design is about 0.7 V, which can change the current mismatch caused by the maximum 0.7 V voltage in the two paths and has enough ability to change the 0.4 V deviation in a practical application.
The schematic diagram of the current-balancing circuit is shown in Figure 8b.R S1 and R S2 perceive the current difference in the two channels and convert the current into voltage.The currents are transmitted to the V S1 and V S2 ports of the current balancing circuit, respectively.Q 1 and Q 3 are common base amplifier circuits, which have currentfollowing and good high-frequency characteristics.A bipolar transistor shows a smaller impedance compared with a MOSFET, which can be better for the impedance coupling.Q 2 provides the same bias points for Q 1 and Q 3 , while Q 1 is isolated from Q 3 to avoid any signal coupling between the two channels.
∆I represents the current difference in the two transmission paths.The current difference between Q 1 and Q 3 is The current difference is added on the V N1 and V N2 routes by the replication of the current mirror.The current flowing through M P9A /M P10A is increased/decreased depending on the polarity of the current difference.Current mirrors M N14A-C and M N17A-C can duplicate the change in the current of Q 1 and Q 3 , while M P7A-B and M P8A-B duplicate the change in the current of Q 1 and Q 3 on the other side, respectively.
When the current in channel 1 is greater than the current in channel 2, the voltage V S1 is greater than V S2 .When the two currents are balanced, the collector currents of Q1 and Q3 increase and decrease, respectively.This change trend is reflected into M N14B,C and M N17B,C , respectively, through the current mirror, so that the current flowing through M N14B,C increases.The current flowing through M N17B,C decreases, while the current variation trend in M N14B and M N17B decreases the current of M P8A and increases the current of M P7A after passing through the current mirror, respectively.Thus, the current flowing through M P9A and M P10A increases and decreases, and the current mirrors M P9A,B , and M P10A,B replicate the increased current to I BN1 and I BN2 in a ratio of 1:5.I BN1 and I BN2 are inputted into the bridge control circuit in Figure 6a to increase and decrease I P1 and I P3 , respectively.The decrease in current flowing through R P1 causes the gate voltage of M P1 to increase, the conduction resistance to increase and the V DS to increase to change the imbalance of the two currents.The increased I P3 increases the V GS of M P3 and continues to work in the deep transistor region, reducing the power loss of the circuit.
In practical applications, with the unavoidable errors of the devices, an error-regulating circuit is designed, as shown in Figure 8b.Two pull-down current paths M N15 and M N16 are placed on V N1 and V N2 , respectively, to offset the errors caused by R S1 , R S2 , R G13 , Q 1 , Q 2 and Q 3 .The two pull-down trimmers are adjusted by adjusting the resistance values of the adjustable resistors R 15 and R 16 .M P9A and M P10A are connected in the form of diodes, so the impedance on V N1 and V N2 is relatively small.Because the impedance of the M N15 and M N16 pull-down current path is high, the frequency response of the original current balance circuit is not affected by the error-regulation circuit.
In the rectifier bridge circuit as shown in Figure 8b, the capacitor C 1-4 is used to compensate the stability of the loop.During each current-equalizing process, only one MOSFET in MP 1-4 is used to adjust the loop current.The current difference between the two paths after current balancing is: where ∆V PSE is the voltage difference between the PSE end and the two paths, ∆R CH is the cable resistance difference, and ∆V DS is the drain-to-source voltage difference of the MOS device in the rectifier bridge.After the adjustment of the current-balancing circuit, the current mismatch between the two channels is reduced.Figure 9 is a simulation in the worst-case scenario, with RCH1 and RCH2 being 0.5 Ω and the voltage difference between the two channels being 0.4 V.The low-frequency gain of the circuit is 52 dB, the gain is 400, and the phase margin is about 90

Dual Ethernet Power Supply Current-Balancing Circuit
Figure 10 shows the two currents under the condition that the volta increases from 0 V to 40 mV without the current-balancing module.Whe difference is 400 mV, the current difference between the two channels is practical applications, the large current will be turned off by the current limi the Ethernet power supply system, affecting the normal power supply of t  3.
Table 3. Key parameters of the devices in the current-balancing module.

Dual Ethernet Power Supply Current-Balancing Circuit
Figure 10 shows the two currents under the condition that the voltage difference increases from 0 V to 40 mV without the current-balancing module.When the voltage difference is 400 mV, the current difference between the two channels is 321 mA.In practical applications, the large current will be turned off by the current limiting circuit in the Ethernet power supply system, affecting the normal power supply of the entire system.increases from 0 V to 40 mV without the current-balancing module.Whe difference is 400 mV, the current difference between the two channels i practical applications, the large current will be turned off by the current lim the Ethernet power supply system, affecting the normal power supply of tem.With the introduction of the current-balancing module, the current difference is reduced to 0.65 mA and 0.91 mA at 200 mV and 400 mV, and the current mismatch is reduced to 0.2% without any equalization of voltage differences up to 400 mV. Figure 11c shows the situation when the voltage in channel 2 is higher than that in channel 1.The current equalization circuit of the designed dual power supply Ethernet system can be used when the PSE input is of different power polarity.
Figure 11a,b show the simulation results of the non-current-balancing circuit and the current-balancing circuit.Adding a voltage difference of 200 mV and 400 mV at 0.4 s and 0.7 s (assuming that the voltage in channel 1 is greater than that in channel 2) results in a current difference of 161 mA and 321 mA, respectively, in the absence of a current balancing module.With the introduction of the current-balancing module, the current difference is reduced to 0.65 mA and 0.91 mA at 200 mV and 400 mV, and the current mismatch is reduced to 0.2% without any equalization of voltage differences up to 400 mV. Figure 11c shows the situation when the voltage in channel 2 is higher than that in channel 1.The current equalization circuit of the designed dual power supply Ethernet system can be used when the PSE input is of different power polarity.In order to further test the reliability of the current equalization circuit of the dual Ethernet power supply, the conditions of input common-mode voltage variations and load current variations were simulated.
Under the conditions of the voltage difference of the input common-mode voltage of 400 mV, Figure 12a,b show the currents of the two channels with or without the current-balancing circuit.When there is no current-balancing circuit, the current difference between the two channels is 375.66 mA, as shown in Figure 12b.On the contrary, with the current-balancing circuit, the current difference between the two channels can be In order to further test the reliability of the current equalization circuit of the dual Ethernet power supply, the conditions of input common-mode voltage variations and load current variations were simulated.
Under the conditions of the voltage difference of the input common-mode voltage of 400 mV, Figure 12a,b show the currents of the two channels with or without the currentbalancing circuit.When there is no current-balancing circuit, the current difference between the two channels is 375.66 mA, as shown in Figure 12b.On the contrary, with the currentbalancing circuit, the current difference between the two channels can be reduced to 0.75 mA, as shown in Figure 12a.As shown in Figure 12c, when the load current is 600 mA, the current of channel 1 is 300.44 mA, and the current of channel 2 is 299.67 mA, the current difference between the two paths is 0.77 mA.At 550 ms, the load current is 900 mA.At that time, the current of channel 1 is 450.49mA, and the current of channel 2 is 449.62 mA.The current difference between the two channels is 0.87 mA.

Analysis of Output Power and Power Loss of Dual Ethernet Power Supply Current-Balancing Circuit
In order to verify the maximum output power and power loss of the circuit, the output current was varied from 0.6 A-2 A. Based on the IEEE standard, the maximum current per transmission channel is 1 A. Figure 13 shows that the output current is changed from 0.6 A to 2 A, and the output power is changed from 29.3 W to 96.5 W, accordingly.Assuming a DC-DC conversion efficiency of 75%, the maximum output power can provide 72 W of power to the PD end.The power loss is increased from 500 mW to 2.86 W.

Conclusions
PoE technology is popular in the market because of its advantages such as simplified wiring, energy saving and environmental protection.However, the traditional single-channel Ethernet power supply system cannot meet the high power demand of an electric appliance.The dual-channel Ethernet power supply system can provide more power.However, the imbalance of the two channels is one of the key problems and

Analysis of Output Power and Power Loss of Dual Ethernet Power Supply Current-Balancing Circuit
In order to verify the maximum output power and power loss of the circuit, the output current was varied from 0.6 A-2 A. Based on the IEEE standard, the maximum current per transmission channel is 1 A. Figure 13 shows that the output current is changed from 0.6 A to 2 A, and the output power is changed from 29.3 W to 96.5 W, accordingly.Assuming a DC-DC conversion efficiency of 75%, the maximum output power can provide 72 W of power to the PD end.The power loss is increased from 500 mW to 2.86 W.

Analysis of Output Power and Power Loss of Dual Ethernet Power Supply Curr Circuit
In order to verify the maximum output power and power loss of th output current was varied from 0.6 A-2 A. Based on the IEEE standard, t current per transmission channel is 1 A. Figure 13 shows that the outp changed from 0.6 A to 2 A, and the output power is changed from 29.3 W t cordingly.Assuming a DC-DC conversion efficiency of 75%, the maximum o can provide 72 W of power to the PD end.The power loss is increased from 2.86 W.

Conclusions
PoE technology is popular in the market because of its advantages such wiring, energy saving and environmental protection.However, the tra gle-channel Ethernet power supply system cannot meet the high power d

Figure 2 .
Figure 2. (a) Schematic of the PSE−PD interface structure; (b) schematic of the PD interface structure; (c) equivalent circuit of the transmission path structure; (d) relationship between the current and the power of the two channels.

Figure 2 .
Figure 2. (a) Schematic of the PSE−PD interface structure; (b) schematic of the PD interface structure; (c) equivalent circuit of the transmission path structure; (d) relationship between the current and the power of the two channels.

Figure 3 .
Figure 3. (a) Schematic of the PSE−PD interface structure.(b) Equivalentprinciple diagram of the rectifier bridge.

Figure 4 .
Figure 4. Reference current source using a threshold voltage.

Figure 4 .
Figure 4. Reference current source using a threshold voltage.

Figure 5 .
Figure 5. (a) Schematic diagram of the bias module.(b) The reference current source output us the threshold voltage varies with the voltage.

I 1 Figure 5 .
Figure 5. (a) Schematic diagram of the bias module.(b) The reference current source output using the threshold voltage varies with the voltage.

Figure 9 .
Figure 9. Simulation results of current−balancing circuit.Key parameters in Figure 8b are listed in Table3.

Figure 10 .
Figure 10.Influence of different voltage differences on the two currents.

Figure 10 .
Figure 10.Influence of different voltage differences on the two currents.

Figure
Figure11a,b show the simulation results of the non-current-balancing circuit and the current-balancing circuit.Adding a voltage difference of 200 mV and 400 mV at 0.4 s and 0.7 s (assuming that the voltage in channel 1 is greater than that in channel 2) results in a current difference of 161 mA and 321 mA, respectively, in the absence of a current balancing module.With the introduction of the current-balancing module, the current difference is reduced to 0.65 mA and 0.91 mA at 200 mV and 400 mV, and the current mismatch is reduced to 0.2% without any equalization of voltage differences up to 400 mV.Figure11cshows the situation when the voltage in channel 2 is higher than that in channel 1.The current equalization circuit of the designed dual power supply Ethernet system can be used when the PSE input is of different power polarity.

Figure 11 .
Figure 11.(a) Currents without current−-balancing module.(b) Currents with current−balancing module.(c) Currents on condition of larger voltage of channel 2 than channel 1.4.2.Disturbance Stability of Two-Channel Ethernet Power Supply Current Equalization Circuit

Figure 11 .
Figure 11.(a) Currents without current−-balancing module.(b) Currents with current−balancing module.(c) Currents on condition of larger voltage of channel 2 than channel 1.4.2.Disturbance Stability of Two-Channel Ethernet Power Supply Current Equalization Circuit

JFigure 12 .
Figure 12.(a) Currents of the two channels with the current-balancing circuit.(b) Currents of the two channels without the current-balancing circuit.(c) Currents of the two channels with different loads.

Figure 13 .
Figure 13.Analysis of the output power and the power loss.

Figure 12 .
Figure 12.(a) Currents of the two channels with the current-balancing circuit.(b) Currents of the two channels without the current-balancing circuit.(c) Currents of the two channels with different loads.

Figure 12 .
Figure 12.(a) Currents of the two channels with the current-balancing circuit.(b) C two channels without the current-balancing circuit.(c) Currents of the two channels loads.

Figure 13 .
Figure 13.Analysis of the output power and the power loss.

Figure 13 .
Figure 13.Analysis of the output power and the power loss.

Table 1 .
Key parameters of the bias circuit.

Table 2 .
Key parameters in the rectifier bridge and bridge control circuit.

Table 3 .
Key parameters of the devices in the current-balancing module.