Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

: The application of the ﬂipped voltage follower to implement two high-performance circuits is presented: (1) The ﬁrst is a class AB cascode ﬂipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional ﬂipped voltage follower. It has a small signal ﬁgure of merit FOM SS = 46 MHz pF/ µ W and a current efﬁciency ﬁgure of merit FOM CE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 G Ω output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary ampliﬁers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.


Introduction
Two of the basic building blocks of analog integrated circuits are the voltage follower and the current mirror. The conventional common-drain amplifier or voltage follower (denoted here as CONV_VF)) [1][2][3] of Figure 1a has been used for many years as a buffer due to its infinite input resistance, medium-low output impedance R out = 1/g m (in the order of tens of kΩs) close to the unity voltage gain, and relatively high bandwidth BW = g m /(2π C L ). The flipped voltage follower of Figure 1b [4] is an improved voltage follower that uses local negative feedback to provide lower output resistance R out = 1/[g m (g m r o )] = 1/(g m A) (hundreds of Ω), where C L is the load capacitance, g m and r o are the transconductance gain and output resistance, and A = g m r o is the intrinsic gain of the MOS transistor. The basic Flipped Voltage Follower(FVF) version of Figure 1b (denoted here as CONV_FVF) suffers the serious limitation that it has a very low peak-to-peak output swing V oswingpp , which is independent of the supply voltage and given by V oswingpp = V TH − V DSsat (where V TH is the threshold voltage and V DSsat is the drain-source saturation voltage of M FVF ). It operates in class A with a peak positive output current and positive slew rate limited by the bias current I bias to a value SR + = I bias /C L . Several versions of the flipped voltage follower have been reported with improved output range and lower output resistance. For example, the cascode FVF (denoted here as CONV_CSCFVF) shown in Figure 1c and 2 of 17 reported in [5] uses an additional branch with a cascode transistor M CAS that increases the local feedback loop gain and provides even lower output resistance by a factor A = g m r o so that, in this circuit, R out = 1/[g m (g m r o ) 2 ] = 1/[g m A 2 ] (on the order of tens of Ωs). It also has an increased output swing, which is dependent on the supply voltage and given by V outswingpp = V DD − (V GS + V DSsat ) = V DD − V TH − 2V DSsat . The cascode FVF of Figure 1c (denoted here as CONV_CSCFVF) is a class A circuit with a positive slew rate seriously limited by the bias current to a value: SR + = I bias /C L . Class AB versions of the FVF have also been reported [6][7][8][9] to overcome this limitation to a certain degree. limited by the bias current Ibias to a value SR + = Ibias/CL. Several versions of the flipped voltage follower have been reported with improved output range and lower output resistance. For example, the cascode FVF (denoted here as CONV_CSCFVF) shown in Figure 1c and reported in [5] uses an additional branch with a cascode transistor MCAS that increases the local feedback loop gain and provides even lower output resistance by a factor A = gmro so that, in this circuit, Rout = 1/[gm(gmro) 2 ] = 1/[gmA 2 ] (on the order of tens of Ωs). It also has an increased output swing, which is dependent on the supply voltage and given by Voutswingpp = VDD − (VGS + VDSsat) = VDD − VTH − 2VDSsat. The cascode FVF of Figure 1c (denoted here as CONV_CSCFVF) is a class A circuit with a positive slew rate seriously limited by the bias current to a value: SR + = Ibias/CL. Class AB versions of the FVF have also been reported [6][7][8][9] to overcome this limitation to a certain degree. The low-voltage cascode current mirror of Figure 2a (denoted here as CN_CS_CM) has been used for many years as a high-bandwidth linear current amplifier. It has a moderately low input resistance Rin = 1/gm (on the order of tens of kΩs), moderately high output resistance Rout = ro(gmro) = roA (on the order of tens of MΩs), high linearity, low gain error, low output compliance voltage (Voutmin = 2VDSSat), and moderate input voltage requirements Vin = VGS = VTH + VDssat. A simple rearrangement of the circuit of Figure 2a is shown in Figure 2b. It injects the input current source Iin at the source of the cascode transistor M1C (node Vx) instead of at its drain (node Vy). This reduces the input voltage requirements from VGS to VDSsat and leads to a reduction in the input resistance by a factor A from Rin = 1/gm to Rin = 1/[gm(gmro)] = 1/[gmA]. Notice that, in this circuit, the input transistors M1 and M1C form a flipped voltage follower with a constant input voltage Vcn at the The low-voltage cascode current mirror of Figure 2a (denoted here as CN_CS_CM) has been used for many years as a high-bandwidth linear current amplifier. It has a moderately low input resistance R in = 1/g m (on the order of tens of kΩs), moderately high output resistance R out = r o (g m r o ) = r o A (on the order of tens of MΩs), high linearity, low gain error, low output compliance voltage (V outmin = 2V DSSat ), and moderate input voltage requirements V in = V GS = V TH + V Dssat . A simple rearrangement of the circuit of Figure 2a is shown in Figure 2b. It injects the input current source I in at the source of the cascode transistor M 1C (node V x ) instead of at its drain (node V y ). This reduces the input voltage requirements from V GS to V DSsat and leads to a reduction in the input resistance by a factor A from R in = 1/g m to R in = 1/[g m (g m r o )] = 1/[g m A]. Notice that, in this circuit, the input transistors M 1 and M 1C form a flipped voltage follower with a constant input voltage V cn at the gate of M 1C and the current input signal I in injected at the output terminal of the FVF (node V x ). In spite of the improvement in the mirror characteristics, this modification suffers from a non-linear current mirror gain resulting from lambda effect and unequal drain source voltages in the input and output transistors M 1 and M 2 of the current mirror. This is due to the fact that the cascode input and output transistors M 1C and M 2C have unequal drain currents which cause their gate-source voltages to be different. The gate source voltages of M 1C and M 2C determine the drain-source voltages of M 1 and M 2 and the linearity of the mirror. This effect can be greatly mitigated in a BiCMOS process by replacing the cascode transistors by bipolar transistors.  In this paper, the authors introduce two improved circuits based on the flipped voltage follower: (1) a power-efficient class AB cascode FVF (denoted here as HP_CSCFVF) with high swing, very low output resistance, and essentially higher small signal and large signal figures of merit than previously reported AB FVF versions and (2) a low-voltage high-performance cascoded current mirror (denoted here as HP_CS_CM) with much lower input resistance and much higher output resistance than the conventional current mirror and highly linear gain. The proposed circuits are described in Section 2. Section 3 shows the post-layout simulation results that verify the high-performance characteristics of the proposed circuits, and Section 4 provides the conclusions. In this paper, the authors introduce two improved circuits based on the flipped voltage follower: (1) a power-efficient class AB cascode FVF (denoted here as HP_CSCFVF) with high swing, very low output resistance, and essentially higher small signal and large signal figures of merit than previously reported AB FVF versions and (2) a low-voltage high-performance cascoded current mirror (denoted here as HP_CS_CM) with much lower input resistance and much higher output resistance than the conventional current mirror and highly linear gain. The proposed circuits are described in Section 2. Section 3 shows the post-layout simulation results that verify the high-performance characteristics of the proposed circuits, and Section 4 provides the conclusions.  Figure 3 shows the scheme of the proposed class AB high-performance cascode FVF (HP_CSCFVF). It is a modification of the class A cascode FVF reported in [5] and is shown 4 of 17 in Figure 1c. It includes an additional branch with a PMOS transistor M source that provides efficient class AB operation. M source has a small quiescent current I Qsource , but it can inject positive output currents I out into the load C L , which are much larger than I Qsource . On the other hand, transistor M sink can sink very large negative load currents (also much larger than the quiescent current of M sink given by I Qsink = I Qsource + I bias ), as is discussed below. The biasing branch has two diode-connected PMOS transistors M b and M bC . Based on replica biasing, this branch sets the voltage V y to a value V y = V DD − V SGb and the gate voltage of M source to a value V g = V y + V bat , where V bat = I bat R bat. The values of I bat and R bat are selected so that V bat has an approximate value V bat = V SDsat = 0.1 V. In this case, the quiescent source-gate voltage of M source is given by V Q SGsource = V SGb − I bat R bat . This leads to a quiescent voltage V Q SGsource = V SGb − V SDsat ≈ V TH close to the threshold voltage of M source . This quiescent source-gate voltage sets a relatively small quiescent current I Qsource in M source , which is independent of the supply voltage. A capacitor C bat forms a high-pass filter with R bat and C bat . This is used to transfer fast transient variations from V x to the gate V g of M source. Figure 3 shows the scheme of the proposed class AB high-performance ca (HP_CSCFVF). It is a modification of the class A cascode FVF reported in [5] an in Figure 1c. It includes an additional branch with a PMOS transistor Msource tha efficient class AB operation. Msource has a small quiescent current IQsource, but it positive output currents Iout into the load CL, which are much larger than IQso other hand, transistor Msink can sink very large negative load currents (also m than the quiescent current of Msink given by IQsink = IQsource + Ibias), as is discussed biasing branch has two diode-connected PMOS transistors Mb and MbC. Based biasing, this branch sets the voltage Vy to a value Vy = VDD − VSGb and the gate Msource to a value Vg = Vy + Vbat, where Vbat = IbatRbat. The values of Ibat and Rbat are that Vbat has an approximate value Vbat = VSDsat = 0.1 V. In this case, the quiesce gate voltage of Msource is given by V Q SGsource = VSGb − IbatRbat. This leads to a quiesce V Q SGsource = VSGb − VSDsat ≈ VTH close to the threshold voltage of Msource. This quiesc gate voltage sets a relatively small quiescent current IQsource in Msource, which is in of the supply voltage. A capacitor Cbat forms a high-pass filter with Rbat and C used to transfer fast transient variations from Vx to the gate Vg of Msource.

Class AB Operation of Proposed Voltage Follower
For positive input voltage variations in Vin, the output voltage VoHPCSC incr the gate voltage Vx of Msink decreases. The current in Msink decreases (and event off) and the dynamic changes in Vx are transferred to Vg by Cbat to the gate of M decrease in Vg causes the current Isource of Msource to increase, providing a posit current Iout that can be significantly larger than the quiescent current IQsource o the design described in Section 3, IQsource has a value IQsource = 7 µA). For nega voltages, the output voltage decreases, and Vx increases. This increases the curr provides a large negative output current Iout that can be much larger than the current IQsink of Msink. The FVFs in Figures 1b,c and 3 use an RC compensatio formed by Cc and Rc for the local feedback loop. These elements provide a dom and a high-frequency zero at Vx that approximately match the output pole o loop gain ωpout = gmFVF/CL at the output node VoHPCSC. This allows FVF circuits cantly improve their bandwidth with respect to the conventional voltage follo ure 1a. This simple but effective FVF compensation and bandwidth extension was reported in [10].

Class AB Operation of Proposed Voltage Follower
For positive input voltage variations in V in , the output voltage V oHPCSC increases, and the gate voltage V x of M sink decreases. The current in M sink decreases (and eventually turns off) and the dynamic changes in V x are transferred to V g by C bat to the gate of M source . The decrease in V g causes the current I source of M source to increase, providing a positive output current I out that can be significantly larger than the quiescent current I Qsource of M source (in the design described in Section 3, I Qsource has a value I Qsource = 7 µA). For negative input voltages, the output voltage decreases, and V x increases. This increases the current I sink and provides a large negative output current I out that can be much larger than the quiescent current I Qsink of M sink . The FVFs in Figures 1b,c and 3 use an RC compensation network formed by C c and R c for the local feedback loop. These elements provide a dominant pole and a high-frequency zero at V x that approximately match the output pole of the open loop gain ω pout = g mFVF /C L at the output node V oHPCSC. This allows FVF circuits to significantly improve their bandwidth with respect to the conventional voltage follower of Figure 1a. This simple but effective FVF compensation and bandwidth extension technique was reported in [10].

High-Performance Low-Voltage Current Mirror (HP_CS_CM)
The scheme of the proposed low-voltage high-performance current mirror (HP_CS_CM) is shown in Figure 4a. It is a modified version of the FVF current mirror of Figure 2b that includes two auxiliary amplifiers A SEinvfcamp with gain A aux and a level shifter FVF levelshifter .
The transistor level implementation of the auxiliary amplifiers and the level shifter is shown in Figure 4b. Each of the amplifiers form local negative feedback loops with the cascode transistors M 1C and M 2C . They boost their effective gain by the gain A aux = (g m r o ) 2 = A 2 of the auxiliary amplifiers. They are implemented in Figure 4b using single-ended folded cascode inverting amplifiers formed by M FCA1 and M CA1 and by M FCA2 and M CA2 . A modified flipped voltage follower is used to generate a very-low-impedance node V G that operates as the signal ground (or reference node) for the input common source transistors M FCA1 and M FCA2 of the auxiliary amplifiers. Transistors M BAT , M FCA1 , and M FCA2 have the same W/L dimensions, the same quiescent current, and quiescent gate-source voltages. For this reason, the negative feedback loops of the auxiliary amplifiers shown in Figure 4a,b cause the gate voltages V refX , V X , and V XP to have the same value. This results in equal drain-source voltages of the input and output mirror transistors and leads to a highly linear and accurate current mirror gain. On the other hand, the large gain boosting of the cascode transistors M 1C and M 2C provided by the folded cascode auxiliary amplifiers leads to an extremely low input resistance R in = 1/(g m A 3 )/2, which is lower by a factor of A aux = A 2 /2 than the input resistance of the FVF mirror of Figure 2b and to an extremely high output resistance R out = r o A 3 that is higher by the same factor A aux than the output resistance of the mirrors of Figure 2. The value of V refX (selected by the designer) sets the input voltage requirement V in of the mirror. It must be higher than V DSsat in order to keep the input and output mirror transistors in saturation. In the proposed design, V refX was selected to have a value V refX = 0.15 V, but it can also have been lower since input and output transistors had a value V DSat = 0.06 V in the design discussed in Section 3. Remarks: (1) The FVF level shifter is a modified version of the basic FVF (or CONV_FVF). It has a resistor R in series with transistor M BFVF . This resistor R in Figure 4a is used to generate a voltage drop that pulls down the voltage at node V z and allows transistor M BAT to have enough drain-source (V DS > V DSSat ) voltage to operate in saturation. (2) The implementation of the auxiliary amplifiers using folded cascode amplifiers with a floating virtual ground node V G in which the nominal voltage is set by the designer has the purpose of reducing the supply requirements of the circuit. (3) A distinctive characteristic of the proposed mirror is that the modified FVF with resistor R allows the quiescent value of V G to be set to a value that is convenient to minimize the supply voltage and the input voltage requirements of the circuit. It also allows M BAT to be maintained in saturation. Previous implementations of mirrors with auxiliary amplifiers (i.e., the regulated cascode mirrors discussed in [1]) required the source of the auxiliary amplifier's input transistors to be connected to one of the supply rails and does not allow the supply requirements to be minimized or V in to be set. (4) If required, the gain A aux of the auxiliary amplifiers can be further boosted from a value A aux = A 2 /2 in the circuit of Figure 4b to a value A aux = A 3 /2 by utilizing double-cascoded auxiliary amplifiers. This would also boost the output impedance by an additional factor A/2 and decrease the input impedance of the mirror by the same factor. (5) The local negative feedback loops formed by the auxiliary amplifiers have only one high-impedance node at V Y and V YP . Compensation elements R c and C c are used to generate a dominant pole (and a zero) at these nodes. This is in order to compensate these loops and to prevent instability. (6) In order to reduce power dissipation, the auxiliary amplifiers and the FVF level shifters are biased with currents I bias /k, which is a factor k times smaller than the bias current I bias of the input and output mirror transistors M 1 and M 2 . In the proposed design, a value k = 10 was used. This lead to a total quiescent current and power dissipation of the proposed mirror that is only 25% higher than the power dissipation of the mirrors of Figure 2. (7) The proposed current mirror can be easily transformed into a class AB mirror using the techniques reported in [11].

Simulations of the High-Perfromance Class AB Follower HP_CSCFVF
The CONV_VF, CONV_FVF, CONV_CSCFVF, and proposed HP_CSCFVF circuits of

Simulations of the High-Perfromance Class AB Follower HP_CSCFVF
The CONV_VF, CONV_FVF, CONV_CSCFVF, and proposed HP_CSCFVF circuits of selected to provide a dominant pole ω pdom = 1/R x C c at node V X : and a high-frequency zero ω z = 1/R c C c at V x that approximately matches at the output pole ω pout = g mFVF /C L at the output node V oHPCSC of the FVF, as suggested by the design guidelines in [10]. Transistors M source and M sink were scaled up by factors 10 and 3, respectively. This was performed in order to equalize their dynamic output currents and to achieve symmetrical slew rates (SR+ and SR−). The total quiescent current and power dissipation of the proposed circuit were I TotQ = 21 µA and P dissQ = 31.5 µW, respectively. The small signal transconductance g m and output conductance g ds of the NMOS and PMOS unit transistors had the following values: g mN = 148 µA/V, g dsN = 2.94 µA/V, g mP = 160 µA/V, and g dsP = 2.2 µA/V. Figure 5 shows the frequency responses of the CONV_VF, CONV_FVF, CONV_CSCFVF, and proposed HP_CSCFVF. The bandwidth of the HP_CSCFVF is 14.6 MHz, that of the CONV_CSCFVF is 3.47 MHz, that of the CONV_FVF is 2.5 MHz, and that of the CONV_VF is 0.347 MHz. Notice that the bandwidth of the proposed circuit is a factor almost 42 times larger than the bandwidth of the CONV_VF and 4.2 times larger than the CONV_CSCFVF. Figure 6a shows the pulse response of the proposed HP_CSCFVF and of the CONV_CSCFVF to a 1 MHz 0.9 V pp pulse input. Figure 6b shows the corresponding load capacitor currents. It can be seen that the proposed circuit has close to symmetrical positive and negative peak output currents (and consequently slew rate) with the values I outpk + = 2.6 mA and I outpk − = 2.47 mA, respectively. Notice that the proposed circuit has peak output currents, which are a factor 118 times larger than the total quiescent current of the circuit. This corresponds to a very large current efficiency factor CE = I outpk /I TotQ = 118. The peak currents (and slew rates) of the conventional circuits is much lower due to their class A operation.
The positive and negative slew rates of the proposed circuit are SR+ = 34.47 V/µs and SR− = 34.03 V/µs (for C L = 100 pF). Figure 7 shows the pulse response for various C L values of 10 pF, 32 pF, 55 pF, 80 pF, and 100 pF. It can be seen that, in all cases, the pulse response has a only a small overshoot. Figure 8 shows the AC response of the output resistance of the proposed circuit. It has a very low value R out = 2.11 Ω at low frequencies.
The layout of the proposed design is shown in Figure 9. It occupies a 114 µm × 47 µm Si area.  Figure 5 shows the frequency responses of the CONV_VF, CONV_FVF, CONV_CSCFVF, and proposed HP_CSCFVF. The bandwidth of the HP_CSCFVF is 14.6 MHz, that of the CONV_CSCFVF is 3.47 MHz, that of the CONV_FVF is 2.5 MHz, and that of the CONV_VF is 0.347 MHz. Notice that the bandwidth of the proposed circuit is a factor almost 42 times larger than the bandwidth of the CONV_VF and 4.2 times larger than the CONV_CSCFVF. Figure 6a shows the pulse response of the proposed HP_CSCFVF and of the CONV_CSCFVF to a 1 MHz 0.9 Vpp pulse input. Figure 6b shows the corresponding load capacitor currents. It can be seen that the proposed circuit has close to symmetrical positive and negative peak output currents (and consequently slew rate) with the values Ioutpk + = 2.6 mA and Ioutpk -= 2.47 mA, respectively. Notice that the proposed circuit has peak output currents, which are a factor 118 times larger than the total quiescent current of the circuit. This corresponds to a very large current efficiency factor CE = Ioutpk/ITotQ = 118. The peak currents (and slew rates) of the conventional circuits is much lower due to their class A operation.    Figure 7 shows the pulse response for various CL values of 10 pF, 32 pF, 55 pF, 80 pF, and 100 pF. It can be seen that, in all cases, the pulse response has a only a small overshoot. Figure 8 shows the AC response of the output resistance of the proposed circuit. It has a very low value Rout = 2.11 Ω at low frequencies. The layout of the proposed design is shown in Figure 9. It occupies a 114 µm × 47 µm Si area.      Table 1A-C show corner analysis of the proposed HP_CSCFVF at three different temperatures (27 °C, 120 °C, and −20 °C). It can be said that the proposed VF's characteristic is very stable against process and temperature variations. The standard deviation (SD) of each parameter for variation in the process has been given in Table 1 for the considered temperatures (27 °C, 120 °C, and −20 °C).    Table 1A-C show corner analysis of the proposed HP_CSCFVF at three different temperatures (27 °C, 120 °C, and −20 °C). It can be said that the proposed VF's characteristic is very stable against process and temperature variations. The standard deviation (SD) of each parameter for variation in the process has been given in Table 1 for the considered temperatures (27 °C, 120 °C, and −20 °C). Table 1A-C show corner analysis of the proposed HP_CSCFVF at three different temperatures (27 • C, 120 • C, and −20 • C). It can be said that the proposed VF's characteristic is very stable against process and temperature variations. The standard deviation (SD) of each parameter for variation in the process has been given in Table 1 for the considered temperatures (27 • C, 120 • C, and −20 • C). The THD of the proposed circuit is 0.2% for a 0.5 V pp 100 kHz input signal and 1% for a 0.5 V pp 1 MHz sinusoidal input signal. The equivalent input noise power spectral density and RMS noise are 29 nV/ √ Hz and 130 µV RMS . The small signal figure of merit is FOM SS = 46 MHz·pF/µW, and the large signal current efficiency figure of merit is FOM CE = I outpk /I TotQ = MIN{I outpk +, I outpk −}/I TotQ = 118. The global figure of merit is FOM Global = √ FOM SS FOM CE = 73. Table 2 shows a comparison of the performance characteristics of the proposed HP_CSCFVF with other voltage followers reported recently in the literature. It can be seen that the proposed HP_CSCFVF has the lowest output impedance, the highest small signal (FOM SS ), a large signal and current efficiency (FOM CE ), and global (FOM Global ) figures of merit in the table.  Figure 10 shows the Monte Carlo (MC) analysis of the proposed HP_CSCFVF power dissipation over 200 sample Monte Carlo simulation for process variation and mismatch. The mean quiescent power is 35.38 µW, and the standard deviation is 0.605 µW. From the corner analysis and Monte Carlo analysis, it can be ascertained that the proposed VF is robust against process variation, temperature, and mismatch effect.

Simulation Results for Low-Voltage High-Performance Current Mirror HP_CS_CM
The CN_CS_CM and proposed HP_CS_CM current-mirror circuits of Figures 2a and 4 were simulated in a commercial 180 nm CMOS technology with a supply voltage of 1V and I bias = 2 µA. The resistor used to implement R bat in the FVF level shifter has a value 75 kΩ. It is implemented using a PMOS transistor. The W/L ratio of the PMOS and NMOS transistors used in the input and output stages of both current mirrors are W/L = 5 µm/0.4 µm. Transistors used in the auxiliary amplifiers and the FVF level shifter of the proposed current mirror are scaled down by factor k = 10. This was performed in order to reduce the quiescent power dissipation. The compensation elements had values C c = 1.5 pF and R c = 4 kΩ.

FOMGlobal
3.06 2.24 30 9.7 13 15 12.7 3.04 73 Figure 10 shows the Monte Carlo (MC) analysis of the proposed HP_CSCFVF power dissipation over 200 sample Monte Carlo simulation for process variation and mismatch. The mean quiescent power is 35.38 µW, and the standard deviation is 0.605 µW. From the corner analysis and Monte Carlo analysis, it can be ascertained that the proposed VF is robust against process variation, temperature, and mismatch effect.   Figure 11 shows the frequency response of the proposed high-performance cascoded current mirror (HP_CS_CM). It has a 144 MHz bandwidth. Figure 12 shows the frequency response of the input impedance of the conventional cascode mirror CN_CS_CM and of the proposed HP_CS_CM. The CN_CS_CM has constant input impedance of 22 kΩ, whereas the input impedance of the proposed current mirror is 0.212 Ω up to 800 Hz and 8.9 kΩ at 118 MHz. The HP_CS_CM has an input impedance, at low frequencies, that is close to 10 5 times lower than the CN_CS_CM.  Figure 11 shows the frequency response of the proposed high-performance cascoded current mirror (HP_CS_CM). It has a 144 MHz bandwidth. Figure 12 shows the frequency response of the input impedance of the conventional cascode mirror CN_CS_CM and o the proposed HP_CS_CM. The CN_CS_CM has constant input impedance of 22 kΩ whereas the input impedance of the proposed current mirror is 0.212 Ω up to 800 Hz and 8.9 kΩ at 118 MHz. The HP_CS_CM has an input impedance, at low frequencies, that i close to 10 5 times lower than the CN_CS_CM.     Figure 13 shows the frequency response of the output impedance of the CN_CS_CM and of the HP_CS_CM. The proposed HP_CS_CM has an output impedance of 112 GΩ until 100 Hz, and the lowest output impedance is 18 MΩ through its bandwidth. On the contrary, the output impedance for the CN_CS_CM is 355 MΩ. Thus, the proposed high-  Figure 13 shows the frequency response of the output impedance of the CN_CS_CM and of the HP_CS_CM. The proposed HP_CS_CM has an output impedance of 112 GΩ until 100 Hz, and the lowest output impedance is 18 MΩ through its bandwidth. On the contrary, the output impedance for the CN_CS_CM is 355 MΩ. Thus, the proposed high-performance current mirror has an output impedance that is 315 times higher than the CN_CS_CM at low frequencies. performance current mirror has an output impedance that is 315 times higher than the CN_CS_CM at low frequencies. Figure 14 shows the transient response to a triangular input current waveform. It can be seen that the proposed HP_CS_CM closely follows the linear input triangular current waveform. Figure 15 shows the transient pulse response of the proposed HP_CS_CM to a 10 MHz, 10 µA input pulse. It can be seen that the proposed HP_CS_CM has no peaking in the output pulse response.  Figure 14 shows the transient response to a triangular input current waveform. It can be seen that the proposed HP_CS_CM closely follows the linear input triangular current waveform. Figure 15 shows the transient pulse response of the proposed HP_CS_CM to a 10 MHz, 10 µA input pulse. It can be seen that the proposed HP_CS_CM has no peaking in the output pulse response.  An ideal current source is a circuit element that maintains a constant current flow independent of the voltage developed across its terminals as this voltage is determined by other circuit elements. To verify this property, Figure 16 shows the DC output transfer characteristics for dc voltage variation of 0 to 1 V by stepping the input current up from 0 Frequency(Hz)   An ideal current source is a circuit element that maintains a constant current flow independent of the voltage developed across its terminals as this voltage is determined by other circuit elements. To verify this property, Figure 16 shows the DC output transfer characteristics for dc voltage variation of 0 to 1 V by stepping the input current up from 0 to 10 µA in steps of 2.5 µA. It can be seen that the mirror compliance (minimum output) voltage for performance as a current source is approximately 0.2 V. Figure 17 shows the input voltage of the CN_CS_CM and of the proposed HP_CS_CM by sweeping the input current I in from o to 10 µA. It can be seen that the proposed HP_CS_CM has a constant 0.15 V input voltage, while the input voltage of the conventional mirror CN_CS_CM varies from 450 mV to 550 mV.   Figure 17 shows the input voltage of the CN_CS_CM and of the proposed HP_CS_CM by sweeping the input current Iin from o to 10 µA. It can be seen that the proposed HP_CS_CM has a constant 0.15 V input voltage, while the input voltage of the conventional mirror CN_CS_CM varies from 450 mV to 550 mV. Figure 18 shows the gain error (in percent) e = 100[(Iout − Iin)/Iin] in the current transfer characteristic of the CN_CS_CM and the proposed HP_CS_CM as a function of the input current. It can be seen that, as expected, errors are similar since, in both mirrors, the drainsource voltages of input and output transistors are very similar. The total harmonic distortion of the proposed HP_CS_CM is given in Table 3 for a 200 µA amplitude sine wave at frequencies 500 Hz, 10 KHz, 1 MHz, and 100 MHz.     Figure 18 shows the gain error (in percent) e = 100[(I out − I in )/I in ] in the current transfer characteristic of the CN_CS_CM and the proposed HP_CS_CM as a function of the input current. It can be seen that, as expected, errors are similar since, in both mirrors, the drain-source voltages of input and output transistors are very similar. The total harmonic distortion of the proposed HP_CS_CM is given in Table 3 for a 200 µA amplitude sine wave at frequencies 500 Hz, 10 KHz, 1 MHz, and 100 MHz. A Monte Carlo analysis with 200 samples was executed for some important parameters of the proposed HP_CS_CM for a 2 µA bias current. Table 4 gives the mean value and standard deviation of the bandwidth, input, output resistance, quiescent power, and gain for 200 runs. It can be see that the proposed current mirror is robust against process variation and mismatch effects. A noise analysis was also performed for the HP_CS_CM. The input referred noise was 14.5 pA/ √ Hz.   A Monte Carlo analysis with 200 samples was executed for some important parameters of the proposed HP_CS_CM for a 2 µA bias current. Table 4 gives the mean value and standard deviation of the bandwidth, input, output resistance, quiescent power, and gain for 200 runs. It can be see that the proposed current mirror is robust against process variation and mismatch effects. A noise analysis was also performed for the HP_CS_CM. The input referred noise was 14.5 pA/√Hz.   Table 5 compares the performance characteristics of the proposed HP_CS_CM to other low-voltage mirrors in the literature [17][18][19][20]. The proposed mirror has the highest output resistance and the lowest input resistance of all mirrors. Bandwidth is dependent on power dissipation. A mirror figure of merit FOM CM = BW/P diss is used to compare the circuits. Notice that the proposed mirror has the highest FOM CM in the table (the input compliance voltage of the resistance based mirror in [18] is lower but it has the serious shortcoming that, with the reported 39.6 mV input voltage, it is subject in practice to very large random gain/linearity errors caused by mismatch in V DS due to random offset of input and output transistors in the control circuit).

Conclusions
Two high-performance circuits based on the flipped voltage follower were introduced: (1) One was a class AB high-performance cascode flipped voltage follower that uses an additional output branch with a PMOS current-sourcing transistor. Replica biasing techniques are used to bias the sourcing transistor with a small quiescent current independent of the supply voltage. Under dynamic conditions, the sourcing transistor can provide very large positive output currents, which are over a factor 100 larger than the total quiescent current of the proposed circuit. Simulations in a commercial 0.18 µm CMOS technology have shown that it has low supply voltage requirements, greatly enhanced bandwidth, approximately symmetrical and large slew rates, and the largest small signal and large signal figures of merit of all class AB voltage followers. (2) The other was a low-voltage high-performance current mirror with 0.15 V input and 0.2 V output compliance voltages, 1 V supply voltage, extremely high output resistance (112 GΩ), extremely low input resistance (0.212 Ω), and the highest figure of merit.
This high-performance current mirror is implemented by utilizing two auxiliary amplifiers and a level shifter that boost the gain of the mirror cascode transistors and that equalize the drain source voltages of input and output mirror transistors. The auxiliary circuit increases the power dissipation of the mirror by only 25%. These characteristics were also verified with simulations in a commercial 0.18 µm CMOS technology.