A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair

: This work presents a two-stage operational transconductance ampliﬁer suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the ﬁrst stage and the quasi-ﬂoating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the ampliﬁer exhibits a 350 kHz gain bandwidth product and a phase margin of 69 ◦ while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.


Introduction
In applications that require low power consumption, such as implantable biomedical devices, sensor nodes for the Internet of Things, and energy-harvesting battery-less devices, the design of analog circuits has become a challenging task. Indeed, while in these applications the digital part benefits from the technological scaling in terms of energy consumption reduction and performance enhancement, the performance of analog circuits decreases when technology is scaled down due to the reduced intrinsic gains of transistors and of the signal-to-noise ratios [1,2]. These disadvantages are exacerbated when the supply voltage is reduced below 1V, in which the design of the operational transconductance amplifier (OTA), representing the universal and fundamental building block of any analog front-end, is particularly difficult.
Below the 1V supply, the most widely used design approach is the sub-threshold bias (also known as the weak reverse bias) [3][4][5][6][7][8][9][10]. Inverter-based OTAs represent another viable alternative [11][12][13]. However, the main disadvantage of operating the digital inverter as an amplifier is the high variation of the dc gain and gain bandwidth (GBW), with temperature and process corners. Moreover, only pseudo-differential operation is achievable.
When input rail-to-rail capability is required, the bulk driving (body driving) technique is an effective solution, even in combination with sub-threshold operation [14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. However, when compared to conventional gate-driven circuits, body-driven counterparts exhibit a lower voltage gain due to the reduced value of the bulk transconductance, which accounts for only 10-20% of the gate transconductance [1]. Moreover, if the bulk of NMOS transistors must also be driven, the body-driven approach mandates for a triple-well process. However, since most of the modern CMOS technologies provide such feature, this point is not a real limitation.
To overcome the low gain of bulk-driven OTAs, we exploit in this work local positive feedback to improve first-stage transconductance [26,[29][30][31]. The class AB operation of the second stage is enabled by exploiting the quasi-floating gate approach [32]. Moreover, the tail bias current of the input gain stage is avoided while maintaining differential operation. This paper is structured as follows.Section 2 discusses the circuit operation principle and analytical design equations are carried out. Section 3 describes the design and simulation of the OTA, while in Section 4 the experimental measurements and a comparison with other amplifiers in the literature are reported. Finally, concluding remarks are drawn in Section 5. Figure 1 shows the schematic diagram of the designed amplifier. Where not represented, the transistor bulk terminal is considered to be connected to the corresponding source. The first OTA stage is a bulk-driven non-tailed differential pair M 1 -M 2 loaded by the current mirror M 3 -M 4 and M 5 -M 6 . Differential to single-ended conversion is implemented by the additional current mirror M 9 -M 10 . The diode-connected transistor M B1 generates the voltage V B1 to be applied to the gates of M 1 -M 2 , thus setting their bias current. It is worth noting that the bulk terminal of M B1 is biased through the voltage divider R 1 -R 2 , which sets the analog ground [26]. Due to the lack of the tail current generator, the couple M 1 -M 2 works as a pseudodifferential pair; however, as detailed in [26], the overall OTA input stage exhibits a quasi-differential behavior due to the action of M 7 and M 8 that make voltages at node 1 and 2, as seen in in Figure 1, dependent on the difference of the inverting and noninverting input voltages.

The Proposed Circuit
Thanks to the action of the local positive feedback implemented by transistors M 7 and M 8 , the equivalent differential transconductance of the first stage is expressed by [26]: where and g mb1,2 is the bulk transconductance of M 1 and M 2 and it is assumed that (W/L) 9 = (W/L) 10 .
From (1), it is apparent that the first-stage transconductance can be boosted by appropriately choosing the aspect ratios α and β from (2) and (3), respectively. In particular, to avoid the magnitude of the positive feedback being higher than one (and, consequently, the amplifier becoming a latch), parameter α must be lower than 1. As a general rule of thumb, it is desirable to set α less than 0.9 to guarantee an adequate margin against process mismatches [31].
The second stage is made up of the common source stage M 11 and M 12 . Class AB operation is enabled by adding resistor R BATT , connected between the gate of the load transistor M 12 and the diode-connected transistor M B3 , and capacitor C BATT which adds a path for the signal during dynamic operation [32]. Under quiescent conditions and considering that no DC current flows through R BATT , the voltage at the gate of M 12 is the same as at the gate of M B3 . Consequently, the quiescent current in M 12 can be precisely set like in a conventional current mirror. During dynamic operation, the voltage at the output of the first stage is subject to a large variation. Capacitor C BATT , which cannot discharge/charge rapidly through R BATT , acts as a floating battery and transfers the voltage changes to the gate of M 12 , thus providing class AB operation to the second stage.
The frequency compensation branch is implemented by the conventional Miller capacitor C C in series with the resistor R C connected across node 1 and the output node.
Neglecting the parasitic capacitance contribution at nodes 1, 2, and 3 in Figure 1, the open-loop transfer function of the OTA can be approximated as being A 0 = G mb (g m11 + g m12 )r o1 r o2 the DC gain, with r o1 = r d10 //r d6 and r o2 = r d11 //r d12 , and the zero and poles expressed by where the rightmost approximation in (6) and (7) holds if the following relation is satisfied: It is worth noting that, thanks to the adopted compensation strategy which exploits the embedded current buffer M 3 -M 4 -M 9 -M 10 , the non-dominant pole p 2 is moved at high frequency by a factor equal to (1 + α)β as compared to a conventional two-stage Miller OTA.
The evaluation of the phase margin (PM) yields where GBW is the gain bandwidth product equal to g mb1,2 /C C . The slew rate (SR) of an amplifier is determined by the maximum available charging/discharging currents of capacitors in the circuit. By inspection of Figure 1 and neglecting the effect of parasitic capacitors, the overall SR can be expressed as where I 1 is the maximum current provided by M 1 and I out is the charging/discharging current of the class AB output stage. Being C C << C L , the rightmost approximation in (10) holds.

Design and Simulation Results
Using a standard 180 nm CMOS process supplied by STMicroelectronics, the amplifier shown in Figure 1 was designed using the transistor dimensions, bias conditions, passive components values, and small-signal parameters reported in Tables 1-3 and assuming a nominal supply voltage equal to 0.6 V. The resistors were implemented using highresistance polysilicon resistors with a square resistance of 3 kΩ.   3.98 µA/V g m9, 10 31.38 µA/V g mb1, 2 1.197 µA/V g m11 55.97 µA/V g m3, 5 2.71 µA/V g m12 62.89 µA/V g m4, 6 36.04 µA/V r o1 1.03 MΩ g m7, 8 1.848 µA/V r o2 764 kΩ Considering the transistor dimensions reported in Table 1, parameters α and β are equal to 0.83 and 15, respectively. Therefore, the bulk transconductance of M 1 and M 2 , equal to 3.98 µA/V, is boosted by about 88 times.
Corner simulations and Monte Carlo analysis are executed to assess the robustness of the amplifier over process, temperature, and mismatch variations. The results are reported in Tables 4-6 for three different temperatures (i.e., −10 • C, 27 • C, and 85 • C) for all transistor corners. The results show that the amplifier is stable in all conditions. Furthermore, Monte Carlo simulation results over 1000 runs show a relative standard deviation lower than 25% for all parameters. Figure 2 shows the simulated input referred noise versus frequency. The white noise level is equal to 1.3 µV/ √ Hz. Figure 3 shows the magnitude of the power supply rejection ratio (PSRR) and the common mode rejection ratio (CMRR) versus frequency. Figure 4 depicts the DC transfer characteristic of the amplifier in unity-gain configuration, showing a rail-to-rail input common mode range (ICMR). In the same figure, it can be also noted that the input current is lower than 13 nA.

Measurement Results and Comparison
The OTA in Figure 1 has been fabricated and experimentally tested. The layout and the chip microphotograph of the circuit are shown in Figure 5. The occupied area is 1329 µm 2 . The circuit has been characterized at a 0.6 V supply and a 150 pF capacitive load. Figure 6 reports the measured Bode plot in open-loop configuration, showing a GBW equal to 350 kHz and a PM equal to 69 • . The transient response to a 100 mV pp input step, with the OTA in unity gain, is shown in Figure 7.   Table 6 summarizes the OTA main performance parameters and a comparison with other sub-1 V amplifiers taken form the literature. To evaluate the performance trade-off between bandwidth, load capacitance, slew rate (SR), and total bias quiescent, I T , we use in Table 6, the following conventional figures of merit: Among the considered solutions, only the single-stage in [26] exhibits a higher value of IFOM S but with a DC gain equal to 38 dB only. As compared to the remaining solutions, the increase in (11a) is equal to about 3.45. The proposed topology shows an increase in IFOM L equal to 4.36× against all the other solutions.
Two other traditional figures of merit, which take into account the silicon area, are included in Table 7: Additionally, in this case the proposed solution outperforms the other amplifiers, except for the IFOM AS of [26]. It is worth noting, however, that the tail-less structure does not offer a CMRR and PSRR as high as tailed ones, but the values are still acceptable and comparable with other solutions.  GD  BD  BD  GD  BD  GD  BD  GD  BD  BD  BD  BD  BD  BD  BD  BD  BD  Stage #  2  2  1  1  2  2  3  2  3  2  2  3  3  1  2  3

Conclusions
In this paper, a two-stage OTA exploiting local positive feedback, a non-tailed differential pair, and a class AB second stage are discussed, analyzed, and experimentally tested. A comparison with the state-of-the-art reveals that the proposed solution is suitable for area-constrained low-voltage low-power applications such as battery-less IoT nodes.

Data Availability Statement:
No new data were created or analyzed in this study. Data sharing is not applicable to this article.

Conflicts of Interest:
The authors declare no conflict of interest.