Implementation of Power-Efﬁcient Class AB Miller Ampliﬁers Using Resistive Local Common-Mode Feedback

: An approach to implement single-ended power-efﬁcient static class-AB Miller op-amps with symmetrical and signiﬁcantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary ampliﬁer with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by signiﬁcantly enhanced large-signal dynamic, static current efﬁciency, and small-signal ﬁgures of merits. The dynamic current efﬁciency is 15.6 higher, the static current efﬁciency is 10.6 times higher, and the small-signal ﬁgure of merit is 2.3 times higher than the conventional class-A op-amp. A global ﬁgure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp. the quiescent output current has a nominal well-deﬁned value independent of VDD, technology parameters, and temperature.


Introduction
The Miller op-amp is the essential building block of analog integrated circuits [1,2]. In the conventional class-A Miller op-amp with an NMOS input stage [2,3] shown in Figure 1a, the NMOS output transistor limits the peak negative output current to a value I outQ corresponding to the output branch's quiescent current. This imposes a severe limitation in the op-amp's negative slew rate (SR − ). This can be expressed as SR − = (I outQ − I RL )/ (C C + C L ), where C C and C L are compensation and load capacitors and I RL is the current of the resistive load. Many approaches have been proposed to implement Miller op-amps with static class-AB [4,5] output stages. This type of amplifier can drive a wide range of capacitive and resistive loads down to very low frequencies or DC. They are required to have approximately symmetrical slew rates and to be able to generate symmetrical peak load positive and negative output currents I Outpk + and I Outpk − much larger than the total op-amp quiescent current I totQ . A common figure of merit to characterize the op-amp current efficiency CE = I Outpk /I totQ is defined as the ratio of the minimum of the positive and negative peak output currents I Outpk = MIN{I Outpk + , I Outpk − } to I totQ .

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The conventional class-A op-amp (Conv-A) is characterized typically by CE < 0.5. Many approaches to implementing class-AB op-amps are based on the floating battery [6] scheme shown in Figure 1b. The floating battery that exists between the gates of the PMOS and NMOS output transistors causes the voltage V Y at the gate of the output NMOS transistor to follow the variations at node V X , which is the high impedance output node of the differential input stage. The voltage V X drives the output PMOS transistor M OP . The small signal model of the class-AB op-amps based on the floating battery [6] scheme is shown in Figure 1c. In this, the ideal floating battery has been replaced by an AC short circuit. The output resistance R Out is given by R Out = R oOP ||r oON ||R L . As the conventional Miller compensation is used in the op-amp, the transfer function of the circuit of Figure 1c can be written as Equation (1).
J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 2 of 14 peak output currents IOutpk = MIN{IOutpk + , IOutpk − } to ItotQ. The conventional class-A op-amp (Conv-A) is characterized typically by CE <0.5. Many approaches to implementing class-AB op-amps are based on the floating battery [6] scheme shown in Figure 1b. The floating battery that exists between the gates of the PMOS and NMOS output transistors causes the voltage VY at the gate of the output NMOS transistor to follow the variations at node VX, which is the high impedance output node of the differential input stage. The voltage VX drives the output PMOS transistor MOP. The small signal model of the class-AB opamps based on the floating battery [6] scheme is shown in Figure 1c. In this, the ideal floating battery has been replaced by an AC short circuit. The output resistance ROut is given by ROut = RoOP||roON||RL. As the conventional Miller compensation is used in the opamp, the transfer function of the circuit of Figure 1c can be written as Equation (1).
where C X is given by C X = (1 + |A Out |) C C , R X = g m r o 2 /2, and |A Out | is the gain of the output stage.
The operation of Class-AB op-amps based on the floating battery principle is discussed below: (a) Upon application of a positive step at V in , the output of the op-amp provides a positive output current to the load. When the output slews in the positive direction, the voltage at node Vx is subject to a large negative variation, which is followed by the voltage at node V Y until it reaches the bottom rail. This increases the current in M OP and decreases the current in M ON , bringing it to zero for large negative variations in V Y that lead to V GSON < V TN , where V TN is the threshold voltage of M ON . Since V X can have large negative variations, the peak positive output current I Outpk + provided by M OP can be much larger than its quiescent current I OutQ, and a large positive slew rate can be achieved. The situation is quite different for negative steps in V in . In this case, V X has a relatively limited excursion in the positive direction, which is transferred (in practice with some attenuation) to V Y . This causes the current in M OP to decrease (and eventually go to zero) and M ON to increase. However, given that the variation in the positive direction of Vx and V Y is much smaller than the variation in the negative direction, the op-amp's peak negative output current I Outpk − generated by M ON is in general much smaller than I Outpk + . This leads to a negative slew rate, which can be much smaller than the positive slew rate. In practice, the smaller of the two slew rates determines the nominal op-amp's slew rate SR ≡ MIN{SR + , SR − }. (b) The practical implementation of the floating battery scheme requires a control circuit to achieve the desired nominal output quiescent current I OutQ , which adjusts the value of the floating battery V BAT so that its value is well defined and remains constant, independent of temperature, process parameters, and supply voltage variations. It can be shown that, in saturation, I OutQ is approximately given by, where β N , β P , V TN , and V TP are the NMOS and PMOS output transistors' gain factors and threshold voltages, respectively. A control circuit to adjust the value of V BAT is required since a fixed V BAT value would lead to large variations in I OutQ with changes in V supply , V TN , V TP , β N , or β P . An example of the class-AB output stage using a foating battery and a control circuit is shown in Figure 2. In this example, the floating battery is implemented using a voltage follower. The circuit implementation of both V BAT and the control circuit [7,8] can be relatively complex (as shown in Figure 2b and in the circuit of [8]) and increases the total op-amp's quiescent current. This can significantly lower the current efficiency of the class-AB op-amp. In some cases, it can also increase the supply requirements beyond the nominal supply voltage of the implementation technology, which has been reduced to sub-volt values (V supply < 1 V) in modern CMOS technologies.
technology, which has been reduced to sub-volt values (Vsupply < 1 V) in modern CMOS technologies.  This paper introduces a simple scheme that overcomes the shortcomings discussed above, requiring minimal additional power dissipation and not increasing the supply requirements. This scheme is discussed in the next section. Traditionally, the performance of op-amps is compared using three well-known figures of merit: This paper introduces a simple scheme that overcomes the shortcomings discussed above, requiring minimal additional power dissipation and not increasing the supply requirements. This scheme is discussed in the next section. Traditionally, the performance of op-amps is compared using three well-known figures of merit: (a) the small-signal figure of merit FOM SS = f u ·C L /P Q , where f u is the unity-gain frequency and P Q is the quiescent power of the op-amp; (b) the large-signal static current efficiency figure of merit FOM CEStat = I outpkRL /P Q ; and (c) the large-signal dynamic current efficiency figure of merit FOM CEDyn = SR·C L /P Q , which is related to the maximum dynamic output current in load capacitance C L . FOM CEStat is determined by the maximum DC output current in the load resistor R L (denoted I outpkRL ) relative to the total quiescent power P Q of the op-amp. In addition, as both FOM SS and FOM CEDyn determine the ultimate speed of an op-amp, a new global figure of merit FOM Global given by FOM Global = FOM SS FOM CEDyn is also used here.

Circuit Description
The scheme of the proposed op-amp is shown in Figure 3a. A telescopic input stage is used in the first stage to achieve high gain even in the presence of a low-valued load resistor R L (high loading conditions) that can degrade the second stage gain significantly. The proposed op-amp uses an auxiliary non-inverting amplifier with gain A aux to generate a voltage variation V Y , which is an amplified version of the variations in V X, that is, V Y = A aux V X . This auxiliary amplifier consumes less than 10% of the op-amp's total bias current and does not increase supply requirements. The transistor-level implementation of the auxiliary amplifier is shown in Figure 3b. It uses a differential stage with resistive common-mode feedback (RCMFB) that has approximately a gain A aux = (g m4 R CMF )/2, as shown in the analysis below. The auxiliary amplifier increases the op-amp's output negative current; the open-loop DC gain shifts the output poles to the higher frequency, allowing for a higher unity gain frequency. The quiescent voltage of V Y has a value V YQ = V GSQM5P independent of R CMF (and of A Aux ). This allows to accurately control the quiescent current I OutQ in the op-amp's output branch independent of the gain A aux , supply voltage, technology parameters variations, and temperature changes. Given that the variations generated at V Y are amplified with respect to those at Vx, M ON can provide large negative output currents even though the amplitude of positive variations in V X is smaller than that for negative variations. This overcomes one of the limitations of the conventional battery approach shown in Figure 1b.

Circuit Description
The scheme of the proposed op-amp is shown in Figure 3a. A telescopic input stage is used in the first stage to achieve high gain even in the presence of a low-valued load resistor RL (high loading conditions) that can degrade the second stage gain significantly. The proposed op-amp uses an auxiliary non-inverting amplifier with gain Aaux to generate a voltage variation VY, which is an amplified version of the variations in VX, that is, VY = AauxVX. This auxiliary amplifier consumes less than 10% of the op-amp's total bias current and does not increase supply requirements. The transistor-level implementation of the auxiliary amplifier is shown in Figure 3b. It uses a differential stage with resistive common-mode feedback (RCMFB) that has approximately a gain Aaux = (gm4RCMF)/2, as shown in the analysis below. The auxiliary amplifier increases the op-amp's output negative current; the open-loop DC gain shifts the output poles to the higher frequency, allowing for a higher unity gain frequency. The quiescent voltage of VY has a value VYQ = VGSQM5P independent of RCMF (and of AAux). This allows to accurately control the quiescent current IOutQ in the op-amp's output branch independent of the gain Aaux, supply voltage, technology parameters variations, and temperature changes. Given that the variations generated at VY are amplified with respect to those at Vx, MON can provide large negative output currents even though the amplitude of positive variations in VX is smaller than that for negative variations. This overcomes one of the limitations of the conventional battery approach shown in Figure 1b. In order to prevent degradation of the phase margin of the op-amp, the value of RCMF (and Aaux) is chosen in such a way that the pole at node Y is higher than the unity gain frequency fu of the op-amp by at least a factor of 3. Thus, the selection of the optimal value of RCMF is the crucial factor for the design of the proposed auxiliary amplifier. Larger values of RCMF lead to enhanced negative output currents and gains, resulting in lower values for the pole at node Y and lower phase margin.
In the presence of positive signals in VX larger than VSDsat4, all of the tail current of MTAILAUX flows through M4P and RCMF. This causes a large positive voltage change at node VY that generates large negative op-amp output currents. In order to achieve similar peak positive and negative output currents with the selected value of RCMF, the output transistors MON and MOP are scaled by factor 5/1 and factor 8/0.7 with respect to the unit PMOS and NMOS transistors of size 10/0.27 used in the input stage. In addition, conventional Miller compensation is used to achieve stability. In order to prevent degradation of the phase margin of the op-amp, the value of R CMF (and A aux ) is chosen in such a way that the pole at node Y is higher than the unity gain frequency f u of the op-amp by at least a factor of 3. Thus, the selection of the optimal value of R CMF is the crucial factor for the design of the proposed auxiliary amplifier. Larger values of R CMF lead to enhanced negative output currents and gains, resulting in lower values for the pole at node Y and lower phase margin.

Operation
In the presence of positive signals in V X larger than V SDsat4 , all of the tail current of M TAILAUX flows through M 4P and R CMF . This causes a large positive voltage change at node V Y that generates large negative op-amp output currents. In order to achieve similar peak positive and negative output currents with the selected value of R CMF, the output transistors M ON and M OP are scaled by factor 5/1 and factor 8/0.7 with respect to the unit PMOS and NMOS transistors of size 10/0.27 used in the input stage. In addition, conventional Miller compensation is used to achieve stability.

Operation
The working principle of the proposed op-amp can be explained by considering its voltage follower operation. In the presence of the positive input signal V in , the voltage at node V X decreases and the voltage at node V Y also decreases by a factor A aux . As a result, M OP provides a large positive current, and the drain current of M ON decreases and eventually reaches zero. On the other hand, for negative input signals, the voltage at node V Y corresponds to the amplified version of the positive signals of node V X, which is V Y = A aux V X . As a result, M ON can also provide large negative output currents.

Frequency Response
Conventional Miller compensation is used in the proposed op-amp. The proposed op-amp has one dominant pole ω pDOMX at node V X and two high-frequency poles ω pY and ω pOut . The zero ω z approximately nullifies the effect of ω pOut.
Thus, the transfer function of the proposed op-amp is given by Equation (5).
The gain of the first stage A I is given by Equation (6).
Here, for simplicity, g m is the transconductance gain of all unit size NMOS and PMOS transistors, r o is their output resistance, and R X is resistance at node V X . The auxiliary amplifier's gain is given by A aux = (g m4 R Y )/2, where R Y = r o4P ·g mCP2P r oCP2P R CMF r o5P . As R CMF << r o4P , r oCP2P , r o5P , R Y ≈ R CMF and A aux ≈ (g m4 R CMF )/2.
The gain of the output stage is given by Equation (7).
where R Out is R Out = r oOP ||r oON ||R L .
Thus, the open-loop DC gain A OLDC of the proposed op-amp is expressed by Equation (8).
A OLDC = A I A Out = (g m r o ) 2 /2 g mouteff R Out (8) where g mouteff = g mOP + A aux g mON and R Out = r OP ||r ON ||R L . The dominant pole is at node V X and is given by Equation (9).
where C X is given by C X = (1 + |A out |) C C . Thus, the gain-bandwidth product (GBW) of the proposed op-amp is given by Equation (10).
Besides the dominant pole, the proposed op-amp has two high-frequency poles: one at V Y and another at V Out . The output high-frequency pole f pOut is given in Equation (11).
The pole at node V Y is expressed by Equation (12).
where C Y is given by C Y = C gsON + C dBCP2P + C dB5P + C gdON 1 + A Out A VY + C gd5P and R Y = r o4p ·g mCP2P ·r oCP2P R CMF r o5P . The selection of R CMF plays an important role in determining a compromise between the gain of the auxiliary amplifier and the phase margin of the op-amp. To achieve a sufficient phase margin, f PY should be higher than the unity gain frequency of the op-amp. Thus, R CMF has to be selected in such a way that the pole of the node Y, i.e., f PY , is located at least a factor three higher than the op-amp's unity gain frequency, and in that case, R CMF << r o5P ,r o4P g mCP2P r oCP2P and R Y can be approximated as R Y ≈ R CMF . In this case, f PY has a minor effect on the op-amp's frequency response up to the unity gain frequncy f u , and Equation (12) can be simplified as below.
The zero is given by Equation (14).
The simplified transfer function of the proposed op-amp neglecting the pole at node Y can be approximated by Equation (15).
The small-signal model of the proposed op-amp is given in Figure 4.
where CY is given by . The selection of RCMF plays an important role in determining a compromise between the gain of the auxiliary amplifier and the phase margin of the op-amp. To achieve a sufficient phase margin, fPY should be higher than the unity gain frequency of the op-amp. Thus, RCMF has to be selected in such a way that the pole of the node Y, i.e., fPY, is located at least a factor three higher than the op-amp's unity gain frequency, and in that case, RCMF << ro5P,ro4PgmCP2ProCP2P and RY can be approximated as RY≈`RCMF. In this case, fPY has a minor effect on the op-amp's frequency response up to the unity gain frequncy fu, and Equation (12) can be simplified as below.
The simplified transfer function of the proposed op-amp neglecting the pole at node Y can be approximated by Equation (15) The small-signal model of the proposed op-amp is given in Figure 4.

Results
The proposed and conventional class-A op-amps are designed in 130 nm CMOS technology. The unit size transistors used in both op-amps are (W/L)N = (W/L)P = 10/0.27 (µm/µm). The compensation capacitor has a value CC = 4 pF for both op-amps. The compensation resistor RC has a value 8 kΩ for the proposed op-amp and 19 kΩ for the Conv-A op-amp. For a fair comparison, the output transistors of the Conv-A op-amp MOP are scaled by the same factor 8/0.7 and MON is by the same factor 5/1 as the proposed op-amp compared to the unit size transistors used in the circuit. They are simulated using the same bias current IB = 15 µA, and dual supply voltages VDD = +0.6 V and VSS = −0.6 V. Figure

Results
The proposed and conventional class-A op-amps are designed in 130 nm CMOS technology. The unit size transistors used in both op-amps are (W/L) N = (W/L) P = 10/0.27 (µm/µm). The compensation capacitor has a value C C = 4 pF for both op-amps. The compensation resistor R C has a value 8 kΩ for the proposed op-amp and 19 kΩ for the Conv-A op-amp. For a fair comparison, the output transistors of the Conv-A op-amp M OP are scaled by the same factor 8/0.7 and M ON is by the same factor 5/1 as the proposed op-amp compared to the unit size transistors used in the circuit. They are simulated using the same bias current I B = 15 µA, and dual supply voltages V DD = +0.6 V and V SS = −0.6 V.  Figure 6 shows the corresponding frequency response of the Conv-A op-amp with C L = 300 pF.
The unity gain frequency fu of the proposed op-amp for RL = 1 MΩ is 16.9 MHz and for RL = 200 Ω is 16.01 MHz. The small-signal figures of merit FOMSS of the proposed opamp are 28.8 and 27.2 for RL = 1 MΩ and 200 Ω. The Conv-A op-amp's FOMSS for similar loading conditions are 12.4 and 10.8. Thus, the proposed op-amp can drive a low-value resistive load (high-loading condition) by maintaining a relatively high open-loop gain. It can be seen that, as expected, the introduction of the auxiliary amplifier in the proposed op-amp leads to lower gain degradation (and consequently, lower gain errors) for lowervalued load resistors.   It can be seen that, as expected, the introduction of the auxiliary amplifier in the proposed op-amp leads to lower gain degradation (and consequently, lower gain errors) for lower-valued load resistors. Figure 7 shows the transient response of the proposed and Conv-A op-amp with R L = 1 MΩ and C L = 300 pF for a 500 kHz input pulse with 500 mVpp amplitude. It can be observed that the Conv-A op-amp cannot follow the input signal. From Figure 8, it can be asserted that this is because of the limitation of the peak negative output current, which corresponds to the quiescent current of the output branch in the Conv-A op-amp. From the pulse responses and load currents of the proposed and Conv-A op-amp for R L = 1 MΩ, it can be asserted that the proposed op-amp increases the negative slew rate by a factor of 20 compared with the Conv-A op-amp. The SR enhances by a large factor close to 20 from 0.36 V/µs for the Conv-A to 7.4 V/µs for the proposed op-amp. Therefore, the CE of the proposed and Conv-A op-amps are 15.6 and 0.8, respectively.  Figure 7 shows the transient response of the proposed and Conv-A op-amp with RL = 1 MΩ and CL = 300 pF for a 500 kHz input pulse with 500 mVpp amplitude. It can be observed that the Conv-A op-amp cannot follow the input signal. From Figure 8, it can be asserted that this is because of the limitation of the peak negative output current, which corresponds to the quiescent current of the output branch in the Conv-A op-amp. From the pulse responses and load currents of the proposed and Conv-A op-amp for RL = 1 MΩ, it can be asserted that the proposed op-amp increases the negative slew rate by a factor of 20 compared with the Conv-A op-amp. The SR enhances by a large factor close to 20 from 0.36 V/µs for the Conv-A to 7.4 V/µs for the proposed op-amp. Therefore, the CE of the proposed and Conv-A op-amps are 15.6 and 0.8, respectively. From Figure 9, it can be asserted that the proposed op-amp can drive both large capacitive and low-valued resistive loads. Figure 10 shows the output current in the 200 Ω load resistor for the Conv-A and proposed op-amps for 500 mVpp and 500 kHz input pulse. It can be seen that the proposed op-amp can provide 1.24 mA positive and negative peak From Figure 9, it can be asserted that the proposed op-amp can drive both large capacitive and low-valued resistive loads. Figure 10 shows the output current in the 200 Ω load resistor for the Conv-A and proposed op-amps for 500 mV pp and 500 kHz input pulse. It can be seen that the proposed op-amp can provide 1.24 mA positive and negative peak output currents to a 200 Ω resistive load for a 500 mV pp and 500 kHz input pulse. In contrast, the Conv-A op-amp with the same input signal can provide only a 105 µA negative output current, which is limited by the quiescent current of the output branch. Figure 8. Current in the load capacitance CL = 300 pF in the Conv-A and proposed op-amps for 500 kHz and 500 mVpp amplitude pulse inputs.
From Figure 9, it can be asserted that the proposed op-amp can drive both large capacitive and low-valued resistive loads. Figure 10 shows the output current in the 200 Ω load resistor for the Conv-A and proposed op-amps for 500 mVpp and 500 kHz input pulse. It can be seen that the proposed op-amp can provide 1.24 mA positive and negative peak output currents to a 200 Ω resistive load for a 500 mVpp and 500 kHz input pulse. In contrast, the Conv-A op-amp with the same input signal can provide only a 105 μA negative output current, which is limited by the quiescent current of the output branch.       The bandwidth (BW) is 29 MHz for R L = 1 MΩ and 26.4 MHz for R L = 200 Ω. In comparison, the Conv-A op-amp has 8.37 MHz and 4.6 MHz 3 dB bandwidths for similar loading conditions. It can be seen that the proposed op-amp has a higher bandwidth than the Conv-A op-amp.
A corner analysis of the proposed op-amp was performed to verify its robustness against temperature, process variations, and mismatches in the values of the design components. Table 1 shows the corner analysis of the op-amp employing typical 2% mismatches in the differential pair and the resistors used in the auxiliary amplifier. It can be asserted that, from the corner analysis, the proposed op-amp is robust against the temperature and process variations.  Comprehensive comparisons of the proposed op-amp's performance with state-ofthe-art op-amps and Conv-A op-amp are shown in Table 2. The proposed op-amp has the highest small-signal, dynamic, static current efficiency, and global figures of merits. It can be asserted that, from the comparison table, the proposed architecture can drive both resistive and capacitive load efficiently. The presence of the auxiliary amplifier in the prosed architecture makes this possible.

Conclusions
A simple class-AB Miller op-amp that can drive both resistive and capacitive loads is presented here. A compact auxiliary amplifier is used to provide the static class-AB operation and helps to achieve higher gain, bandwidth, and a well-defined output quiescent current. The proposed op-amp can provide a 13.9 dB higher open-loop gain, a factor 20 higher slew-rate, and a factor 3.3 to 5.7 higher bandwidth (in VF configuration) than the conventional op-amp at the expense of only 10% additional quiescent current compared to the Conv-A op-amp.