A New VCII Application: Sinusoidal Oscillators

: The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demon-strates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII − ). Interestingly, the same analysis shows that no canonic oscillator conﬁguration can be achieved using positive type VCII (VCII + ), since a single VCII + does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator conﬁgurations are the only possible ones and make use of two resistors, two capacitors and a single VCII − . Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.


Introduction
There has always been an interest in designing sinusoidal oscillators due to several applications in different areas such as communication, instrumentation, biomedical, etc. [1][2][3]. Compared to LC and RLC sinusoidal oscillators, RC-active type oscillators are advantageous from the integration point of view. In the early implementations of RC-active sinusoidal oscillators, operational amplifiers (Op-Amps) were used as active elements [4][5][6]. A systematic approach was introduced in [5] to design Op-Amp-based oscillators with a single active element and the minimum number of passive elements. The design method of [5] resulted in Op-Amp-based oscillator configurations composed of one active device, two capacitors and four resistors.
However, the limited frequency performance and slew rate of Op-Amps as well as their high power consumption imposed a restriction in the application of Op-Ampbased sinusoidal oscillators. A literature survey shows that, after revealing the potential capabilities of current-mode (CM) signal processing, efforts have been made to design RC-active sinusoidal oscillators using various CM active building blocks (ABBs) . Undoubtedly, second-generation current conveyor (CCII) as the main ABB of CM signal processing is the most widely used one for this purpose. Different approaches were employed to realize CCII-based oscillators. For example, in [8], the Op-Amps were replaced with composite current conveyors, resulting in CM oscillators. Unfortunately, this approach did not reach a simple realization because each amplifier could only be implemented with at least two CCIIs and two resistors. The extension of the approach presented in [5] was employed in [9] to synthesize CCII-based oscillators. Although the resulting sinusoidal oscillators enjoyed a canonic structure with the minimum possible number of elements, they were still not readily cascadable, i.e., they required additional voltage buffers to be actually usable in a real-world application. Most of the other CM oscillator realizations reported in  using different ABBs instead of CCIIs also suffered from a large number of active and/or passive elements.
Recently, the dual circuit of CCII, called second-generation voltage conveyor (VCII), has attracted the attention of researchers [35][36][37][38][39][40][41][42][43][44]. In particular, the recent study reported in [35,36] showed that this device helps to benefit from CM signal processing features and overcome the limitations in CCII-based circuits. Particularly, unlike CCII, there is a low-impedance voltage output port in VCII which allows it to be easily cascaded with other high-impedance processing blocks, without the need for extra voltage buffers in voltage output applications. Compared to CCII, VCII has proven superior performance in many applications [37]; up to now, this device has not been employed in the realization of sinusoidal oscillators.
However, the VCII, combining the advantages of CM processing with a voltage-mode interfacing, could provide sinusoidal oscillators operating up to higher frequency than Op-Amp-based ones. Moreover, breaking the gain-bandwidth tradeoff, it could ease decoupling oscillation frequency and oscillation condition even at the higher end of the spectrum. Among the possible implementations of VCII-based sinusoidal oscillators, those requiring the minimum number of (active and) passive components, so-called canonic, are of particular interest to minimize silicon area and power consumption. The aim of this work is only to present possible VCII-based canonic sinusoidal oscillator realizations, replicating the general approach presented in [5,9] which, as previously anticipated, has been used to synthesize Op-Amp-based and CCII-based sinusoidal oscillators. We will show that it is possible to implement sinusoidal oscillators with a minimum number of elements using a single negative type VCII (VCII − ), two resistors and two capacitors, so demonstrating a new practical application of the VCII. The notable advantage of the proposed VCII − -based oscillator is that it is easily cascadable from port Z of VCII − , alleviating the need for any extra voltage buffer. Moreover, THD values are low also for higher frequency oscillators. However, the results of this study show that the applied approach does not reach any canonic configuration using positive type VCII (VCII + ). The effect of non-idealities in the VCII has been considered, and the proposed approach has been tested by both simulations and measurement results.
The organization of this paper is the following: in Section 2, an introduction on the VCII as active building block as well as the basics of the general configuration of the VCII-based oscillator is introduced. Section 3 proposes, in detail, the study on the possible realizations of VCII-based oscillators, and the effects of non-idealities in VCII are considered in Section 4. Simulations and measurement results are given in Section 5. Finally, Section 6 concludes the paper.

General Configuration of the VCII-Based Oscillator
The symbolic representation and internal structure of VCII are shown in Figure 1. In this block, Y is a low-impedance (ideally zero) current input terminal. The current entering into Y node is transferred to X terminal which is a high-impedance (ideally infinity) current output port. The voltage produced at X terminal is transferred to Z terminal which is a low-impedance (ideally zero) voltage output terminal. The relationship between port currents and voltages are given by: v Z = αv X , i X = βi Y and v Y = 0. In the ideal case we have α = 1 and β = ± 1. If β = 1 we are considering a VCII + , whereas if β = −1 we have a VCII − .
Using the approach presented in [5,9], the general configuration of an RC-active oscillator based on a single VCII is shown in Figure 2, where N GC represents 4-terminal network consisting of only capacitors and conductances. Using the approach presented in [5,9], the general configuration of an RC-active oscillator based on a single VCII is shown in Figure 2, where represents 4-terminal network consisting of only capacitors and conductances. The characteristic equation (CE) of the whole system can be calculated replacing, in the circuit of Figure 2, the equivalent model of a VCII of Figure 1b and considering a fictitious input at the node (of course, no input signal will be present in an actual oscillator circuit), as shown in Figure    Using the approach presented in [5,9], the general configuration of an RC-active oscillator based on a single VCII is shown in Figure 2, where represents 4-terminal network consisting of only capacitors and conductances. The characteristic equation (CE) of the whole system can be calculated replacing, in the circuit of Figure 2, the equivalent model of a VCII of Figure 1b and considering a fictitious input at the node (of course, no input signal will be present in an actual oscillator circuit), as shown in Figure 3a at the building block level and Figure 3b    The characteristic equation (CE) of the whole system can be calculated replacing, in the circuit of Figure 2, the equivalent model of a VCII of Figure 1b and considering a fictitious input at the Y node (of course, no input signal will be present in an actual oscillator circuit), as shown in Figure 3a   Using the approach presented in [5,9], the general configuration of an RC-active oscillator based on a single VCII is shown in Figure 2, where represents 4-terminal network consisting of only capacitors and conductances. The characteristic equation (CE) of the whole system can be calculated replacing, in the circuit of Figure 2, the equivalent model of a VCII of Figure 1b and considering a fictitious input at the node (of course, no input signal will be present in an actual oscillator circuit), as shown in Figure 3a at the building block level and Figure 3b    The configurations in Figures 2 and 3 can hence be seen as a positive feedback system for which the current transfer function (TF) is given by: Since A(s) = ±1 and β(s) = i f (s)/i out (s), (1) becomes: However, since from Figure 3b i out = −i X and in an oscillator circuit there is no input (i in = 0), we have i f = i Y and the TF is given by: From (3), we can derive the condition of existence (CE) as: By assuming v Z = v X , v Y = 0, the transconductance functions of the passive network in Figure 2 can be expressed by a rational expression as: where N X (s) and N Y (s) are the numerators at X and Z nodes, respectively, while D(s) is a common denominator. Using (5) and (6) in (4), the CE becomes: In (7), the plus and minus signs are for VCII − and VCII + respectively. To ensure a pure sinusoidal oscillation, the CE in (7) should be a second-order polynomial with purely imaginary roots. This requires the network N GC to include at least two capacitors. It has to be noted that, in Figure 2, by using a VCII + rather than a VCII − , at least three capacitors are required to provide a phase shift to generate a positive feedback loop. Therefore, no canonic oscillator is possible using VCII + , and for the following, we will consider the VCII in Figure 2 as a VCII − . By then assuming a network with only two capacitors, Equation (7) will be in the form: In order to start the oscillation, the following commonly known criteria must be satisfied: with c = 0, a = 0, so that, according to the Barkhausen criterion, purely imaginary poles for the closed-loop transfer function are obtained. The oscillation frequency is:

Oscillator Circuits
In this section we analyze the possible VCII − -based oscillators based on the scheme of Figure 2. The passive N GC is assumed as a general n-node network consisting of b possible branches between two nodes. Each node is a junction where two or more branches are connected, and each branch is an admittance connected between two nodes represented as: In the following, we analyze the CE to see if oscillation is possible for the particular case study of a five-node network. From this analysis we see that for a four-node network it is not possible to obtain a second-order polynomial for (7), whereas for a six-node network (or more) only non-canonic oscillators using more than the minimum number of passive components are possible.

N GC as a Five-Node Network
In Figure 4 we assume N GC as a five-node network. We start analyzing this network by performing KCL at node Y as reported in the following: Since no current is flowing into Y 8 and Y 9 , these admittances can be assumed as open circuit (Y 8 = Y 9 = 0). Routine analysis of Figure 4 results in i 3 as: Using (13)- (14), we have: Similar analysis for i x results:

Oscillator Circuits
In this section we analyze the possible VCII − -based oscillators based on the scheme of Figure 2. The passive NGC is assumed as a general -node network consisting of b possible branches between two nodes. Each node is a junction where two or more branches are connected, and each branch is an admittance connected between two nodes represented as: In the following, we analyze the CE to see if oscillation is possible for the particular case study of a five-node network. From this analysis we see that for a four-node network it is not possible to obtain a second-order polynomial for (7), whereas for a six-node network (or more) only non-canonic oscillators using more than the minimum number of passive components are possible.

NGC as a Five-Node Network
In Figure 4 we assume NGC as a five-node network. We start analyzing this network by performing KCL at node Y as reported in the following: Since no current is flowing into Y8 and Y9, these admittances can be assumed as open circuit (Y8 = Y9 = 0). Routine analysis of Figure 4 results in i3 as: Using (13)-(14), we have: Similar analysis for ix results: Using (15) and (16) in (7), the CE of the five-node network is found as: Figure 4. The N GC as a five-node network.
Using (15) and (16) in (7), the CE of the five-node network is found as: It can be noticed that CE does not depend on Y 7 , . . . , Y 10 which means that these branches can be assumed to be open circuit. For the other branches we can make different choices. If two branches have non-zero admittances, the following CEs are possible: In the general case, (18) can be expressed as By assuming Y a = sC a + G a and Y b = sC b + G b , (19) can be written as: From (20) it is not possible to have imaginary roots. Therefore, in case of two non-zero branches, no oscillation is possible.
Finally, we investigate the possibility of achieving oscillations from (17) in the case that three branches of N GC present non-zero admittance. For In both these cases, the CE has the general form of (19).
, the CE is obtained as: The CEs of (21) and (22) do not result in pure imaginary roots; therefore, these cases cannot give oscillator topologies.
Considering instead the cases ( , the CE has the following general form: It is easy to verify that the CE in (23) cannot be associated with an oscillator topology if only two capacitors are used (we need three of them at least).
Finally, for (Y 1 = Y 3 = Y 5 = 0) and (Y 2 = Y 4 = Y 6 = 0), the CEs will be given by (24a) and (24b), respectively: which are equations with the general form: In (25), oscillation condition is related to the choice of Y c and Y a or Y b as a capacitance.
In order to design an oscillator with the minimum number of components, we now have to verify the choice of the components in (25). It can be demonstrated that it is possible to have a minimum of two capacitors and at least two resistors in order to have a constant term in the constituting equation. In fact, with this choice we obtain a complete polynomial. In this case, having only three branches of the type sC + G with C ≥ 0, G ≥ 0, it is a matter of choosing an admittance between Y a , Y b , Y c of the type sC + G; the two remaining admittances will be a capacitance sC, and a conductance G. Inserting all possible combinations of options into (25), two sets of CEs which show imaginary roots are obtained. For For From (26) and (27), the oscillation condition (C o ) and oscillation frequency (ω 0 ) for the two cases are obtained respectively as: Thus, the minimum number of elements necessary to obtain an oscillator based on the scheme of Figure 2 is four, being two of these capacitors and two resistors. Considering the two cases (Y 1 = Y 3 = Y 5 = 0) and (Y 2 = Y 4 = Y 6 = 0) and the possible choices for Y a and Y b , we obtain a total of four canonic oscillators, corresponding to the following CEs: However, this number is reduced again to two if we consider that from each of the cases (Y 1 = Y 3 = Y 5 = 0) and (Y 2 = Y 4 = Y 6 = 0) we obtain two equal oscillators if we exchange the order of the elements which are connected in series. These two configurations are shown in Figure 5, and the corresponding transfer functions, oscillation frequencies ω 0 and oscillation conditions are reported in Table 1. The oscillation frequencies and oscillation conditions in (28) show a strong interdependence since they are functions of the same parameters. Since the oscillation condition requires that the sum of the ratios of the capacitances and of the conductances is constant and equal to 1, a possible strategy for frequency tuning requires varying both resistors or both capacitors, maintaining their ratio constant. For example, a ratio of 2 between C a and C c can be obtained by using two parallel capacitors equal to C a to obtain C c ; all three capacitors can be varied together; thus their ratio remains constant unless there are mismatches and the effect of parasitics.

Analysis of Parasitic Effects: A Case Study
The only two possible canonic topologies for the VCII-based oscillator are synthesized in Figure 6, where ZA and ZB are a series-connected RC network and a parallel-connected RC network; we define tA = RACA and tB = RBCB as the time constants associated with these networks. The two oscillator topologies shown in Figure 6  where Ri = 1/Gi. From Figure 6, the oscillation condition can be obtained as: where and are the VCII current and voltage gains (ideally both equal to 1), and the oscillation frequency is given by:    T I (s) = −

Analysis of Parasitic Effects: A Case Study
The only two possible canonic topologies for the VCII-based oscillator are synthesized in Figure 6, where Z A and Z B are a series-connected RC network and a parallel-connected RC network; we define t A = R A C A and t B = R B C B as the time constants associated with these networks. The two oscillator topologies shown in Figure 6 correspond to the cases: Type II : where R i = 1/G i . From Figure 6, the oscillation condition can be obtained as: where β and α are the VCII current and voltage gains (ideally both equal to 1), and the oscillation frequency is given by: The oscillation condition and the oscillation frequency are affected by the non-idealities of the VCII, i.e., finite port impedances, gain errors (a < 1, |b| < 1) and poles of the voltage and current buffers. In order to analyze the effects of these non-idealities on the oscillator behavior, a model of a real VCII has been developed and implemented (see Figure 7), able to take into account the non-idealities. The oscillation condition and the oscillation frequency are affected by the non-idealities of the VCII, i.e., finite port impedances, gain errors (a < 1, |b| < 1) and poles of the voltage and current buffers. In order to analyze the effects of these non-idealities on the oscillator behavior, a model of a real VCII has been developed and implemented (see Figure 7), able to take into account the non-idealities. In the general case, we can model the VCII with the first-order transfer functions and complex port impedances The oscillation condition and the oscillation frequency are affected by the non-idealities of the VCII, i.e., finite port impedances, gain errors (a < 1, |b| < 1) and poles of the voltage and current buffers. In order to analyze the effects of these non-idealities on the oscillator behavior, a model of a real VCII has been developed and implemented (see Figure 7), able to take into account the non-idealities. In the general case, we can model the VCII with the first-order transfer functions and complex port impedances In the general case, we can model the VCII with the first-order transfer functions and complex port impedances In order to better understand the effects of non-idealities and to compare the performance of the two topologies in Figure 5, different cases have been considered under the hypothesis that the ideal design has been carried out starting from the oscillation condition (34). When the non-idealities of the VCII are taken into account, Equation (34) becomes By a simple inspection of the impedances Z A and Z B given by (33), and of the port impedances (38)- (40), it is evident that the Type I canonic oscillator should be less affected by non-idealities. In fact, in this case Y x can be absorbed in Z A (G x and C x are summed to 1/R 5 and C 5 , respectively), and Z y and Z z in Z B : a parallel RC network is used in parallel to a port impedance modeled as an RC parallel network, and a series impedance is connected in series to port impedances modeled as RL series networks. In contrast, for the Type II canonic oscillator, a series network is connected in parallel to the parallel RC port impedance, and a parallel RC network is connected in series to LR series port impedances, thus non-ideal port impedances alter Z A and Z B more significantly. The Type I canonic VCII-based oscillator seems therefore more suited to a practical realization, and it has been selected for further analysis.

Resistive Port Impedances
If only the resistive parasitics G x , R y and R z in (39)- (41) are considered, the oscillation condition for the Type I canonic oscillator becomes: It is evident from (42) that the effect of the port impedances is limited, since they are simply summed to the ones from the NGC network (that have to be chosen as much larger than the corresponding parasitics to make them negligible). The oscillation frequency in Table 1 is modified as follows: where R 1 = R 1 + R y + R z and G 5 = 1/R 5 = G 5 + G x , and the oscillation condition becomes α |β| If the parasitic capacitance C x at the X terminal is also considered, Equations (43) and (44) have to be slightly modified by considering G 5 = C 5 + C x instead of C 5 . Inductances L y and L z can be neglected in several applications and have not been considered in the following. However, for the sake of completeness, we report below the expression for the oscillation frequency when inductive parasitics are also considered:

Single-Pole Transfer Functions
If the non-ideal transfer functions in (36) and (37) are also considered in addition to the terminal resistive parasitics in (38)- (40), the denominator of the oscillation condition in (34) becomes of fourth degree: α |β| sG 5 R 5 as 4 + bs 3 + cs 2 + ds + e = 1 (46) Prime variables are considered for R 5 , G 5 and R 1 to account for parasitic resistances R y and R z and admittance Y x , as in the previous subsection, and we have A real value is obtained for the left-hand side, under the hypothesis of a purely imaginary denominator. By equating to zero the real part of the denominator at ω = ω 0 , we get: where c is given by (47c). The approximation 4a c 2 << 1 is justified under the hypothesis that the parasitic time constants τ x and τ z are significantly lower than the time constants τ A = R 5 C 5 and τ B = R 1 C 3 . Finally, the oscillation frequency ω 0 can be expressed in terms of the ideal value ω 0 , by using the expression of coefficient c: Under the simplifying assumptions τ x = τ y = τ par and τ A = τ B = τ, the relative error on the oscillation frequency (1 − ω o /ω o ) can be readily expressed as a function of the ratio τ par /τ, thus providing a design guideline for the bandwidth of the VCII transfer functions.
The graph in Figure 8 shows that errors lower than 10% can be obtained if the time constant ratio is lower than 0.06.
Ry and Rz and admittance Yx, as in the previous subsection, and we have A real value is obtained for the left-hand side, under the hypothesis of a purely imaginary denominator. By equating to zero the real part of the denominator at = , we get: where c is given by (47.c). The approximation << 1 is justified under the hypothesis that the parasitic time constants and are significantly lower than the time constants = ′ ′ and = ′ . Finally, the oscillation frequency ′ can be expressed in terms of the ideal value , by using the expression of coefficient c: Under the simplifying assumptions x = y = par and A = B = , the relative error on the oscillation frequency (1 − ⁄ ) can be readily expressed as a function of the ratio / , thus providing a design guideline for the bandwidth of the VCII transfer functions. The graph in Figure 8 shows that errors lower than 10% can be obtained if the time constant ratio is lower than 0.06.

Experimental Results
The performance of the Type I canonic oscillator of Figure 5a has been verified by both LTSpice simulations and experimental results. In particular, the approximated ex-

Experimental Results
The performance of the Type I canonic oscillator of Figure 5a has been verified by both LTSpice simulations and experimental results. In particular, the approximated expression for ω 0 in (49) has been checked for different values of τ and τ x = τ z , and errors lower than 1% have been found.
Then, we have used the commercially available AD844 to configure a VCII − as shown in Figure 9. A single VCII is realizable using two AD844 ICs, whose Spice model can be found in [45]. The situation is quite different in the case of an integrated design, where a single VCII block can be exploited to design the oscillator, as shown in the previous sections.
The circuit was supplied with a dual ±5 V voltage, achieving a total power consumption of 14 mA.
Firstly, simulation of the topology in Figure 5a has been carried out to evaluate performance in terms of robustness to parasitics, and to estimate the achievable THD. In particular, the circuit has been designed with C 3 = 2C 5 = 2 nF and R 5 = 2R 1 = 15 kΩ, and an oscillation frequency f 0 = 10.6 kHz was expected.
However, AD844 parasitics can slightly change the oscillation frequency and/or cause failing of oscillation condition: in this case, starting from the nominal design, the resistance R 1 can be changed (to 7.3 kΩ in the present case, see the schematic in Figure 10) to allow fulfillment of oscillation condition in (41): the obtained oscillation frequency is f 0 = 10.8 kHz, as shown in Figure 11.
A model for the VCII composed of AD844 components, shown in Figure 9, has been extracted from Spice simulations according to the equations presented in Section 4. At terminal X, we have found C x = 5.5 pF in parallel with a resistor R x = 3 MΩ. Purely resistive input impedances have been extracted at node Y (R y = 50 Ω) and Z (R z = 15 Ω). Finally, a dominant pole has been found for both the transfer function α(s) at f = 49 MHz (corresponding to τ x = 3.25 ns), and for β(s) at f = 764 MHz (τ z = 208 ps). lower than 1% have been found.
Then, we have used the commercially available AD844 to configure a VCII − as shown in Figure 9. A single VCII is realizable using two AD844 ICs, whose Spice model can be found in [45]. The situation is quite different in the case of an integrated design, where a single VCII block can be exploited to design the oscillator, as shown in the previous sections.
The circuit was supplied with a dual ±5 V voltage, achieving a total power consumption of 14 mA.
Firstly, simulation of the topology in Figure 5a has been carried out to evaluate performance in terms of robustness to parasitics, and to estimate the achievable THD. In particular, the circuit has been designed with = 2 = 2 nF and = 2 = 15 kΩ, and an oscillation frequency f0 = 10.6 kHz was expected. However, AD844 parasitics can slightly change the oscillation frequency and/or cause failing of oscillation condition: in this case, starting from the nominal design, the resistance can be changed (to 7.3 kΩ in the present case, see the schematic in Figure  10) to allow fulfillment of oscillation condition in (41): the obtained oscillation frequency is f0 = 10.8 kHz, as shown in Figure 11.
A model for the VCII composed of AD844 components, shown in Figure 9, has been extracted from Spice simulations according to the equations presented in Section 4. At terminal X, we have found Cx = 5.5 pF in parallel with a resistor Rx = 3 MΩ. Purely resistive input impedances have been extracted at node Y (Ry = 50 Ω) and Z (Rz = 15 Ω). Finally, a dominant pole has been found for both the transfer function ( ) at f = 49 MHz (corresponding to = 3.25 ns), and for ( ) at f = 764 MHz ( = 208 ps).  The element values used for the different design case studies, the simulated THD and the oscillation frequency evaluated with both the LTSpice AD844 non-linear model and with the VCII linear model, including parasitics, are summarized in Table 2. The linear model is accurate enough to be used for circuit design, and excellent simulated performance has been achieved in terms of THD with the proposed VCII topology. The element values used for the different design case studies, the simulated THD and the oscillation frequency evaluated with both the LTSpice AD844 non-linear model and with the VCII linear model, including parasitics, are summarized in Table 2. The linear model is accurate enough to be used for circuit design, and excellent simulated performance has been achieved in terms of THD with the proposed VCII topology. The element values used for the different design case studies, the simulated THD and the oscillation frequency evaluated with both the LTSpice AD844 non-linear model and with the VCII linear model, including parasitics, are summarized in Table 2. The linear model is accurate enough to be used for circuit design, and excellent simulated performance has been achieved in terms of THD with the proposed VCII topology. Figure 11. Simulated output spectrum of the oscillator shown in Figure 10. Finally, experimental verification of performance has been carried out, exploiting the test bench shown in Figure 12: for data acquisition, the Digilent Analog Discovery 2™ board was used [46]. The design of Figure 5a was implemented as the reference topology for the oscillator. Measurements were carried out in the range (10-10 6 ) Hz and are reported in Table 3. In agreement with simulation results, the oscillator shows a very low Figure 11. Simulated output spectrum of the oscillator shown in Figure 10. Finally, experimental verification of performance has been carried out, exploiting the test bench shown in Figure 12: for data acquisition, the Digilent Analog Discovery 2™ board was used [46]. The design of Figure 5a was implemented as the reference topology for the oscillator. Measurements were carried out in the range (10-10 6 ) Hz and are reported in Table 3. In agreement with simulation results, the oscillator shows a very low THD value even at 1 MHz (considering 10 harmonics). The average relative frequency error between measured and ideal values is −5.2% and is comparable with tolerances of the passive components. THD value even at 1 MHz (considering 10 harmonics). The average relative frequency error between measured and ideal values is −5.2% and is comparable with tolerances of the passive components. An example of the output signal, both in the time and frequency domains, is reported in Figure 13a,b for a frequency of 1 MHz. Figure 14 shows the THD and frequency error trends vs. frequency.   An example of the output signal, both in the time and frequency domains, is reported in Figure 13a,b for a frequency of 1 MHz.
An example of the output signal, both in the time and frequency domains, is reported in Figure 13a,b for a frequency of 1 MHz. Figure 14 shows the THD and frequency error trends vs. frequency.

Conclusions
By means of a systematic analysis, the possibility of realizing VCII-based oscillators is studied and demonstrated. The investigation results in a pair of new canonic oscillators based on VCII − . However, it is shown that, using the systematic approach, no oscillator configuration is possible using VCII+. The two found oscillator configurations are the only possible ones which use only two resistors, two capacitors and a single VCII − . Compared to Op-Amp-based oscillators, designed using the same systematic approach which employs two capacitors and four resistors, the proposed VCII-based oscillator is preferred in terms of low number of capacitors and resistances. Another interesting feature of the found VCIIbased oscillator is that the produced sinusoidal output signal is easily available through the low output impedance Z port, while the CCII-based oscillators designed using the same systematic approach requires an additional voltage buffer for practical use. Simulations and experimental results using AD844 as VCII are reported to validate the theory.
A comparison with oscillator topologies based on different ABBs, with particular attention to canonic topologies, is reported in Table 4. The table reports the type of active building block (ABB) the oscillator is based on, the number of active and passive components, specifying how many of them are grounded, the availability of a quadrature output and the independence of oscillation condition from oscillation frequency that allows tuning the oscillator acting on a single component. It has to be noted that the independence from the oscillation condition on oscillation frequency often requires additional passive (and sometimes also active) components, thus resulting in non-canonic topologies. Notable exceptions are the oscillators of [21,26] that use complex ABBs with gain, whose value contributes to satisfying the oscillation condition.