Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits

: Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μ m/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.


Introduction
Artificial neural networks (ANNs) are the core of artificial intelligence (AI) in next generation systems that mimic the parallel processing capabilities of the human brain. One important characteristic of the distributed processing element of the brain, the neuron, is to deal with chaos through its hysteretic I/O response [1]. It is shown that this characteristic of a neuron makes ANNs stable [2] and converge more rapidly [3]. Additionally, the artificial neuron has to be small and consume minimal power to be able to be integrated into mass numbers [4].
CMOS STs can be categorized based on their mode of operation (voltage or current), inputs (single or differential input), outputs (inverting or noninverting), and hysteresis controls (fixed or programmable). The simplest and most compact STs are the ones with fixed hysteresis, and single voltage input and single voltage output types. Six well known single input/single output ST topologies are investigated in this paper: Dokic [5] (three types: N, P, and CMOS), Steyaert [6], Pedroni [7], and Al-Sarawi [8]. In this paper, we show how to derive the hysteresis voltages accurately for these STs, and determine their design limitations and sensitivities to process variations. For the analysis and design of an ST circuit, three fundamental input-output (I/O) parameters are considered: high-to-low switching voltage (VHL), low-to-high switching voltage (VLH), and hysteresis voltage (ΔVH = VHL − VLH), as shown in Figure 1. The hysteresis offset (VHO) in Figure 1 can be calculated as (VHO = VLH + ∆VH/2).
Detailed analysis and the hand calculation equations of each topology are presented in Section 2. Each topology is extensively simulated at different corners of the selected CMOS process. The simulation results are presented in Section 3, as are the comparisons between hand calculations and the simulation results of each topology, in addition to the comparisons between the six topologies. The conclusion is presented in Section 4.

Analysis of Schmitt Trigger (ST) Circuits
Six well known single input and single output ST topologies and their variants are analyzed in this section, providing transistor level and more accurate and intuitive design equations. They are Dokic [5] (three types), Steyaert [6], Pedroni [7], and Al-Sarawi [8] STs. We used long-channel MOSFET models and high supply voltage process in this section. Equations (1) and (2) are the quadratic MOSFET transistor model equations that were used for the analysis in saturation (SAT) and linear/triode (LIN) regions, respectively [45]. The threshold voltage equation was modified slightly, linearizing bulk-to-source voltage dependency as Vthx = Vth0 + ψ•VSB. Here, ψ is defined as ψ = n•GAMMA•PHI, where GAMMA is the back-gate effect parameter, PHI is the surface potential, and n is a fitting parameter (0.3 < n < 0.5) which is determined through the simulation.

Dokic Schmitt Trigger Circuits
Dokic proposed three ST topologies in [5]: N-type, P-type, and CMOS-type. These topologies are investigated and detailed, and more accurate design equations for VHL, VLH, and ΔVH are derived. Figure 2a shows the N-type Dokic ST [5]. It is composed of four transistors and its hysteresis is shown in Figure 2b. Depending on how the input signal changes, two I/O characteristics can be observed. If the input goes from low (0) to high (VDD), the output changes from high to low at VHL. If the input goes from high (VDD) to low (0), the output changes from low (0) to high (VDD) at VLH. The VHL and VLH can be found when the input and output voltages are equal to each other at operating points OP1 and OP2, respectively, as marked in Figure 2b.

VHL Voltage
From Figure 2a, in the steady-state and when input is 0 V, the transistors M1 and M2 are OFF, M3 is in the deep LIN region where Vds3 is close to 0 V, and M4 can be considered in the subthreshold region, where Vgs4 < Vthn4 while the output is VDD. The node voltage V1 would be (VDD -Vthn4) and rising. When the input is increased and greater than Vthn0, M1 turns ON, discharging V1 to a switching point. Since Vsb2 = Vsb4 > Vthn0, M2 is still OFF and M4 is in SAT. M2 turns ON only when Vin is Vthn0 above the V1 voltage. Before M2 turns on, the V1 can be found by equating the drain currents of transistors M1 and M4. The general V1 equation, including body-effect where Vthn4 ≈ Vthn0 + ψ•V1, is: where 1n = When Vin further increases, V1 drops further, and finally, M2 turns ON. Then, the output node starts discharging, first turning M4 OFF and then turning M3 ON during this high to low transition. M2 turns ON when Vin(min) > V1 + Vthn2. Vin(min) could be considered as the threshold voltage of the series combination of M1 and M2, or Vthnx. Using (4), it can be found as follows: in(min) ≥ + thn2 = + thn0 + ⋅ = DD + 1n thn0 − 1n in(min) (6) When Vin = VHL, Dokic [5] assumes that M1 works in LIN, and M2 and M3 are in SAT regions, while M4 is OFF. However, series transistors M1 and M2 (Figure 2c) work in two different operation regions (M1 in LIN, M2 in SAT) that could be simplified into a single NMOS (Mx) transistor working in SAT with an equivalent threshold voltage of Vthnx, and β = βxn, as follows: using (9) in (10): (11) and assuming that Vthn1 ≅ Vthn2 = Vthn0, where ψ = 0, and Ids1 = Ids2 = Idsx, Equation (11) becomes, where The VHL of the N-type Dokic ST can now be found by equating the drain currents of the transistors M3 and Mx shown in Figure 2c, assuming that both are working in SAT region at OP1: where, 1n = and 2n = xn (16) VLH Voltage The VLH can be found by considering M4 as being OFF right before the output transition from low to high which occurs at OP2 (Vin = Vout = VLH), and by equating the drain current of M3 to that of Mx, which both work in SAT. It is important to note here that the current of Mx is equal to that of M2 (as in (13)) in which βxn, Vthn0, and α1n, and α2n from Equation (16) are used.
Hysteresis Voltage The hysteresis voltage of the N-type Dokic ST can then be derived by using (15) and (17) as: Compared to Dokic's original hysteresis equation (Equation (7) in [5]), (18) provides a transistorlevel design strategy, that the hysteresis voltage could be maximized by minimizing α1n and by maximizing α2n parameters while ensuring that the individual transistor parameters satisfy β4 > β1 and β3 < βxn. Figure 3 shows the P-type Dokic ST [5]. It is the complementary version of the N-type and has the same hysteresis characteristics. Transistors are numbered the same as the N-type as shown in Figure 2 and the analysis is carried out following the same process presented in the previous section. The VHL and VLH of the P-type Dokic ST can be found when input and output voltages are equal at operating points OP1 and OP2 as shown in Figure 3. The design equations and parameters for the P-type Dokic ST can be derived as: (20) and the hysteresis voltage:

P-Type ST by Dokic
Compared to Dokic's original hysteresis equation (Equation (13) in [5]), (21) provides a transistor-level design strategy, that the hysteresis voltage could be maximized by minimizing both α1p and α2p parameters while ensuring the individual transistor parameters satisfies β4 > β1 and βxp < β3 conditions. Figure 4 shows the CMOS type Dokic ST circuit [5]. It is composed of six transistors and its hysteresis is shown in Figure 4b. Depending on how the input signal changes, two I/O characteristics can be observed. If the input goes from low (0) to high (VDD) voltage level, the output state is changed at VHL where the output goes from high (VDD) to low (0) and vice versa, it switches from low (0) to high (VDD) at VLH. The VHL and VLH can be found when the input and output voltages are equal at operating points OP1 and OP2, as shown in Figure 4b.

VLH Voltage
When the input is VDD, the output is close to 0 V and M1, M2, and M5 are OFF, while M6 operates in the subthreshold region. M3 and M4 are in the deep LIN region where Vds3,4 ≈ 0, and Ids3,4 ≈ 0. V1 approaches but remains below |Vthp6| and is continuously discharged by the subthreshold current of M6. When Vin drops a |Vthcp| below VDD, the series combination of M1 and M2 (MCp) turns ON and works in the SAT region. During this time, M3 still works in SAT, while M5 is OFF and M4 is in LIN, which keeps V2 voltage close to 0 V. Thus, the VLH voltage could be determined by equating the SAT current of the transistor MCp to that of MCn formed by the series combination of M3 and M4, while assuming V2 = 0. This means that MCn will have Vthn0 as the threshold voltage, while the threshold voltage of MCp will be |Vthcp|, the same as |Vthpx| in Equation (22). Thus, the VLH can be derived as: When the input is 0 V, the output is close to VDD and transistors M3, M4, and M6 are OFF, while M5 operates in the subthreshold region. Transistors M1 and M2 are in the deep LIN region where Vsd1,2 ≈ 0, and Isd1,2 ≈ 0. V2 approaches but remains below VDD and is continuously charged by the subthreshold current of M5. When Vin increases a Vthcn above 0 V, the series combination of M3 and M4 (MCn) turns ON and into the SAT region. During this time, M2 still works in SAT, while M6 is OFF and M1 is in the LIN region, which keeps V1 voltage close to VDD. Thus, the VHL voltage could be determined by equating the SAT current of transistor MCn to that of MCp formed by the series combination of M1 and M2, while assuming V1 = VDD. This means that MCp will have |Vthp0| as threshold voltage, while the threshold voltage of MCn will be Vthcn, the same as Vthnx in Equation (7). Thus, VHL can be derived as: where = and thcn = DD Hysteresis Voltage The hysteresis voltage can then be derived by using Equations (23) and (25), as follows: Compared to Dokic's original hysteresis equation (Equation (16) in [5]), (27) provides a transistor-level design strategy, that hysteresis voltage could be adjusted accordingly. The design parameters sensitivity (VHL, VLH, and ∆VH) in terms of the individual transistor parameters (α1, α2, α3) can also be determined by using the new design Equations (23), (25) and (27), which provides better insight for the design of CMOS-type Dokic ST.
The new design equations for N-, P-, and CMOS-type Dokic ST presented in this section also provides better hand calculation accuracy in the wide process, supply, and device parameters variation as presented in the next section. Figure 5a shows the CMOS type ST circuit by Steyaert [6]. It is composed of five transistors and has the hysteresis that is shown in Figure 5b. Depending on how the input signal changes, two I/O characteristics can be observed. If the input goes from low (0) to high (VDD), the output state changes at VLH, where the output goes from low (0) to high (VDD) supply voltage. If the input goes from high (VDD) to (0) low, in this case, the output changes its value at VHL, where the output value goes from high (VDD) to (0) low. The VHL and VLH can be found when input and output voltages are equal at the operating points OP1 and OP2, as shown in Figure 5b. During the analysis, we will assume that, without M5, the switching voltages of the two inverters are the same. Thus, the device sizes of M1 and M3 and M1 and M3 are the same. We also assume that there is a slight delay between voltages Vin and Vout due to the loading at the V1 and output nodes.

VLH Voltage
When the input is low (0 V), V1 is high (VDD). Transistors M2 and M3 are ON while M1, M4, and M5 are OFF. At OP1, the VLH voltage is determined by equating the SAT currents of M1 and M2, like a regular CMOS inverter. Thus, the VLH can be derived as: This formulation is the same as the one presented by Steyaert as Equation (1) in [6].

VHL Voltage
When the input is high (VDD), V1 is low (0 V). Transistors M2 and M3 are OFF while M1, M4, and M5 are ON. At OP2, M2 turns ON, and the VHL voltage could be determined by equating the SAT currents of M1, M2, and M5 while ignoring the channel-length modulation parameter (λ) of the transistors as follows: and The formulation presented by Steyaert (Equation (2) in [6]) is given below, which is much simpler than Equation (30) above, but inaccurate for hand calculations as discussed in the next section.

Hysteresis Voltage
The hysteresis voltage can then be derived by using Equations (28) and (30) as: Compared with the Steyaert's formula, Equation (34) is more accurate, but less intuitive in designing the ST circuit. More accurate hysteresis voltage could be derived if we include the channellength modulation mechanism, but the equation becomes more complicated and less intuitive. Figure 6 shows the non-inverting ST by Pedroni [7]. It is composed of six transistors and its hysteresis is shown in Figure 6a. When the input goes from low (0) to high (VDD) voltage level, the output state changes at VLH where the output goes from low (0) to high (VDD). If the input goes from high (VDD) to (0) low, the output changes at VHL, where the output goes from high (VDD) to (0) low. The VHL is defined by the switching point of the inverter composed of M1 and M2 and the VLH is set by the inverter transistors M3 and M4, as shown in Figure 6b. Besides, the hysteresis exists only if VSP3,4 > VSP1,2.

Non-Inverting Schmitt Trigger by Pedroni
where = Similarly, the VHL can be found as: where = The hysteresis voltage could then be derived as: Figure 7 shows the low-power CMOS-type ST by Al-Sarawi [8]. It is composed of six transistors and its hysteresis is shown in Figure 7d. Depending on how the input signal changes, two I/O characteristics can be observed: If the input goes from low (0) to high (VDD) voltage level, the output state changes at VHL where the output goes from high (VDD) to low (0). If the input goes from high (VDD) to low (0), in this case, the output changes at VLH, where the output goes from low (0) to high (VDD). The VHL and VLH can be found when the input and the output voltages are equal at the operating points OP1 and OP2, as shown in Figure 7b,c. For the analysis, the switching voltage of the two inverters is assumed to be the same. Thus, the device sizes of M1 and M3, and M2 and M4 are the same.

VHL Voltage
When the input is low (0 V), Vout is high (VDD). Since Vout is a high impedance node and M1 is OFF, VCN drifts towards low (0) potential through the diode-connected M5 that works in the subthreshold region. While M3 works in the deep LIN region that VDS3 is close to 0. As a result, M6 turns fully ON which pulls the node voltage VP to VDD. Thus, when input is low (0) at steady state, transistors M2, M6, and M3 are ON, M5 is in subthreshold and, other transistors are fully OFF. Assuming VHL is larger than the threshold voltage of M1 at OP1, the VHL switching voltage could be determined by equating the SAT currents of M1 and M2, like a regular CMOS inverter with finite Vn that keeps M5 on the edge of SAT and OFF regions.
Vn could be found by using the equivalent circuit shown in Figure 7b. Here, it is assumed that the Vout node voltage is close to VDD, and M3 shorts Vcn to Vn effectively connecting the gate of M5 to its drain, which keeps it in the SAT region. Thus, using SAT currents of transistors M1 and M5, we can determine the Vn voltage as follows: where = Using (42) in (40) for Vin = VHL, we can find the VHL as follows.

VLH Voltage
When the input is high (VDD), Vout is low (0 V). As a result, M4 is ON shorting drain and gate of M6 that keeps M6 at the edge of SAT and OFF regions. Thus, when the input is high (VDD), transistors M1, M5, M4, and M6 are ON and the other transistors are OFF. At OP2, the VLH voltage can be determined by equating the SAT currents of M1 and M2. Here, Vp could be considered as finite and less than VDD, where M6 is on the edge of the SAT and OFF regions.
Vp could be found by using the equivalent circuit as shown in Figure 7c. Here, it is assumed that the Vout node voltage is approximately equal to 0 V, and M4 shorts Vcn to Vp effectively connecting the gate of M6 to its drain, which keeps it in SAT region. Thus, using SAT currents of transistors M2 and M6, we can determine the Vp voltage as follows: Using (46) in (45) for Vin = VLH, we can derive the VLH as follows: Al-Sarawi derived the VLH equation (Equation (4) in [8]) rather differently, which assumes VLH = VDD − VHL as well as Vthn0 = |Vthp0| = Vth. This assumption results in a simple but inaccurate VLH design equation. Additionally, his VLH equation has a typographical error that causes gross calculation error larger than 200% of simulated values. The corrected equation that gives reasonable hand calculation error (<20% of simulated values) is given below. We used this corrected equation instead of Equation (4) in [8] to compare our new equation.

Hysteresis Voltages
Formulation provided by Al-Sarawi (Equations (2)-(4) in [8]) assumes that the threshold voltages of the NMOS and PMOS devices are the same and do not cover all design and process variations. Thus, the equations given in (44) and (48) are more detailed and useful for hand calculations and design for the hysteresis voltage (∆VH = VHL − VLH).

Comparison of Simulation and Hand Calculations
Simulations of all ST circuits were performed using a well established, analog/mixed-signal, 0.35 μm CMOS, 3.3 V, CMOS process with BSIM3v3 Spice models. The process has device characteristics listed in Table 1. This process allows a fair comparison with literature that used long channel MOSFET models and high supply voltages. We used a minimum channel length (Lmin) of 0.35 μm and changed widths of transistors to cover a wide range of design spaces. In addition, Monte-Carlo, corner/parameter, or both, sweep simulations were run to find hysteresis voltages (VLH and VHL) under various conditions. Here, we only reported 3.3 V supply results at room temperature (T = 300 K), while similar trends were observed for other supply voltages.

Dokic ST Circuits
For the simulations of Dokic's circuits, transistor widths were changed between 2 Lmin and 20 Lmin with 2 Lmin steps such that channel widths of transistors M1, M2, and M4 were set equal to each other and M3 varied separately for P-type and N-type ST circuits. For CMOS type ST, widths of M1, M2, M6 and widths of M3, M4, M5 were set equal, respectively. Since minimum channel length was used for all transistors, setting α1n, α1p, α1, and α3 to 1.0 for all ST types, while α2n and α2p were varied between 0.383 and 3.83 for N-type and P-type circuits. For CMOS ST, α2 was changed between 0.54 and 5.4. The bulk of all NMOS transistors were connected to ground and the bulk of all PMOS transistors were connected to VDD.  (5) and (6) in [5]). Hand calculation accuracy compared to the simulation results are shown in Figure 9. Hand calculations result in lower than −13 and +5% errors for VHL and VLH, respectively. Wide hysteresis voltage can be achieved by choosing (W/L)1,2,4 = 20 (α1n = 1.0), and (W/L)3 = 2 (α2n = 3.83).   (15) and (17) for N-Type ST (or with Equations (5) and (6) in [5]) for VDD = 3.3 V and different device sizes (0.383 < α2n < 3.83).

P-Type ST by Dokic
For P-type Dokic ST, the channel length of M3 is set to 4 Lmin and the bulk of M4 is connected to the node V1 while the dimensions of other transistors and bulk connections are kept the same as Ntype Dokic ST. Figure 10 shows the simulation results of P-type Dokic ST for 3.3 V supply voltage. Hysteresis voltage (ΔVH) as large as 0.9 V could be achieved for α2p = 0.383. Moreover, hysteresis voltages close to 0.1 V are also possible with P-type Dokic ST for larger α2p values. The simulation results for the hysteresis voltages for different device sizes and supply voltages show that, typically, the VHL voltage is widely controlled by the design parameters. Figure 11 shows the hand calculation errors of the hysteresis voltages for the design parameter α2p using Equations (19) and (20) (or with Equations (8) and (12) in [5]). The error could be less than ±13%.   (19) and (20) for P-Type ST (or with Equations (8) and (12) in [5]) for different device sizes (0.383 < α2p < 3.83) and VDD = 3.3 V.

CMOS-Type ST by Dokic
For CMOS-type Dokic ST circuit simulations, the bulk of M6 is connected to the node V1. Figure  12 shows the simulation results for the 3.3 V supply voltage. Hysteresis voltage (ΔVH) as large as 1.2 V could be achieved for α2 = 0.54. The simulation results show that a smaller hysteresis voltage is not possible. Additionally, hand calculation equations (Equations (23) and (25)) and original Dokic equations (Equations (14) and (15) in [5]) do not provide good approximations that result in up to ±50% error for VHL and between +10% and −25% error for VLH, as shown in Figure 13.   (14) and (15) in [5]) for different device sizes (0.54 < α2 < 5.4) at VDD = 3.3 V.

CMOS-Type ST by Steyaert
Transistor widths were changed between 2 Lmin and 10 Lmin with Lmin steps for transistors M1, M3, and M5, and between 7 Lmin and 14 Lmin with 4 Lmin steps for transistors M2 and M4 during the simulation. The channel lengths of NMOS and PMOS transistors were set to 10 Lmin and Lmin, respectively. As a result, a wide design space was covered for simulations and calculations. A new design parameter, the transconductance factor ratio (κ) which is defined as the ratio between β2 (M2) and β1 + β5 (M1 and M5 combination) represents the design space. κ was set between 1.0 and 12. This results in the VHL voltage being between 0.55 and 2.04 V, the VLH between 1.7 and 2.30 V, and the hysteresis voltage between 0.24 and 1.15 V for 3.3 V supply voltage, as shown in Figure 14a.
Derived VLH equation in this work, Equation (28), and the original Steyaert equation ((1) in [6]) are the same, resulting in a maximum −4% hand calculation error. Steyaert's VHL equation ((2) in [6]), on the other hand, results in gross hand calculation errors up to −120% for smaller κ values, while Equation (30) presented in this work results in less than −25% as shown in Figure 14b. As a result, overall hand calculation error for the hysteresis voltage ΔVH by Equation (34) is lower than that of the original Steyaert equation, (Equations (1) and (2) in [6]), as shown in Figure 14c.  (1) in [6], and (c) hand calculation error of ΔVH using Equation (34) and Equations (1) and (2) in [6].

Non-Inverting ST by Pedroni
The hysteresis voltages of Pedroni ST can be set by modifying the sizes of NMOS (M1, M3, M5) or PMOS (M2, M4, M6) transistors. For simulation, NMOS transistor widths were changed between 2 Lmin and 10 Lmin with 2 Lmin steps. The multiplication factor (M) of M1 is set to Mx and M3 and M5 is to unity, respectively. Similar widths and steps used for the PMOS transistors while setting the multiplication factor of M4 to be Mx, and keeping the multiplication factor of M2 and M6 to be unity. The channel length of NMOS and PMOS transistors were set to Lmin or 0.35 μm. Multiplication factor of transistor M1, M4, the Mx, varied from 2 to 6 while other Ms were kept constant at unity so that a wide range of VHL and VLH voltages were achieved.
Design parameter Mx, α1, and α2 can be used for setting hysteresis voltages (VHL, VLH, and ΔVH) as shown in Figure 15. Hysteresis voltage as large as 1 V can be achieved by increasing all design parameters, however, this will result in a large silicon footprint. Equations (35) and (37) predict the hysteresis voltages, VHL, and VLH with +14% to −8% calculation errors as shown in Figure 16.

CMOS-Type ST by Al-Sarawi
The sensitivity of the VHL to α1 parameter, which can be derived from Equation (44), is much higher than the α2 and α3 parameters. Thus, for simulation and evaluation of the design equation accuracies, α1 parameter varied from 0.15 to 1.3 while α2 and α3 were set to 1.41 and 2, respectively. We proposed new hysteresis design equations for the Al-Sarawi ST. Figure 17 shows the simulated and calculated values by using Al-Sarawi's original design equation and the proposed design Equation (44) of the hysteresis voltages VHL, VLH, and ΔVH versus α1 parameter. The simulation results show that the ΔVH reaches 0.98 V (Figure 17c), which is larger than Al-Sarawi's original design equation. However, it saturates around these values even if α1 parameter is increased. Figure 18 illustrates the hand calculation errors of proposed design equations in Section 2.4 as well as Al-Sarawi's original design equations related to the simulated values of VHL, VLH, and ΔVH. It can be noticed from Figure 18b that VLH hand calculation error of the proposed design Equation (48) is less than 2% while it could be as large as 17% for Al-Sarawi's original design equation. Additionally, hand calculation errors of VHL and ΔVH by the proposed design equations are always inversely proportional to VHL and ΔVH, respectively, and are lower than the calculation errors of Al-Sarawi's original design equations.  Table 2 summarizes a comparison between Dokic [5], Steyaert [6], Pedroni [7], and Al-Sarawi [8] ST circuits in terms of total area, simulated power consumption, transition delays, and maximum hysteresis voltage based on the variation of device dimensions. There are tradeoffs among these parameters that the larger ΔVH design may have the higher-power consumption or the larger footprint or the lower speed. By design, it is desirable to have larger ΔVH, and smaller delay, area, and power consumption. Thus, we propose a figure of merit (FoM) based on these parameters. FoM for ST circuits can be calculated using the following equation:

Comparison of All Circuits
This equation is scaled by a multiplying factor of 10,000 for better number representation. Delay was measured at 50% of the supply voltage level when a 100 fF loading is added at the output of each ST design. The sum of rising (trise) and falling times (tfall) was calculated as the delay.
From Table 2, if the large hysteresis voltage is the main requirement, the Steyaert ST circuit is the best, yet it has the lowest FoM due to large power consumption and area. Overall, Al-Sarawi's ST circuit offers the best FoM. However, it is slower than Pedroni's ST, which is the second-best choice among the investigated topologies.

Conclusions
In this paper, detailed reviews of Dokic [5], Steyaert [6], Pedroni [7], and Al-Sarawi [8] SISO ST circuits are presented. The paper starts with the detailed derivation of the hysteresis voltages (VHL, VLH, and ΔVH) for each topology. Then, we propose some new design equations which result in a more intuitive, and accurate design through hand calculations. Simulations were run to verify that the derived and the original design equations are accurate. The simulations were carried out in a well-established 0.35 μm/3.3 V analog/mixed-signal CMOS process. For each ST circuit, hysteresis voltages (VHL, VLH, and ΔVH) were calculated with respect to different device sizes, which cover wide design space at a process supply voltage of 3.3 V. The hand calculation results derived from both the original and the new design equations were presented for each ST circuit and are compared with simulation results. The comparisons show that the new design equations are better than the original ones in terms of accuracy and intuition. Finally, the proposed FoM in Equation (51) can work as a criterion to compare different ST circuits. It is found that Al-Sarawi's ST circuit offers the best FoM of the investigated topologies.