Electronic Tuning Square-Wave Generators with Improved Linearity Using Operational Transresistance Ampliﬁer

: Two new electronic tuning current-mode square-wave generators are introduced in the ensuing paper. In the ﬁrst proposed square-wave generator circuit, one Operational Trans-resistance Ampliﬁer (OTRA) and two passive components are involved, along with two NMOS depletion mode transistors. This circuit generates a square-wave with almost equal and ﬁxed duty cycles. The second proposed circuit is able to control both on-duty and o ﬀ -duty cycles independently with the help of two passive components, two NMOS depletion mode transistors, and two diodes connected to the circuit. The frequency of the proposed circuits can be adjusted with the passive components connected to the circuit. Moreover, electronic tuning can also be achieved with the proposed circuits. The measured results that are included in the paper show the linear variation of a time period as compared with existing OTRA based square waveform generator. The performance of the proposed circuits is examined while using SPICE models. These circuits are built on a laboratory breadboard using commercially available Current Feedback Operational Ampliﬁer (AD844 AN) and passive components are connected externally and tested for square waveform generation. The obtained results demonstrate good agreement with the theoretical values.


Introduction
The square-wave generator is widely operated in many electronic fields, such as digital, instrumentation, and communication systems. Conventionally, Operational Amplifier (Op-Amp) is used to generate square waveform along with some passive components. These voltage-mode (Op-Amp) circuits pose some drawbacks, such as complex internal circuitry, lower slew rate, constant gain bandwidth product, and more passive components are, however, required to generate the waveforms [1].
Recently, an alternative approach, called current-mode technology, has attracted considerable attention for analog circuit designers, due to its advantage over voltage-mode devices, like high performance, high linearity, wide dynamic range, low power consumption, simple circuitry, and versatility over voltage-mode devices [2]. Several waveform generators have been proposed using current-mode devices; these waveform generator circuits offer several advantages over voltage-mode waveform generators. The circuits that are given in [3][4][5][6][7][8][9][10][11][12][13][14] are designed with Voltage Differencing Buffered/Inverted Amplifier (VDIBA), Multiple Output Current Through Transconductance Amplifiers (MO-CTTA), Controlled Gain Current and Differential Voltage Amplifier 2 of 16 (CG-CDVA), Differential Voltage Current Conveyors (DVCC), and Operational Transconductance Amplifier (OTA). These square-wave generators require external voltage or current biasing to produce the square waveform. Current Feedback Operational Amplifier (CFOA) based waveform generator was introduced in [15]. However, this waveform generator requires more passive components and two active components. A single CFOA based waveform generator was proposed in [16]. The configuration of the circuit is simple with a few passive components. However, the oscillation frequencies are limited to few kHz. Second generation Current Conveyor (CCII+) based waveform generators were proposed in the literature [17][18][19][20][21]. These waveform generators provide some advantages, like higher slew rate and wider bandwidth. However, some of these waveform generators require more than one active device and more passive components. Square-wave generators with single CCII+ were proposed in [20]. These waveform generators have the advantage of less power consumption. However, the oscillation frequencies of these circuits are limited to only few kHz. The square-wave generator using three operational transconductance amplifier (OTA) and three passive components was proposed in [22]. The advantage of this waveform generator would be that it can control the amplitude and frequency independently by changing the resistance or changing the biasing current. However, this waveform generator consumes more power and the use of three OTAs requires more chip area. Table 1 shows the comparison of active devices. Recently, an active current-mode device, called an operational transresistance amplifier (OTRA), has come to limelight with the introduction of several high performances CMOS OTRA realizations. Several waveform generators using an operational transresistance amplifier (OTRA) were reported earlier in the literature [23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42]. Square-waveform generator using single OTRA and a few passive components was proposed in [28]. Figure 1 shows this proposed circuit. The architecture of the circuit is simpler than the voltage-mode waveform generators. This circuit generates oscillations up to a few MHz. However, this circuit exhibits non-linear variation of time period with respect to the resistance R 2 . Transconductance Amplifiers (MO-CTTA), Controlled Gain Current and Differential Voltage Amplifier (CG-CDVA), Differential Voltage Current Conveyors (DVCC), and Operational Transconductance Amplifier (OTA). These square-wave generators require external voltage or current biasing to produce the square waveform. Current Feedback Operational Amplifier (CFOA) based waveform generator was introduced in [15]. However, this waveform generator requires more passive components and two active components. A single CFOA based waveform generator was proposed in [16]. The configuration of the circuit is simple with a few passive components. However, the oscillation frequencies are limited to few kHz. Second generation Current Conveyor (CCII+) based waveform generators were proposed in the literature [17][18][19][20][21]. These waveform generators provide some advantages, like higher slew rate and wider bandwidth. However, some of these waveform generators require more than one active device and more passive components. Square-wave generators with single CCII+ were proposed in [20]. These waveform generators have the advantage of less power consumption. However, the oscillation frequencies of these circuits are limited to only few kHz. The square-wave generator using three operational transconductance amplifier (OTA) and three passive components was proposed in [22]. The advantage of this waveform generator would be that it can control the amplitude and frequency independently by changing the resistance or changing the biasing current. However, this waveform generator consumes more power and the use of three OTAs requires more chip area. Table 1 shows the comparison of active devices. Recently, an active current-mode device, called an operational transresistance amplifier (OTRA), has come to limelight with the introduction of several high performances CMOS OTRA realizations. Several waveform generators using an operational transresistance amplifier (OTRA) were reported earlier in the literature [23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42]. Square-waveform generator using single OTRA and a few passive components was proposed in [28]. Figure 1 shows this proposed circuit. The architecture of the circuit is simpler than the voltage-mode waveform generators. This circuit generates oscillations up to a few MHz. However, this circuit exhibits non-linear variation of time period with respect to the resistance R2. Figure 1. Conventional Operational Trans-resistance Amplifier (OTRA) based square-wave generator [28].
In this paper, two new square-wave generators based on single OTRA are presented. The proposed circuits are able to overcome the non-linear variation of the time period with respect to the passive components. The remaining sections of the paper are designed, as follows. In Section 2, the In this paper, two new square-wave generators based on single OTRA are presented. The proposed circuits are able to overcome the non-linear variation of the time period with respect to the passive components. The remaining sections of the paper are designed, as follows. In Section 2, the function of the OTRA is introduced first and then the operation of the proposed configurations is described along with the non-idealities. Section 3 presents simulated and experimental results. Finally, the conclusion is drawn in Section 4.

Circuit Description and Operation
The OTRA is a three terminal current-mode analog device with two low-impedance input terminals and one low-impedance output terminal [27,28]. The input terminals of the OTRA are virtually grounded, this leads to the circuits that are insensitive to the parasitic capacitances. Figure 2 shows the circuit symbol of the OTRA. The input and output terminal relations of an OTRA can be characterized by the following matrix. For ideal operation, the transresistance gain R m approaches infinity, forcing the input currents to be equal.
J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 3 of 16 function of the OTRA is introduced first and then the operation of the proposed configurations is described along with the non-idealities. Section 3 presents simulated and experimental results. Finally, the conclusion is drawn in Section 4.

Circuit Description and Operation
The OTRA is a three terminal current-mode analog device with two low-impedance input terminals and one low-impedance output terminal [27,28]. The input terminals of the OTRA are virtually grounded, this leads to the circuits that are insensitive to the parasitic capacitances. Figure  2 shows the circuit symbol of the OTRA. The input and output terminal relations of an OTRA can be characterized by the following matrix. For ideal operation, the transresistance gain Rm approaches infinity, forcing the input currents to be equal.  Figure 3 shows the first proposed square-wave generator. This square-wave generator consists of one active element (OTRA), one resistor R1, one capacitor C, and two depletion mode NMOS transistors. The two NMOS transistors M1 and M2 are operated in the triode region and they act as a linear resistor.  2.1. Proposed Circuit-1 Figure 3 shows the first proposed square-wave generator. This square-wave generator consists of one active element (OTRA), one resistor R 1 , one capacitor C, and two depletion mode NMOS transistors. The two NMOS transistors M 1 and M 2 are operated in the triode region and they act as a linear resistor. function of the OTRA is introduced first and then the operation of the proposed configurations is described along with the non-idealities. Section 3 presents simulated and experimental results. Finally, the conclusion is drawn in Section 4.

Circuit Description and Operation
The OTRA is a three terminal current-mode analog device with two low-impedance input terminals and one low-impedance output terminal [27,28]. The input terminals of the OTRA are virtually grounded, this leads to the circuits that are insensitive to the parasitic capacitances. Figure  2 shows the circuit symbol of the OTRA. The input and output terminal relations of an OTRA can be characterized by the following matrix. For ideal operation, the transresistance gain Rm approaches infinity, forcing the input currents to be equal.

V+ = V− = 0 and Vo = Rm(I+ − I−)
(2) Figure 2. OTRA symbol. Figure 3 shows the first proposed square-wave generator. This square-wave generator consists of one active element (OTRA), one resistor R1, one capacitor C, and two depletion mode NMOS transistors. The two NMOS transistors M1 and M2 are operated in the triode region and they act as a linear resistor.  Equation (3) depicts the equivalent amount of resistance R 2 realized from the parallel combination of NMOS transistors as shown in Figure 4.   This circuit generates a square-wave with almost equal and fixed on-duty and off-duty cycles, i.e., 50% duty cycles. Figure 5 shows the corresponding output waveform of the first proposed circuit. From Figure 5, it could be construed that the output square-wave (V o ) has two saturation levels V + sat and V − sat . Let us assume that V o is at any one of these two saturation levels. If V o changes its state from V − sat to V + sat , it implies that the current at the non-inverting terminal I + becomes more than the current at the inverting terminal I − of the OTRA. At this moment, the voltage V C of the capacitor C begins to increase from the lower threshold value V TL to the final value V + sat . From Figure 3, the current I o at the output terminal and the current I − at the inverting input terminal of the OTRA can be written, as

Proposed Circuit-1
This circuit generates a square-wave with almost equal and fixed on-duty and off-duty cycles, i.e., 50% duty cycles. Figure 5 shows the corresponding output waveform of the first proposed circuit. From Figure 5, it could be construed that the output square-wave (Vo) has two saturation levels  sat V and  sat V . Let us assume that Vo is at any one of these two saturation levels. If Vo changes its state from  sat V to  sat V , it implies that the current at the non-inverting terminal I+ becomes more than the current at the inverting terminal I− of the OTRA. At this moment, the voltage VC of the capacitor C begins to increase from the lower threshold value VTL to the final value  sat V . From Figure  3, the current Io at the output terminal and the current I− at the inverting input terminal of the OTRA can be written, as Subsequently, the non-inverting input terminal current I+ can be expressed as From the terminal relations presented in Equation (1), Vo changes its state when the non-inverting terminal current is equal to the inverting terminal current I+ = I−. The capacitor voltage can be derived from Equations (5) and (6) by putting I+ = I−.
The capacitor voltage changes between VTH and VTL. Subsequently, VTH and VTL can be derived from Equation (7) by substituting threshold and saturation values The time evolution equation for the capacitor voltage VC, when it starts to increase from VTL towards its final value  sat V can be expressed as Subsequently, the non-inverting input terminal current I + can be expressed as From the terminal relations presented in Equation (1), V o changes its state when the non-inverting terminal current is equal to the inverting terminal current I + = I − . The capacitor voltage can be derived from Equations (5) and (6) by putting I + = I − .
The capacitor voltage changes between V TH and V TL . Subsequently, V TH and V TL can be derived from Equation (7) by substituting threshold and saturation values The time evolution equation for the capacitor voltage V C , when it starts to increase from V TL towards its final value V + sat can be expressed as Time period T 1 can be derived by making V C (t) = V TH By substituting V TH and V TL values from Equations (8) and (9) From the output waveform, it can be written as The above Equation (15) is meant for on-duty cycle (T ON ). At the end of the on-duty cycle, the capacitor voltage V C is charged up to the upper threshold voltage V TH , instead of V + sat . At this point of time, the current at the non-inverting terminal I + becomes less than the current at the inverting terminal I − of the OTRA. Subsequently, the output changes its state from the upper saturation level V + sat to the lower saturation level V − sat and the capacitor starts discharging. When the voltage across capacitor C starts to decrease from V TH , it can be expressed, as Time period T 2 can be derived by setting V C (t) = V TL By substituting V TH and V TL values in the above Equation (16) and following the same demonstration as the on-duty cycle T 1 , we obtain: The above Equation (18) is for off-duty cycle (T OFF ). The final time period (T) of the waveform is the sum of the T 1 and T 2 cycles.
For fixed duty cycles, the R 1 , R 2 , and C values will be obtained from the above Equation (19) for a required time period T. The required value of the resistor R 2 is calculated from (3) by adjusting the voltage V X .

Proposed Circuit-2
The second proposed circuit that is shown in Figure 6 is designed to vary both the duty cycles independently with the help of resistors R 11 and R 12 . The voltage drops across these resistors used to control the operation of the diodes D 1 and D 2 . The capacitor C starts charging towards V + sat when non-inverting terminal current is more than the inverting terminal current. This makes diode D 1 becomes forward bias and D 2 reverse bias. The diode D 1 and resistor R 11 controls the amount of current at the inverting input terminal. Consequently, the on-duty cycle is more as compared to the off-duty cycle. Similarly, the diode D 2 becomes forward bias and D 1 reverse bias and capacitor starts discharging towards V + sat . The resistor R 12 and diode D 2 controls the inverting input terminal current. Due to this, the off-duty cycle is more when compared to the on-duty cycle. When considering ideal diodes (zero voltage drop), capacitor threshold voltages can be described by the following equations: Time period T1 (TON) can be obtained from Equations (20) and (21), while following the same demonstration reported in Section 2.1 for the proposed circuit-1 The total time period (T) for the proposed square-wave generator in Figure 6 can be expressed as T = TON + TOFF

Non-Ideal Analysis
An equivalent circuit model of the OTRA built with two current feedback amplifiers (CFAs) is shown in Figure 7a to consider the non-ideal and parasitic effects on the proposed circuits. When considering ideal diodes (zero voltage drop), capacitor threshold voltages can be described by the following equations: Time period T 1 (T ON ) can be obtained from Equations (20) and (21), while following the same demonstration reported in Section 2.1 for the proposed circuit-1 Similarly for T OFF T OFF = R 2 C ln(1 + (R 12 /R 2 )) The total time period (T) for the proposed square-wave generator in Figure 6 can be expressed as

Non-Ideal Analysis
An equivalent circuit model of the OTRA built with two current feedback amplifiers (CFAs) is shown in Figure 7a to consider the non-ideal and parasitic effects on the proposed circuits.  A practical CFA (AD844AN IC) can be modeled as a positive second-generation current conveyor (CCII+) cascading a voltage buffer with finite parasitic resistances and non-zero current tracking errors. Figure 7a reveals a more detailed circuit model of the OTRA that is given in Figure  7b. Where RX and RZ are the parasitic resistances and α represents the current tracking error factor from the terminal Tz with respect to the inverting terminal. The standard values of RX, RZ, and α are given in AD844AN datasheet are α = 0.98, RX = 50 Ω, and RZ = 3 MΩ. Figure 7a indicates the resultant expressions of the related currents. The voltage tracking error effect between the CCII+ input terminals are skipped (eliminated) in the circuit model, because of the non-inverting terminal for each CCII+ being connected to ground.

Non-Ideal Analysis of Proposed Circuit-1
For the proposed circuits, the non-ideal analysis gives the following equations Substituting these higher and lower threshold voltages into Equations (11) and (17), the non-ideal time period of the proposed circuit in Figure 3 can be expressed, as A practical CFA (AD844AN IC) can be modeled as a positive second-generation current conveyor (CCII+) cascading a voltage buffer with finite parasitic resistances and non-zero current tracking errors. Figure 7a reveals a more detailed circuit model of the OTRA that is given in Figure 7b. Where R X and R Z are the parasitic resistances and α represents the current tracking error factor from the terminal Tz with respect to the inverting terminal. The standard values of R X , R Z , and α are given in AD844AN datasheet are α = 0.98, R X = 50 Ω, and R Z = 3 MΩ. Figure 7a indicates the resultant expressions of the related currents. The voltage tracking error effect between the CCII+ input terminals are skipped (eliminated) in the circuit model, because of the non-inverting terminal for each CCII+ being connected to ground.

Non-Ideal Analysis of Proposed Circuit-1
For the proposed circuits, the non-ideal analysis gives the following equations Substituting these higher and lower threshold voltages into Equations (11) and (17), the non-ideal time period of the proposed circuit in Figure 3 can be expressed, as

Non-Ideal Analysis of Proposed Circuit-2
The non-ideal equation for the second proposed circuit in Figure 6 is given in Equation (32) V TH = (αR 12 /(αR 12 It can be easily verified that Equations (29) and (32) reduces to Equations (19) and (26), as expected, for ideal OTRA when α ≈ 1 and R X ≈ 0.

Simulation and Experimental Results
The proposed circuits were simulated using SPICE CMOS model parameters with a supply voltage of ±1.8 V. Figure 8 provides the CMOS realization of the OTRA. Table 2 depicts the aspect ratios of the transistors, biasing voltages, and biasing currents. Figure 9 provides the simulated output results of the proposed circuits. The non-ideal equation for the second proposed circuit in Figure 6 is given in Equation (32) (  (   2  2  11  11    (31) )) )) /( ( It can be easily verified that Equations (29) and (32) reduces to Equations (19) and (26), as expected, for ideal OTRA when α ≈ 1 and RX≈ 0.

Simulation and Experimental Results
The proposed circuits were simulated using SPICE CMOS model parameters with a supply voltage of ±1.8 V. Figure 8 provides the CMOS realization of the OTRA. Table 2 depicts the aspect ratios of the transistors, biasing voltages, and biasing currents. Figure 9 provides the simulated output results of the proposed circuits.
For generating the square-wave of the first proposed circuit in Figure 3, the required time period is chosen first. Subsequently, the ratio of R1/R2 is taken care of and the value of capacitor C is arbitrarily determined from Equation (19). The voltage VX is adjusted to realize the desired value of resistance R2 from (3). However, with this circuit the on-duty and off-duty cycles are fixed. The first proposed circuit was designed with the following passive components R1 = 15 kΩ, R2 = 1.5 kΩ (W = 5µm, L = 180 nm, VX= 80 mV), and C = 1 nF to generate the square waveform. Figure 9a shows the simulated output waveform of the proposed circuit in Figure 3 with a time period of 7.56 µs, which is close to the theoretical time period of 7.19 µs.  Table 2. Aspect ratios of the circuit shown in Figure 8.   Table 2. Aspect ratios of the circuit shown in Figure 8.  17 3.3 180 V g1 = V g2 = 0.8 V and I 0 = 40 µA the off-duty cycle. These values will be (R12>R11) reversed to set the off-duty cycle more than the on-duty cycle. The passive components R2 =1.5 kΩ (W = 5µm, L = 180 nm, VX= 80 mV), R11= 1.5 kΩ, R12= 5 kΩ, and C=0.1µF were used to design the second proposed circuit in Figure 6. Figure 9b, and 9c provide the corresponding simulated output waveforms for the second proposed circuit. From Figure 9b, and 9c, the simulated time period is 0.36 ms, which is close to the theoretical time period of 0.32 ms.  AD844AN is adopted to construct the proposed circuits on a laboratory breadboard in order to verify the theoretical study. The commercial IC AD844AN with current feedback architecture (configuration) is used to implement the OTRA, as shown in Figure 7a [27,28]. Therefore, the behavior of the OTRA is obtained with the schematic shown in Figure 7a. For the proposed circuit in Figure 3, the required time period is chosen first. Subsequently, suitable values of passive components (R1, R2, and C) are derived from Equation (19). In all measurements, the passive component R2 value is the same as the resistance R2 value calculated from Equation (3). For higher For generating the square-wave of the first proposed circuit in Figure 3, the required time period is chosen first. Subsequently, the ratio of R 1 /R 2 is taken care of and the value of capacitor C is arbitrarily determined from Equation (19). The voltage V X is adjusted to realize the desired value of resistance R 2 from (3). However, with this circuit the on-duty and off-duty cycles are fixed. The first proposed circuit was designed with the following passive components R 1 = 15 kΩ, R 2 = 1.5 kΩ (W = 5µm, L = 180 nm, V X = 80 mV), and C = 1 nF to generate the square waveform. Figure 9a shows the simulated output waveform of the proposed circuit in Figure 3 with a time period of 7.56 µs, which is close to the theoretical time period of 7.19 µs.
For the second proposed circuit in Figure 6, the values of resistors R 11 = R 12 , equivalent resistance R 2 and capacitor C, are derived from the above process as stated in fixed duty cycles. Then the resistors R 11 and R 12 are tuned independently in order to set the required on-duty and off-duty cycles. If resistor R 11 is chosen to be greater than the resistor R 12 , then the on-duty cycle is more than the off-duty cycle. These values will be (R 12 > R 11 ) reversed to set the off-duty cycle more than the on-duty cycle. The passive components R 2 =1.5 kΩ (W = 5µm, L = 180 nm, V X = 80 mV), R 11 = 1.5 kΩ, R 12 = 5 kΩ, and C = 0.1µF were used to design the second proposed circuit in Figure 6. Figure 9b,c provide the corresponding simulated output waveforms for the second proposed circuit. From Figure 9b,c, the simulated time period is 0.36 ms, which is close to the theoretical time period of 0.32 ms.
AD844AN is adopted to construct the proposed circuits on a laboratory breadboard in order to verify the theoretical study. The commercial IC AD844AN with current feedback architecture (configuration) is used to implement the OTRA, as shown in Figure 7a [27,28]. Therefore, the behavior of the OTRA is obtained with the schematic shown in Figure 7a. For the proposed circuit in Figure 3, the required time period is chosen first. Subsequently, suitable values of passive components (R 1 , R 2 , and C) are derived from Equation (19). In all measurements, the passive component R 2 value is the same as the resistance R 2 value calculated from Equation (3). For higher sensitivity of the time period with respect to the resistor, the resistor R 2 is chosen to be less than 2 kΩ. The experimental output waveform of the proposed circuit-1 is given in Figure 10   AD844AN is adopted to construct the proposed circuits on a laboratory breadboard in order to verify the theoretical study. The commercial IC AD844AN with current feedback architecture (configuration) is used to implement the OTRA, as shown in Figure 7a [27,28]. Therefore, the behavior of the OTRA is obtained with the schematic shown in Figure 7a. For the proposed circuit in Figure 3, the required time period is chosen first. Subsequently, suitable values of passive components (R1, R2, and C) are derived from Equation (19). In all measurements, the passive component R2 value is the same as the resistance R2 value calculated from Equation (3). For higher sensitivity of the time period with respect to the resistor, the resistor R2 is chosen to be less than 2 kΩ. The experimental output waveform of the proposed circuit-1 is given in Figure 10 with a time period of 7 µs. Similarly, in the case of the second proposed circuit, the suitable passive component values will be obtained from Equation (26) to a chosen time period. If the required time period is 0.32 ms with 60% on-duty and 40% off-duty cycles then the capacitor C is slightly increased to set the required time period. The resistor R11 and R12 values will be reversed to set the 40% on-duty and 60% off-duty cycles. The output waveforms for the second proposed circuit are given in Figure 11a,b with a time period of 0.31 ms. Similarly, in the case of the second proposed circuit, the suitable passive component values will be obtained from Equation (26) to a chosen time period. If the required time period is 0.32 ms with 60% on-duty and 40% off-duty cycles then the capacitor C is slightly increased to set the required time period. The resistor R 11 and R 12 values will be reversed to set the 40% on-duty and 60% off-duty cycles. The output waveforms for the second proposed circuit are given in Figure 11a,b with a time period of 0.31 ms.
(b) Output waveform of with variable off-duty cycle (TON<TOFF). Scale: X-axis 0.2 ms/div and Y-axis 1 V/div. A linear like variation of time period was exhibited by the circuit and it is presented in the form of plot in Figure 12. Similarly, for the capacitor C, the selected parameter values are resistors R1 = 15 kΩ and R2 = 1.5 kΩ. The capacitor C was varied from 0.1 nF to 100 nF. Figure 13 plots the practical and theoretical time period variation against the capacitor C. Likewise, for the resistor R2, the circuit was built with resistor R1= 15 kΩ, capacitor C = 1 nF and R2 was varied from 200 Ω to 3 kΩ.    From Figures 12-14, the variation of the time period with respect to the passive components is linear. Figure 1 shows the OTRA based square-wave generator proposed in [28]. For generating the square-wave in the circuit shown in Figure 1, it is necessary to maintain the resistor R2 value less than the resistor R1 and as it will not generate the waveform when R1<R2. The proposed circuits in    From Figures 12-14, the variation of the time period with respect to the passive components is linear. Figure 1 shows the OTRA based square-wave generator proposed in [28]. For generating the square-wave in the circuit shown in Figure 1, it is necessary to maintain the resistor R2 value less than the resistor R1 and as it will not generate the waveform when R1<R2. The proposed circuits in  Figure 1. Figure 15 shows the comparison between conventional OTRA square-wave generator circuit [28] and proposed square-wave generator circuit in Figure 3. For the plot in Figure 15 the parameters values are R1 = 15 kΩ and C = 1 nF, and R2 was varied from 200 Ω to 18 kΩ. From Figure 15, it can be construed that the proposed circuit exhibits more linear curve than the conventional circuit. The proposed circuits can generate the oscillations up to 1.2 MHz. A detailed tally of the proposed circuit with the other square-wave generators in the literature are presented in Table 3 in order to highlight the advantage of the proposed circuit in Figure 3. Form this comparison table, the proposed circuit outperforms with most of the listed square wave generators. The square waveform generators reported in [12] and [15] generates a high frequency of oscillations when compared with the proposed circuits. With two active components along with passive component consume a high amount power and occupy large silicon area. The square wave generator that is given in [44] requires two passive components (one resistor and one capacitor) and one passive component to produce high frequency oscillations. However, the active device Dual-X Current Conveyor Transconductance Amplifier (DXCCTA) is very bulky with eight input terminals and one output terminal. The total number of transistors to construct the DXCCTA is also large. A greater number of transistors and input terminals increase the silicon area and power consumption.  Table 3. Comparison of the proposed circuit in Figure 3 with the conventional circuits in the literature.  Figures 12-14 denote the time period variation against the passive components R 1 , R 2 , and C. For the tunability of resistor R 1, the selected passive component values are R 2 = 12 kΩ and C = 1 nF and R 1 was varied from 800 Ω to 10 kΩ.

References
A linear like variation of time period was exhibited by the circuit and it is presented in the form of plot in Figure 12. Similarly, for the capacitor C, the selected parameter values are resistors R 1 = 15 kΩ and R 2 = 1.5 kΩ. The capacitor C was varied from 0.1 nF to 100 nF. Figure 13 plots the practical and theoretical time period variation against the capacitor C. Likewise, for the resistor R 2 , the circuit was built with resistor R 1 = 15 kΩ, capacitor C = 1 nF and R 2 was varied from 200 Ω to 3 kΩ.
From Figures 12-14, the variation of the time period with respect to the passive components is linear. Figure 1 shows the OTRA based square-wave generator proposed in [28]. For generating the square-wave in the circuit shown in Figure 1, it is necessary to maintain the resistor R 2 value less than the resistor R 1 and as it will not generate the waveform when R 1 < R 2 . The proposed circuits in Figures 3 and 6 will generate the waveform independent of the resistor values and exhibit more linear curve than the conventional circuit in Figure 1. Figure 15 shows the comparison between conventional OTRA square-wave generator circuit [28] and proposed square-wave generator circuit in Figure 3. For the plot in Figure 15 the parameters values are R 1 = 15 kΩ and C = 1 nF, and R 2 was varied from 200 Ω to 18 kΩ. From Figure 15, it can be construed that the proposed circuit exhibits more linear curve than the conventional circuit. The proposed circuits can generate the oscillations up to 1.2 MHz. A detailed tally of the proposed circuit with the other square-wave generators in the literature are presented in Table 3 in order to highlight the advantage of the proposed circuit in Figure 3. Form this comparison table, the proposed circuit outperforms with most of the listed square wave generators. The square waveform generators reported in [12,15] generates a high frequency of oscillations when compared with the proposed circuits. With two active components along with passive component consume a high amount power and occupy large silicon area. The square wave generator that is given in [44] requires two passive components (one resistor and one capacitor) and one passive component to produce high frequency oscillations. However, the active device Dual-X Current Conveyor Transconductance Amplifier (DXCCTA) is very bulky with eight input terminals and one output terminal. The total number of transistors to construct the DXCCTA is also large. A greater number of transistors and input terminals increase the silicon area and power consumption. Table 3. Comparison of the proposed circuit in Figure 3 with the conventional circuits in the literature.

References
No. of Active Components

Conclusions
In this paper, two new square-wave generators are proposed. These circuits use only one OTRA and a few passive components, the proposed circuits are simpler than the voltage-mode (op-amp based) waveform generators. The attentive features of these topologies are that they are realized while using commercially available ICs AD 844 AN. The proposed circuits exhibit linear variation of the time period with respect to the passive component. Additionally, the time period of the proposed circuits can be electronically tuned by adjusting the voltage (V X ). The results exhibited by such topologies congruent with the simulated as well as the theoretical values. The proposed circuits can generate oscillations up to 1.2 MHz (experimental). These circuits can be expected to find wider applications in many applied electronics, communications, instrumentation, and signal processing applications.