High-Efﬁciency Switched-Capacitor DC-DC Converter with Three Decades of Load Current Range Using Adaptively-Biased PFM

: A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efﬁciency of 80% is implemented in a 0.18 µ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efﬁciency > 70% for load currents in the range of 12 µ A to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to < 72 mV over the entire load current range.


Introduction
Recent developments in personal wearable devices, such as smart watches, offer more intelligent capabilities in an effort to satisfy consumer demand. High-performance CPUs are integrated into wearable devices to handle tasks such as collecting measurements from sensors and transmitting data over wireless networks. As wearable devices develop, the concerns of battery size and runtime become paramount for enhancing the user's experience. Though continuous shrinking of the transistor has helped to reduce power loss to a certain extent, the market always demands improved design to further extend battery runtime.
A system-on-chip (SoC) uses power, thermal, and performance (PTP) detectors that are distributed within the CPU in order to monitor operating conditions. The use of PTP technology for an SoC in [1] demonstrated a 23% increase in clock speed or up to 41% in power savings. Given PTP input data, SoCs in generic portable devices use several power-saving techniques, such as (a) dynamic power management (DPM), where system blocks are turned off during standby state, and (b) dynamic voltage and frequency scaling (DVFS), where the supply voltage and operating frequency are adjusted based on the workload [2].
Switched-capacitor (SC) DC-DC converters are gaining attention for the advantage of monolithic integration of the converter and no off-chip inductors for low-power applications [3]. Pulse frequency modulation (PFM) is a popular control technique used in SC converters to maintain high efficiency over a wide load current range [4].
Switched-capacitor (SC) DC-DC converters have the advantage of monolithic integration of the converter with no off-chip inductors. SC converters achieve efficiency greater than an LDOwhen the output voltage is not close to the input voltage [5]. The peak theoretical efficiency of a step-down SC converter can be described using the relation [6]: η PK ≈ P OUT P OUT + P BP + P SW + P DR + P LK + P CTRL (1) where P OUT is the output power, P BP is power loss from the parasitic bottom-plate (BP) capacitance of the charge transfer capacitor, P DR is the gate driver loss, P SW is the switch loss, P LK is the power loss due to subthreshold leakage current through the power switches in the off-state, and P CTRL is the power loss in the controller. P BP is technology dependent and is the most important parameter limiting peak efficiency. Charge recycling techniques proposed in [7,8] reduce P BP . P CTRL is a summation of the controller's dynamic switching power loss and static power loss, as in: At low load conditions, P CTRL,DY scales with frequency. However, static power loss in the controller, P CTRL,ST , is largely unaddressed in the literature. η PK is approximately constant as a function of switching frequency if P CTRL,ST is scaled along with P CTRL,DY , until P LK is comparable with other loss mechanisms.
With the objective to reduce the power consumption in the controller during low load conditions, we propose adaptively-biased pulse frequency modulation (ABPFM). The proposed ABPFM technique used along with DVFS and DPM is illustrated in Figure 1. Observe that ABPFM used in conjunction with DVFS has lower power consumption than DVFS by itself, since ABPFM greatly reduces power consumption during the sleep state. As such, the lower the load current requirements, the higher the power savings using ABPFM. The design of an SC converter with the proposed controller is described in Section 2. This includes a detailed description of the adaptively-biased folded-cascode amplifier and the ultra-low-power voltage-controlled oscillator (VCO) with level shifter. The converter implementation and measurement results are presented in Section 3, along with a comparison to state-of-the-art SC converters published in the literature.

SC DC-DC Converter Design and Controller
A conventional 2:1 SC DC-DC converter consists of a single charge transfer capacitor, called the flying capacitor, that delivers charge to the output load capacitor, called the tank capacitor. This conventional topology suffers from asymmetric output voltage ripple and poor load transient response. A symmetric charge-discharge 2:1 SC topology [10,11] divides the flying capacitor into two equal halves, such that each half is operated in anti-phase in order to charge the tank capacitor during both clock phases.
A symmetric charge-discharge topology with the proposed ABPFM controller is shown in Figure 2. The topology employs two-phase time-interleaving to reduce the output voltage ripple. The controller consists of an adaptively-biased error amplifier, an ultra-low-power VCO, an adaptively-biased level shifter (LS), a non-overlapping clock (NOC) generator, and gate drivers. Observe that the output of the error amplifier, V CTRL , is used as a bias input to the error amplifier itself, as well as to the VCO and LS. As in a conventional PFM controller, the output of the amplifier drives the VCO, thereby tuning the frequency. Additionally, in the proposed ABPFM converter, the output of the error amplifier adjusts the bias current in the error amplifier itself and sets the bias current in the LS that follows the VCO.
ABPFM is performed in the control loop to achieve high efficiency at low load currents. The output voltage is sensed by the folded-cascode amplifier, which compares the output voltage, V OUT , with a reference voltage, V REF . This amplifier produces a control voltage, V CTRL , that encodes the SC converter output load current. Load currents from low to high generate low to high V CTRL voltages, respectively.  Figure 3 shows an adaptively-biased folded-cascode amplifier. NMOS mirror M N1 -M N4 is a self-biased cascode current mirror such that (W/L) M N1,2 >> (W/L) M N3,4 . Bias voltages V BP , V CP and V BN are generated using a conventional bias voltage generator [12]. The output of the amplifier, V CTRL , reaches a maximum voltage V CTRL,MAX ≈ V DD − 2V DS,SAT at high load currents and a minimum output voltage of V CTRL,MI N ≈ V SS + V DS,SAT at low load currents. The amplifier bandwidth must be much less than switching frequency f SW [13], so that the average output voltage is regulated at a desired value and the output ripple is minimized. If the bandwidth of the amplifier approaches the output voltage ripple frequency, the amplifier samples the ripple information instead of the average output voltage, causing the loop to be unstable. Low bandwidth is achieved through low input bias current. However, high bias current enables faster transient response. Hence, moderate bias current is normally selected to achieve fast transient response, but at a bandwidth well below f SW . Referring to Figure 3, output voltage V CTRL contains the SC converter load current information. It is used by the amplifier to increase or decrease its bias current at high or low converter load currents, respectively, through long-L transistor M N9 . The ability of the amplifier to set its bias current continuously permits a huge reduction in static power loss when the converter is driving ultra-low current loads. The amplifier is designed for maximum load current conditions. The amplifier bias current is decreased as the load current decreases, reducing the bandwidth of the amplifier. A minimum bias current I MI N must be maintained in the amplifier for stability.

Adaptively-Biased Folded-Cascode Amplifier
The gain bandwidth product (GBW) of the folded-cascode amplifier of Figure 3 is given by [12]: where g m is the input transconductance, R OUT the output resistance, and C OUT the output capacitance.
GBW decreases with g m . Using the long-channel approximation, g m = √ 2I D k W/L, g m decreases with the square root of bias current. This decrease in g m reduces the overall GBW of the amplifier and moves the dominant pole in order to reduce the amplifier bandwidth. This reduction in GBW is critical at low load currents, where the switching frequency is reduced, and the requirement GBW << f SW is maintained [13].
The amplifier has an additional digital input signal, AWAKE. When AWAKE is high, the amplifier bias current is made artificially large in anticipation of the load coming out of sleep mode. The AWAKE signal can be set externally by the PTP detectors in an SoC. These detectors know in advance that the load current requirements are about to increase. In this way, the converter has a much improved output load transient response.

Ultra-Low Power VCO and Level Shifter
A conventional current-starved VCO uses a fixed minimum bias current in each inverter stage in order to oscillate with a large output voltage swing. Using a fixed minimum bias current is a lossy method that limits the peak efficiency when the converter is operating at very low output power.
The proposed ultra-low power VCO shown in Figure 4 solves the above challenge by avoiding a current-starved implementation. The VCO is designed using a fifteen-stage ring oscillator, where the total current from all branches that sets the oscillation frequency is controlled by a single NMOS device M NC . The length of M NC is large to make the VCO linear and achieve a wide oscillation frequency range from a few kHz to hundreds of MHz. Input V CTRL sets the VCO oscillation frequency. Additional delay from transistors M P0 and M N0 in the first stage of the 15-stage ring allows one to obtain a 16-stage equivalent delay. In this way, it is possible to generate two 90 • -phase time-interleaved clocks for the SC converter, labeled CLK 1 and CLK 2 in Figure 4. Variation in the phase of CLK 1 and CLK 2 , due to mismatch in the VCO, increases the output voltage ripple, but does not affect efficiency. In general, low oscillation frequencies in the range of tens of kHz can be generated either by increasing the capacitance in each ring stage or reducing the branch current to a few nA. Increasing the ring stage capacitance limits the peak achievable frequency and also increases the dynamic switching losses. On the other hand, decreasing the branch currents makes the VCO suffer from poor low-side voltage swing.
When the converter is operating at the minimum load current, where the VCO is at the minimum frequency, the voltage swing of the VCO at nodes CLK 1 and CLK 2 is limited to approximately 200 mV. This voltage swing monotonically increases with the oscillation frequency. M NC is a long-L device, which operates in the subthreshold, saturation, and triode regions to generate low, medium, and high frequency oscillations. Switching frequency is directly proportional to load current.
A level shifter (LS) is required to increase the VCO voltage swing and operate over the frequency range of a few kHz to hundreds of MHz. An LS design using conventional methods, such as differential cascode voltage switch (DCVS), current-mirror, and capacitive coupling, suffers from a narrow range of input voltages and/or requires complex circuits that consume significant power [14][15][16].
An LS implementation, which has an input range that swings close to V DD in order to sense the output of the proposed VCO, is shown in Figure 4. The LS is a common-source amplifier with a bias current that is adaptively adjusted by the signal V CTRL , the same signal that sets the VCO oscillation frequency. As V CTRL increases, the bias current in the LS increases, allowing for faster transitions at higher frequencies.
The delay of the LS is less significant as the delay of the error amplifier (labeled gm in Figure 2) is typically higher due to the integration operation. The power consumption of the LS is described below as part of Figure 5.
A simulated power breakdown of the proposed converter as a function of load current is shown in Figure 5. At high load currents, the major power loss contributors are the bottom-plate capacitor (P BP ), large switches (P SW ) in the power stage charging C FLY and C TANK , and gate drivers (P DRIVE ). A relatively small amount of power is consumed in the controller, which is the sum of losses in the amplifier (P AMP ), LS (P LS ), and VCO (P VCO ). As the load current decreases, f SW reduces proportionally, decreasing dynamic losses in P BP , P SW , P DRIVE , and P VCO . In this work, static power losses P AMP and P LS are also reduced with load current through the use of adaptive biasing, achieving high efficiency over a wide load current range. Observe that P LS increases slightly for I LOAD < 50 µA due to the power loss associated with slow transitions in CLK 1 and CLK 2 driving inverter loads, a solution for which is described in [17].

Implementation and Measurement Results
The block diagram of the fully-integrated 2:1 switched-capacitor DC-DC converter shown in Figure 2 was implemented in a 0.18-µm CMOS process with metal-insulator-metal (MIM) and dual-MIM capacitor options. A V I N of 2.0 V was stepped down to 0.9 V while driving a maximum load current of 17.8 mA. A flying MIM capacitor of 515 pF was used for charge transfer [18,19]. An on-chip dual-MIM capacitor of 1.2 nF was used as the tank capacitor, limited by die area. All switches were sized with finite on-resistance to reduce the peak capacitor charging current, such that high efficiency was achieved at peak load current [20]. Signal V REF was given externally.
The converter f SW was set by the output of the folded-cascode amplifier, V CTRL , by sensing the output voltage, V OUT . The proposed VCO was designed to generate f SW from 20 kHz to 49 MHz for applied gate voltages from V CTRL,MI N to V CTRL,MAX . Two clocks at 90 o phase difference were derived from the VCO and level shifted. These clocks were given as input to NOC generators, which produced non-overlapping clocks with at least 1 ns dead time. These clocks went to gate drivers and then powered the switches.

Hardware Measurements
The measured output voltage while driving a peak 17.8 mA current load had an average voltage, <V OUT >, of 0.898 V and ripple, ∆V OUT , of 15 mV. The measured efficiency was 76.7% at a switching frequency of 47 MHz. A peak efficiency of 80.1% was achieved at 10 mA of load current.
The measured efficiency while driving a load current from 4 µA to 17.8 mA is shown in Figure 6a. The measured efficiency was greater than 70% for load currents in the range of 12 µA to 17.8 mA and greater than 60% from 8 µA to 12 µA. The sudden drop in efficiency below 17 µA was due to the dominance of static power loss. The measured switching frequency as a function of load current is shown in Figure 6b. Observe the slope of 5 kHz/µA, equivalent to the rate of change in frequency with respect to load current. A load transient between 10 mA and 100 µA is shown in Figure 7. An overshoot of 70 mV and undershoot of 200 mV were observed. The change in average output voltage during the load transient was 36 mV. When driving 100 µA of load current, the bias currents in the controller were reduced using ABPFM, which lowered the bandwidth of the error amplifier. Prior to a load transient event from 100 µA to 10 mA, the bias current in the error amplifier was increased in order to sense the transient event quickly by setting AWAKE high. The AWAKE signal could be set externally by PTP detectors in an SoC. When AWAKE went high, this increase in bias current reduced the DC gain of the amplifier, causing a slight increase in average output voltage. On the other hand, a large dip of 350 mV in the output voltage occurred if AWAKE was held at zero, as shown with dashed lines in Figure 7. In order to reduce this dip in V OUT to 200 mV, AWAKE was set high several microseconds before the 100 µA to 10 mA transient. No AWAKE pulse was required during the high-to-low load current transient as the bias currents were already high.

Comparison
A comparison of the proposed work with the state-of-the-art of recently published SC converters is shown in Table 1. The proposed converter maintained less than a 10% drop from its peak efficiency over three decades of load current (17.8 mA/12 µA = 1483) and had the highest load current range compared to others. The use of a charge recycling technique in every time-interleaved phase in [8] helped to achieve the record peak efficiency of 94.6% for all fully-integrated SC converters in the literature. However, this converter's efficiency dropped below 60% for load currents <167 µA. On the other hand, our proposed converter had the lowest peak efficiency due to the process limitation in bottom-plate parasitic capacitance. The addition of a charge recycling technique to an ABPFM converter would noticeably improve its peak efficiency. Finally, the proposed converter had the highest power density compared to others except [18], where an area-efficient and costly deep-trench (DT) capacitor was used along with a 33 nF off-chip tank capacitor.
To emphasize the importance of high efficiency over a wide load current range, we propose the following figure-of-merit (FOM): This FOM is the geometric mean of the efficiency limits times the number of decades of load current range. Overall, the proposed converter had the highest FOM, widest load current range, highest minimum efficiency, and highest power density amongst the fully-integrated SC converters in Table 1.

Conclusions
Adaptively-biased pulse-frequency modulation (ABPFM) was introduced in this paper to reduce the static power loss in a low-power DC-DC converter operating in standby/sleep mode. An ultra-low-power VCO was implemented to generate a wide range of frequencies suitable for switching converters. The proposed converter maintained >70% efficiency over three decades of load current range. The proposed ABPFM was implemented with a 2:1 voltage conversion ratio fully-integrated SC DC-DC converter in a 0.18-µm CMOS process. This technique could be applied to extend the battery runtime of wearable devices, which are designed to operate in sleep mode the vast majority of the time.
Author Contributions: The research problem was identified, executed, and solved by both authors. A.V. conducted the literature review, architecture research, feasibility study, and methodology investigation. He also designed, simulated, performed the layout, tested, and wrote the original draft manuscript. He is the main author of the paper. P.M.F. supervised the research that includes and is not limited to: conceptualization, project administration, architecture design, circuit design, simulation and measurement results review, manuscript review, and extensive manuscript corrections. Both authors contributed significantly to this work.
Funding: This research received no external funding.