www.mdpi.com/journal/jlpea/ Review Energy Efficient Design for Body Sensor Nodes

This paper describes the hardware requirements and design constraints that derive from unique features of body sensor networks (BSNs). Based on the BSN requirements, we examine the tradeoff between custom hardware and commercial off the shelf (COTS) designs for BSNs. The broad range of BSN applications includes situations where either custom chips or COTS design is optimal. For both types of nodes, we survey key techniques to improve energy efficiency in BSNs and identify general approaches to energy efficiency in this space.

system design and implementation [5].Although BSNs share many of these challenges and opportunities with general wireless sensor networks (WSNs)-and can therefore build off the body of knowledge associated with them-many BSN-specific research and design questions have emerged that require new lines of inquiry.Unlike generic WSNs that have many nodes doing the same thing, BSNs are likely to have a small number (<10) of nodes with each node dedicated to a specific task.For example, a sensor node monitoring acceleration at the ankle for gait analysis clearly cannot also measure brainwaves using an EEG since both the location and sensing hardware are so different.To achieve widespread adoption, BSN nodes must be extremely noninvasive, which means that the nodes must have a small form factor that is not overly inconvenient to use.Smaller nodes imply smaller batteries, creating strict tradeoffs between BSN node energy consumption and the fidelity, throughput, and latency requirements of BSN applications.Therefore, while the diverse BSN application space results in wide ranging system requirements, all BSN applications-whether real-time or delay insensitive, continuous high data rate streaming or infrequent small packet bursts, etc.-demand energy efficiency while meeting data fidelity requirements.The battery size versus battery life tradeoff plays a major role in defining any BSN system, and applying design techniques to reduce energy consumption can improve both size and lifetime.If energy consumption can be reduced far enough, perpetual operation on harvested energy becomes a possibility.Thus, BSN node sensing, processing, storage, and wireless transmission must all be done in a way that reliably delivers the important data but with the lowest possible energy consumption, thus minimizing battery size (which dominates BSN node form factor) and maximizing time between battery recharge (which is a key factor in wearability), both of which can impact the performance and practicality of possible applications.
The best approach for optimizing the tradeoff between energy consumption and other requirements varies depending on the specific BSN application.To illustrate this, we can consider the tradeoff between battery lifetime (e.g., the application requirement for how long the system must work between re-charges) and effective wireless communication data rate (e.g., the average rate at which data from the node must reach the base station) across different applications.Figure 2 estimates how different applications map to this tradeoff space.Some applications like pulse oximetry (measures saturation of peripheral oxygen, SPO 2 ), ambulatory blood pressure (ABP), or electromyography (EMG) for muscle activity require monitoring lifetimes between an hour (e.g., in the clinic) and a day or two (assuming sensors can be recharged at night), but the quantity of data that must be transferred varies dramatically.Continuous glucose monitoring (CGM) sensors may need to have lifetimes approaching a month, but they do not need to send much data on average.Some RFID-like sensors may only need to work for a second after being queried by a base station acting as a reader, but some long term sensors implanted in the body or incorporated into clothing may need to last for years.This great variety in requirements defies a single solution to solve the energy constraint problem.
For life-critical applications that require continuous high fidelity sensed data for real-time assessment and intervention (e.g., fall detection, heart arrhythmia detection, etc.), which would be very costly to transmit wirelessly, reduction or elimination of wireless transmission may be necessary to meet longer battery life and wearability requirements.Such applications may need to make intervention/actuation decisions on-node and only employ wireless transmission when events of interest are detected.This system level design decision will help to reduce node power consumption sufficiently to satisfy the other system requirements.BSNs for delay insensitive applications, such as those employed by clinicians to gather information in large volume, may alternatively leverage lower power on-node storage, rather than wireless transmission, to increase battery life.Such store-and-forward use cases, including Holter monitoring and activity logging, are capable of acquiring high fidelity data for later assessment off-node.In such cases, on-node processing is limited, as more resource rich or expert assessments are made off-node.Finally, real-time applications involving wireless transmission and high fidelity data (e.g., gait analysis, activity monitoring, gaming, etc.), combine on-node signal processing with radio management to meet battery life demands of hours to days.Value to the user will ultimately determine each technology's success.BSNs must effectively transmit and transform sensed phenomena into valuable information and do so while meeting other system requirements, such as energy efficiency.The value of a BSN therefore rests in large part on its ability to selectively process and deliver information at fidelity levels and rates appropriate to the data's destination, whether that is to a runner curious about her heart rate or a physician needing a patient's electrocardiogram.These disparate application requirements require the ability to aggregate hierarchical information and integrate BSN systems into the existing information technology infrastructure.Increased value of the BSN to the user will also increase user tolerance of non ideal wearability or other technological difficulties.
In this paper, we describe methods for developing efficient hardware within the unique set of requirements of BSNs for different parts of the BSN application design space.Due to the ubiquitous and strict energy constraint on all BSNs, we focus on energy efficiency.In addition, the approaches for achieving energy efficiency in BSNs designed with COTS components sometimes differ from those designed with custom hardware, and this paper explores both paradigms.Finally, this analysis is done within the context of current and projected BSN applications and use cases.The final decision between a custom design versus a COTS design must account for the previous points combined with the economics of the intended application.Designing a COTS system is orders of magnitude faster and cheaper than building a custom IC based node, and COTS nodes provide excellent solutions in many lower lifetime BSN scenarios.For example, low volume research platforms or nodes intended for short term clinical monitoring applications may be more economically produced via a COTS design.In such applications, the final device operational characteristics are much less well defined, and engineering costs are ongoing.In this case the economies of reducing such costs via the employment of a flexible platform outweigh the benefits of extra efficiency that an ASIC solution would offer.For example the TEMPO3 system mentioned in Section 1 may be reprogrammed to operate in a clinical environment in which continuous data streaming is a requirement, or in a more longitudinal study in which data may be stored on node and offloaded after an extended measurement session.Additionally, COTS devices have steadily been improving in computing performance.When TEMPO1 was introduced in 2006, the processor employed had 48 kB of flash memory, 2 kB of RAM, and operated at a maximum clock frequency of 8 MHz.There are now available pin compatible drop-in devices from the same family that have over 100 kB of flash, 8 kB of RAM, and are capable of operating at 20 MHz within similar power budgets.This clearly leads to an expanded application space for a given sensing technology, with little or no non-recurring engineering (NRE) costs for hardware design.High volume, single purpose, mass market devices favor ASIC approaches in which the NRE costs are amortized over many units.Even if COTS systems provide a weaker solution (e.g., by limiting lifetime) than ASICs, simple economics will make COTS the better choice for many BSN applications that cannot provide the volume required to justify an ASIC solution.

General Strategies for Energy Efficient BSN Hardware
We have emphasized that many design decisions depend on the specific BSN application in question, but we can also identify general strategies that should influence any BSN design.In this section, we examine several key tradeoffs that affect BSN design and that provide important opportunities for saving energy regardless of the specific BSN application.Specifically, we examine balances between on-node computation and communication, flexibility and efficiency, and data fidelity and energy consumption.Before describing these tradeoffs, we introduce supply voltage management as a means of energy minimization in circuits, which provides an important foundation for custom energy efficient circuit design of energy constrained systems like BSNs.

Supply Voltage Management
Lowering the supply voltage to a circuit is a well known approach for reducing energy.In this section, we first discuss the limit of lowering voltage to reduce energy consumption, and then describe how dynamic voltage scaling can allow us to tradeoff energy and performance.
For digital circuits, energy of computation varies as the square of the supply voltage (V DD ), which makes it desirable to operate at the lowest possible voltage while preserving functionality and meeting timing constraints.Taking this principle to the extreme, we observe that sub-threshold (sub-V T ) operation of digital integrated circuits provides one important option for energy efficient processing.Sub-V T circuits use a V DD that is below the threshold voltage, V T , of the transistors.This makes the transistors "off" by conventional definitions, but the change in transistor gate-to-source voltage (V GS ) produces a difference in sub-V T conduction current that allows static digital circuits to operate robustly, although slower than they would be at higher voltage.The lower speeds are still more than sufficient for many BSN operations (up to 10's of MHz).Both the off-current and the on-current of the transistors vary exponentially with V DD in the sub-V T region (V GS < V T ).Nevertheless, the on-current in sub-V T remains larger than the off-current by enough (1000× or so) to enable proper functionality of the digital gates.Due to the quadratic relationship between energy and V DD , the main advantage of sub-V T operation is a reduction in energy consumption of over 10× compared to traditional circuit implementations.In fact, sub-V T operation has been shown to minimize energy per operation in conventional CMOS circuits [6].For this reason, sub-threshold operation will play an important role in custom hardware for BSNs.
There are some challenges to making sub-V T digital circuits work.Most notably, the reduced I on /I off ratio combines with process variations in the threshold voltage to increase the potential for circuit failure.Sub-V T circuits also must be level converted to interface with super-V T design, such as radios or sensors.Additionally, design of sub-V T circuits is not yet commonplace.Standard cells used in designs are rarely designed for this voltage of operation, in which transistor strengths change.Nevertheless, sub-V T operation is an emerging approach that is very useful for BSN nodes [7].Operating at a low voltage all of the time may not be a viable option for all BSNs, because lower voltages slow down circuit speed.Given that a BSN's processing latency and throughput requirements may change during execution in response to real-time data and mode changes, dynamic voltage scaling (DVS) can be employed to minimize V DD given those requirements.When high performance is necessary to meet system level requirements, the circuits can operate at the energy-costly higher voltage level.By reducing the circuit's V DD , quadratic energy savings can be achieved instead of just the linear savings obtained through power gating (Figure 4).Different DVS schemes propose different approaches to scaling in terms of the circuit topology and interval at which the voltage is changed, and the overhead of most schemes are minimal compared to the energy savings accomplished, especially when that scaling includes dropping to sub-V T levels when permissible [8].
Some COTS chips provide built-in DVS capabilities or allow for development of DVS schemes.For instance, the TI MSP430 and other similar microcontrollers (MCUs), have on-board clock generation hardware that allows the MCU to programmatically change the operating clock frequency.This is accomplished in the MSP430 through the use of a Digitally Controlled Oscillator (DCO) that may be calibrated using a low frequency (32 kHz) watch crystal as a reference.Frequency agility is accomplished by switching different programmable constants into two clock control registers.The actual change in clock frequency occurs within approximately 10 µs.Furthermore, this microcontroller operates over a wide range of voltages.The clock oscillator may be varied over a 16 to 1 range and the supply voltage over a 2 to 1 range.Within this envelope, a combination of processing rate and power requirements exist, making COTS embedded processors of this type ideal candidates for inclusion in a DVS scheme for BSNs. Figure 5 shows potential DVS operating points measured for the MSP430F2131 processor as explored in [9].For longer lifetime BSN applications where the savings from Figure 5 are still inadequate, a similar DVS scheme can apply to a custom chip.Figure 6 compares a custom MCU design [7] to the MSP430.The custom design offers a 100× improvement in energy per instruction.However, this does not come free of tradeoffs.In this case, the custom built MCU does not have its own clock generation hardware, and frequency agility is not as straight forward since there is only one, single frequency main clock.Though this custom designed MCU also operates over a wide range of voltages and is capable of supporting DVS, additional design effort is required to build in these operating modes.What's more, custom designed hardware does not enjoy the complete suite of mature and compatible peripherals as COTS components, which degrades custom hardware's flexibility.

Communication versus Computation
As is the case in most WSNs, wireless transmission of sensed data is the largest power consumer in most current BSNs [9].This problem is particularly acute in medical BSN applications, in which sensor data rates may be high relative to many WSN applications.Figure 7 illustrates this relationship with the COTS TEMPO platform as an example, where the high power consumption of the Bluetooth transceiver swamps the low power consumption of the TI MSP430 microcontroller during raw data transmission.We could improve this situation by using a lower power radio (e.g., COTS implementing a different protocol, or a custom design), by duty cycling and sending data in bursts, or by other strategies.In this section, however, we focus on the strategy of using computation on the node to reduce the cost of communication, which can influence all types of BSN design regardless of hardware choice.Significant power reduction can be achieved through the development of on-node signal processing and data management which can dramatically reduce the number of bits to be transmitted.By reducing the number of bits to transmit, we effectively allow more substantial duty cycling of the radio (e.g., leaving it off for a larger fraction of the time).Methods to reduce communication data include traditional compression along with advanced signal processing techniques such as pattern classification and feature detection algorithms.Low power signal processing therefore becomes increasingly important to BSN power efficiency.We can quantify the impact of this tradeoff on the overall node energy using a simple energy model.Assume that E r is a ratio of the average energy to transmit one bit (E tx ) to the average energy to process one bit (E proc ).This ratio is typically large (i.e., E r >> 1) and is determined by a number of factors, including processor energy per operation, the signal processing algorithm and implementation, the packet organization and coding, the networking protocol, transmit power, etc.Also assume that the compression ratio (CR) achieved by on-node signal processing is the ratio of the number of raw bits to the number of transmitted bits.The ratio of average processing energy (E proc ) to average total energy (E total ) is therefore: Figure 8 plots this ratio as a function of CR for different values of E r .It is clear that the importance of low power signal processing increases with more effective pre-transmission compression techniques, even at high E r ratios.As a point of reference, 25 nJ/bit is typical for state of the art custom Bluetooth radios targeting 1 Mb/s [10,11], and an MSP 430 consumes roughly 1 nJ/bit.If the system had no other processing costs (e.g., ignoring memory, etc.), it would have an E r of only 25, indicating that processing energy becomes quite important if the CR is even 10.Applying simple generic compression schemes could compress raw data streams by this amount.Even more substantial compression is possible by extracting important features on chip and only transmitting those instead of the raw data.This motivates the need for reducing the hardware energy costs of on-node computation, especially with custom radio solutions.As we described above, sub-threshold operation is one excellent method for decreasing E proc by over 10× compared to operation at the nominal V DD .
Figure 8. Percentage of total energy contributed by on-node signal processing for different E r = E tx /E proc ratios as a function of the bit compression ratio (CR) [9].
The power required to transmit data wirelessly can be high even with reduced duty cycle, so the radio remains a critical component even with on-die data compression.Therefore, it is worthwhile to understand the requirements for BSN radios.BSNs have slightly different radio requirements compared to radios in typical WSNs with low data rate communication for monitoring environmental conditions.For BSN applications, the network is probably arranged as a star-hub topology with the hub acting as a base station [1].All communication from the nodes is to the hub, which can be assumed to have substantially more resources than the nodes (e.g., the hub may be a smart phone).Therefore, the nodes need a small, low power, and short range (1-2 m) radio.This means that a BSN radio could be optimized to operate at a much lower transmission power compared with radios designed for WSN applications.Judging from Figure 2, the ability to accommodate variable communication data rates will be important.Also, since we have observed that processing to reduce the communication data rate allows us to save power by using the radio less often, the radio should save energy when operating at lower data rates or should allow energy efficient transitions to and from active mode.We note that turning off the radio for longer times creates the need to re-synchronize the radio when it turns back on.Since the hub has more resources than the nodes, it can remain active permanently to listen for communication from the nodes.Most radio traffic in a BSN system is from the nodes to the hub, alleviating the need for the nodes to run a receiver continuously looking for messages from the hub.However, the cost of synchronization may still be significant depending on the specific BSN application and communication protocol.
BSN applications can span a large range of data rates from a few bits per minute to almost 1 Mbps depending on the application [5].Currently, there are a few low power radio and radio protocols such as ANT and Zigbee that are commonly used in wireless sensor networks.However, these radios and protocols can only operate with data rates of 10 kbps and 150 kbps, respectively.This severely limits their usefulness for the upper range of BSN applications such as motion assessment, ECG (electrocardiogram), EMG (electromyogram), and EEG (electroencephalogram).Conversely, the high data rate COTS radios and protocols, such as Wi-Fi have data rates which easily cover the entire span of BSN applications.However, these radios and protocols consume so much energy that they are impractical for use on BSNs with longer battery life requirements.Bluetooth is a radio and protocol that sits somewhere in between high data rate and low data rate radios.The protocol uses a large amount of energy due to the fact that it was designed as a very general purpose radio for applications spanning outside of the area of BSN.Bluetooth is convenient for BSN development platform purposes because of its widespread adoption, but its relatively poor energy efficiency leaves room for optimization with custom radios and protocols.Nevertheless, Bluetooth is a convenient and viable option for lower lifetime BSN applications.Due to inefficiencies in existing radios and protocols, there are other protocols that are being developed to accommodate the area of BSNs such as 802.15.6.This protocol specifically targets body sensor devices and the medical applications that can span a wide range of data rates [12].This new protocol supports data rates greater than 850 kbps and allows flexibility for the PHY layers supporting ultra wide band, narrow band, medical implant communication bands, and human body communication PHY.While this new protocol is not a standard yet and is still in working group, it is being designed to be more efficient for BSNs compared to existing options, and their main challenges will be providing efficient access for the broad range of BSN applications (see Figure 2) and achieving the pervasiveness that Bluetooth and Wi-Fi have achieved in smart phones and other personal computing devices.
While there are many COTS radios and protocols available today that are serviceable for BSN applications, there is still a large opportunity for custom radios that provide better energy efficiency for the applications of the BSN community.These radios can take advantage of the small transmission distance and asymmetry of the channel and provide a substantial benefit to the power consumption of the devices.For example, [13] presents a 830 pJ/bit 2.4 GHz radio that can transmit with a data rate of 500 kbps.[14] presents a 2 Mbps low power receiver that consumes 0.18 nJ/b and [15] shows a 0.65 nJ/b 100 kbps receiver at 1.9 GHz.For sub 1 GHz transmission, [16] shows a 1 Mbps OOK transceiver that operates at 10 nJ/bit with very fast startup time of 2.5 µs to allow for efficient duty cycling.All the previously mentioned low power transmitters and receivers take advantage of short range requirements of BSNs and consume much less energy compared to common COTS radios such as Bluetooth and Zigbee.With these improvements in energy consumption, BSNs can run much longer on a single battery charge or the device can be made smaller by allowing the same runtime but with a smaller battery.It is worth noting that since standards for BSNs are still under development, a concrete guideline for low power radios is not readily available.

Flexibility versus Efficiency
The tradeoff between flexibility and efficiency in hardware is well known and very prominent in a comparison of conventional hardware paradigms [17,18].The most flexible category of hardware is general purpose processors (GPPs).GPPs exhibit poor energy efficiency due to the overhead of fetching and decoding the instructions that are required to perform a given operation in the datapath.For low power embedded applications like BSNs, general purpose computation is generally performed in fairly simple microcontrollers [7,[19][20][21].Sophisticated operations like a fast Fourier transform (FFT) or data processing algorithm will thus require numerous instructions in the simple core.For example, several sub-threshold processors provide energy per instruction nearing 1 pJ per operation, but they also tend to use small instruction sets and thus result in more instructions to run an operation [7,[19][20][21].
The most efficient hardware is hardwired to do its specific task or tasks (e.g., ASIC).ASICs achieve very efficient operation, but they can only perform the function for which they were originally defined.Examples of hardwired implementations in sub-threshold circuits include [22][23][24][25].Different types of hardware in sub-threshold systems reveal a similar trend as their above-threshold counterparts.Microcontrollers like the one in [19] consume as low as 2.6 pJ/instruction and provide excellent flexibility since they can be reprogrammed for arbitrary tasks.The ASIC implementation of a JPEG co-processor in [24] consumes 1.3 pJ/frame for VGA JPEG encoding.The numbers for energy/operation are similar, but the individual operations on the microcontroller (e.g., instructions) are simple integer computations like addition.Executing a complete JPEG encoding would take many (100s or 1000s) instructions on such a light weight processor, making the total energy per frame much higher than on the ASIC.Of course, the GPP can perform a much broader range of tasks than the JPEG encoder, so this comparison exemplifies the tradeoff between energy efficiency and flexibility.Some BSN nodes may be implemented as complete ASICs like the JPEG processor, but more commonly, ASICs may appear in BSNs as auxiliary hardware accelerator modules, performing commonly occurring functions in the context of a larger system on chip (SoC).Good examples of hardware acceleration are multipliers, floating point units, or FIR filters.These operations can take several instructions over many clock cycles to complete using a GPP, consuming a large amount of energy and time.A hardware accelerator can process data quickly and efficiently.Here, these commonly used components take advantage of the energy and computational efficiencies of the accelerators, whilst their designs need not change.Hardware accelerators provide an opportunity to process data in very specific ways more efficiently than on accompanying programmable hardware.
Microprocessor operations are largely inefficient, as we described above.Field Programmable Gate Arrays (FPGAs) are reprogrammable hardware that provide an intermediate choice between ASICs and processors in terms of flexibility and efficiency.An FPGA is configured to act like specific hardware, similar to an ASIC, but the configuration can be changed an arbitrary number of times.The cost of this flexibility is that FPGAs consume 10~100 times more energy than an ASIC due to energy overhead from interconnects, which may account for 85% of the total energy consumption.Most commercial FPGAs target high performance applications to compete with processors, but a sub-threshold FPGA [26] demonstrates that custom FPGA implementations can offer a good tradeoff for flexibility and energy efficiency for energy constrained applications like BSNs.
To demonstrate the performance of different hardware platforms in the context of BSN applications, we simulated a typical heart rate (R-R) extraction algorithm that calculates the heart rate of a user based on the raw data of an ECG, which was run on the three different platforms designed in the same technology operating at the same operating voltage (0.4 V) while targeting the same data rate.The results are shown in Table 1.
We make two observations from Table 1.First, not only is ASIC > FPGA > GPP with respect to energy efficiency, but ASIC > FPGA > GPP in terms of potentially speed and performance capacity.The second observation is that there is a drastic improvement in efficiency (>100×) between GPPs and FPGA/ASICs.Therefore, it makes sense to assign on-node processing to FPGA and ASIC platforms, while using GPPs strictly for control or rarely occurring operations.Given the large space of BSN nodes and their applications, there is no obvious optimal platform for all nodes.Though ASICs are extremely efficient in terms of energy minimization and computational capability, they are highly inflexible as their functionality is set.Thus, they must be revisited and redesigned whenever the functionality changes.This is a major drawback, as it leads to increased design time and design cost.Furthermore, ASICs are limited to a certain application space.Therefore, flexibility is another requirement for BSNs that must be examined during the design of a node for a specific application or set of applications.
On the other end of the spectrum, GPPs offer a highly flexible option for on-node processing.Along with popular peripherals, such as the aforementioned floating point unit or multiplier, GPPs are able to perform almost any job and run any processing algorithm for the BSN node.Thus, they are useful in building most nodes, serving as a central controller for the node.The flexibility advantage is most noticeable in generic nodes, where the specific algorithm or signal processing requirements are not pre-determined, but coded into instruction memory.However, this advantage comes at the cost of energy efficiency.GPPs are highly inefficient because of unused logic components and resources within the GPP for each instruction executed.Also, given the instruction per cycle limitations of GPPs, programs cannot fully take advantage of instruction parallelism, resulting in greater latency and energy consumption per package of data processed.State-of-the-art low power COTS GPPs can meet energy and speed requirements for many BSN applications.For example, TI's MSP430 supports a wide range of applications, running on clock frequencies up to 25 MHz while consuming 165 μA/MHz [27].Custom GPPs will be even more efficient but will incur the development costs of an ASIC.
In summary, increasing the flexibility of processing to cover more scenarios will sacrifice energy efficiency.This means that platforms encircling larger regions of Figure 2 will necessarily be less efficient than more targeted solutions, resulting in shorter lifetimes and/or larger form factors.

Data Fidelity versus Energy
The last key tradeoff we will explore involves looking into how much processing and communication is necessarily needed and relevant in an application.Previous work has shown the existence of an energy-fidelity tradeoff in BSNs with digital signal processing employed to examine tremor in a Parkinson's patient [28].This research used Haar wavelet compression and rate-resolution scaling as an example lossy data reduction scheme for use in exploring the tradeoff space since it met the following three criteria: • capable of being implemented on resource-constrained BSN embedded processors; • capable of executing in low-latency and soft real-time applications; • adjustable by key knobs to alter expected data reduction rates.
Mean Squared Error (MSE) was used to assess fidelity as is commonly done in the signal processing community.The results indicated there is a large energy-fidelity exploration space possible in BSNs. Figure 9 shows a small portion of this space using the Haar wavelet transform and run length encoding for data compression and highlights another interesting fact: the input signal characteristics change the possible energy-fidelity operating points.
Moreover, it is interesting to note that the data shown in Figure 9 is from a single patient over the course of a single clinical visit.The amount of "information" present in the sensor signals changes over time along with the rate-distortion curve pointing to the need for dynamic management of energy-fidelity tradeoffs in these embedded environments.To illustrate further, Figure 10 depicts a time domain distortion plot for fixed data compression, yielding a compression ratio (CR) of approximately 18, for a 40 minute tremor dataset.Thus, merely choosing a static operating point on a curve of Figure 9 is not sufficient for application fidelity regulation or energy efficiency.Instead, runtime adjustment of processing methods should be performed for more optimal, data-centric operation.BSN devices must therefore possess energy awareness (knowledge of how much energy has been consumed), data awareness (knowledge of how compression affects current data), and computational resource awareness (knowledge of how algorithm execution affects processing and memory resources) to effectively tradeoff runtime and output fidelity in a way that is executable on resource constrained platforms and that meets real-time requirements.These tradeoff decisions can be made based on efficiently meeting requirements (e.g., maximum lifetime for a given minimum fidelity, maximum fidelity for a given minimum lifetime, etc.) or minimizing bounded cost functions (e.g., minimizing lifetime −α •fidelity −β given minimum lifetime and fidelity requirements, where α and β are determined based on metric priorities).
BSN devices also need adaptable and efficient data rate scaling mechanisms to fully exploit energy-fidelity tradeoffs at the node-level in real-time.For instance, if a MSE ≤ 100 were required for application fidelity to remain acceptable, then any distortion below this level would be considered energy inefficient (marked as the lower region in Figure 10) because data rate could be further reduced to meet the application requirement; and data above this level would not have high enough fidelity to meet the requirement (marked as the upper region in Figure 10).Only by adjusting a data rate knob at runtime would the node operate in an application-specific energy-fidelity optimized range (marked as the middle region in the shaded box of Figure 10).

Case Study of COTS System: TEMPO
TEMPO 3.2 is the latest version of the TEMPO platform which has been designed for a range of BSN applications and illustrates the aforementioned tradeoffs between flexibility and efficiency in a COTS based system platform.Specifically, TEMPO was designed to meet requirements for human motion analysis: a broad category that can contain many specific applications.With this application area in mind, a low power non-invasive device is needed that is still flexible enough to address applications that vary from gait analysis to tremor assessment and activity detection.TEMPO 3.2 uses MEMS accelerometers and gyroscopes to perform inertial sensing to measure and study human motion and wirelessly transmit this data to central aggregator such as a smart phone or PDA.Accelerometers and gyroscopes were chosen for inertial measurement because they are small in size, self contained, and inexpensive when compared with other technologies like optical motion capture or magnetic localization.In order to enable communication to PDAs and smart phones while still keeping power consumption as low as possible, Bluetooth was selected as the communication protocol.While Bluetooth and other standard protocols allow for interoperability, they are not the optimal choice for BSNs, and a networking protocol tailored to these types of systems may be necessary if systems are to be effective and energy efficient.However, standard protocols such as Bluetooth enable quick prototyping for initial data collection which can be beneficial for showing the value of new and emerging BSN technologies.
Also, since the devices need to be a small form factor and wearable, TEMPO 3.2 was created in the form of a large wristwatch.This enables it to be wearable and flexible from design perspective, but puts other significant limitations on the system.The size of the device not only puts restrictions on the size of the electronics, but also has a significant impact on the size and capacity of the battery that powers the device.Therefore, efficiency becomes a large concern for TEMPO 3.2 as it is required to have a runtime of several hours up to several days.
In order to meet the runtime constraints mentioned above, TEMPO 3.2 uses the ultra-low power TI MSP430 microcontroller that still provides the ability to program and load a wide range of functions and digital signal processing techniques.The microprocessor gives the ability to optimize power consumption of the system by compressing data or performing the digital signal processing techniques that let us transmit less data over the radio (the main consumer of power).
However, as is common with many systems, there is a desire to be able to adapt as new technology emerges and as application requirements change.TEMPO 3.2 remains flexible by including a daughter board connector that allows the addition of another sensor for addressing a wider range of applications.Likewise, radio technology is a constantly changing field as newer and lower power technologies are being developed.So TEMPO 3.2 includes the option of taking out the Bluetooth radio and replacing it with a different radio that communicates over the UART or SPI protocols.This leaves TEMPO 3.2 as a general platform that can address a wide range of applications, but does not address a specific application as power and size efficiently as custom hardware could.In summary, this platform utilizes the advantages of COTS based systems such as hardware expandability and interoperability with other commercial devices.Hardware capabilities may be swapped out with pin-compatible ICs and daughter boards to facilitate application reuse along with changing technology standards and software functionality is easily modified and tested which can be beneficial for applications in which the processing requirements are still unknown.These advantages are typical of COTS platforms.However, careful consideration must be given to ensure form factor is kept relatively small even when modifications are done to fully make an attractive BSN node, which is exemplified in [30][31][32].The Mica mote platform presented in [30] sits atop two AA batteries side by side resulting in a form-factor difficult to place on the human body.It contains an 802.15.4 radio with a maximum data rate of 250 kbps and a small 8-bit Atmel processor.No sensors exist on the main circuit board, but a 51-pin expansion connector allows for easy expandability at the expense of wearability.The Telos mote platform presented in [31] provides similar functionality to the Mica mote, comes with a commercial Texas Instrument microcontroller, 16-pin expansion, and optional light, temperature, and humidity sensors on the main board.However, the Telos platform still sits atop two AA batteries with a similar form factor which makes it undesirable for many BSN applications.The BSN node presented in [32] contains the same processor and radio as Telos, but focuses on form factor more extensively.Sensors must be added via a daughter board and the expansion connector with 6 analog channels and two serial ports which adds size.The main board however, is only 26 mm × 26 mm which promotes better wearability.

Case Study of Custom IC System
One example of a custom built BSN is the ECG chip presented in [7].It is a 0.13-μm bulk CMOS sub-threshold (sub-VT) mixed-signal system-on-chip (SoC) that acquires and processes an ECG signal for wireless ECG monitoring.The die photo is shown in Figure 11.The system consists of an adjustable gain instrumentation amplifier (IA), an 8-bit analog to digital converter (A/D), a microprocessor that operates in the sub-threshold region (sub-V T ), and a universal synchronous receiver/transmitter (UART) to communicate with an external radio.The SoC uses a sub-threshold digital microcontroller (μC) for adaptive control of the sub-VT biased analog components and for processing the ECG data.The microcontroller core is a customized variant of the Microchip PIC 16C5X [33].This base unit has 33 instructions and memory sizes of 24 to 73 bytes of RAM.A simple differential IA topology was chosen for the ECG amplifier.Because the amplitude of an ECG signal varies depending on the placement of the recording electrodes and physiological variations between individuals, the IA has a digitally adjustable gain.The 8-bit A/D digitizes the amplified ECG signal at a 1 kHz sampling rate.The A/D uses a dual-slope, integrating architecture.This architecture was chosen for its simplicity, low power consumption, and its insensitivity to device variation.By adjusting the A/D supply voltage, we can trade off power consumption with resolution.This allows for lower system power, since the A/D power can be reduced when the system does not require the full fidelity capabilities of the A/D.The microcontroller, based on a PIC architecture, operates from 0.24 V to 1.2 V and consumes as little as 1.51 pJ per instruction at its minimum energy voltage of 0.28 V.The entire SoC (analog front end, ADC, and digital processor) consumes only 2.6 μW while providing raw ECG data or processed heart rate data.This level of energy efficiency far exceeds the abilities of COTS implementations and makes the idea of an energy harvesting ECG sensor feasible.
When only heart rate information is required, the onboard computation of heart rate reduces the wireless channel data rate by a ratio of 500:1, which allows complete beat-by-beat heart rate information to be communicated with much less energy expended in the radio.This chip exemplifies how low energy processing can be used to increase the effective CR in a BSN by extracting the important information from raw data prior to communication.
This custom SoC platform takes advantage of the fact that the application is well defined, and therefore platform flexibility can be traded off for optimization in energy efficiency and form factor.This platform utilizes the general strategies of communication versus computation and fidelity versus energy to obtain better energy efficiency.Other examples of custom platforms include [34][35][36][37].[34] is a 0.5 × 1.5 × 2 mm 3 size, 5.3 nW intraocular pressure sensor with microprocessor and transmitter that is used to detect glaucoma.It achieves low power by duty cycling, the use of low power clocks, and on board processing.[35] integrates a glucose sensor with a wireless transmitter in a contact lens for diabetes monitoring with a power of 3 µW that is wirelessly transmitted.It utilizes a sub-µW low-power regulator and bandgap reference to achieve its low power profile.[36] is a fully integrated platform that processes heart rate detection and ECG for 445 nW and 895 nW, respectively.It lowers its power profile through the ability to utilize a low power, less precise clock or a higher power, more accurate clock as well as power-efficient biasing analog components.[37] is designed to be used in fabric to monitor vital signs, utilizing only 12 µW.[37] selects their topologies of their low-drop out regulator, analog front end, and A/D carefully to remain under their power budget.As can be seen, design efforts for energy efficiency and very small form factor are two features common for custom platforms.

Conclusions
In this paper, we have explored strategies and methodologies for energy efficient design of BSN nodes.Starting from the characteristics of BSNs that arise from their application space and make them unique (including significant differences from traditional WSNs), we have identified the tradeoff metrics available for design optimization.We then elaborate on general strategies for designing energy efficient hardware, focusing on the tradeoffs of computation versus communication, flexibility versus efficiency, and data fidelity versus energy.We examine key tradeoffs in the BSN space that ultimately may lead to the decision between a COTS based platform or a custom IC design.Finally, we present two cases of previous work to show examples of a COTS based node and a custom designed hardware node.As the field of BSNs continues to grow, we anticipate that a rich selection of design techniques will lead to creative solutions leveraging both types of hardware design and resulting in numerous successful BSN deployments.

Figure 2 .
Figure 2. Broad design space for BSN, but size limits energy for all applications. h

Figure 4 .
Figure 4. Energy-workload curve of normal operation and dynamic voltage scaling (DVS).

Figure 6 .
Figure 6.Energy-delay curves for DVS in a COTS microcontroller and a custom design.

Figure 11 .
Figure 11.Die photograph of the ECG SoC.The analog front end (instrumentation amp (IA) and A/D) and microcontroller (μC) comprise only 0.0633 mm 2 of active area [7].

Table 1 .
Comparison of different hardware platforms.
the BSN node, based on the flexibility versus efficiency discussion.Decide whether a COTS component or custom built hardware is more suitable based on application, flexibility, cost, and purpose.To provide examples for this process, we present two designs for BSN nodes.