Multi-Wire Tri-Gate Silicon Nanowires Reaching Milli-pH Unit Resolution in One Micron Square Footprint

The signal-to-noise ratio of planar ISFET pH sensors deteriorates when reducing the area occupied by the device, thus hampering the scalability of on-chip analytical systems which detect the DNA polymerase through pH measurements. Top-down nano-sized tri-gate transistors, such as silicon nanowires, are designed for high performance solid-state circuits thanks to their superior properties of voltage-to-current transduction, which can be advantageously exploited for pH sensing. A systematic study is carried out on rectangular-shaped nanowires developed in a complementary metal-oxide-semiconductor (CMOS)-compatible technology, showing that reducing the width of the devices below a few hundreds of nanometers leads to higher charge sensitivity. Moreover, devices composed of several wires in parallel further increase the exposed surface per unit footprint area, thus maximizing the signal-to-noise ratio. This technology allows a sub milli-pH unit resolution with a sensor footprint of about 1 µm2, exceeding the performance of previously reported studies on silicon nanowires by two orders of magnitude.

where VG-S denotes the gate-source voltage, VTH the threshold voltage, and ψ0 the potential at the oxide/electrolyte interface. Term A in Equation (1) represents the trans-conductance of the FET. Term B can be expressed as follows: where CGC represents the capacitance between the gate (VG-S) and the inversion charge in the channel (Qi) and CEC relates the induced surface potential with the inversion density. Both term A and term B depend on the electrical properties of the device and on the bias configuration. In case of pH sensing, in which the detected charge is located directly on the front-gate oxide, CEC is the gate oxide capacitance COX and, therefore, it depends on the material the gate insulation is made of and its thickness. The term C of Equation (1)  where kB denotes the Boltzmann constant, T the absolute temperature, q the elementary charge, α the dimensionless sensitivity parameter (0 ≤ α ≤ 1), with CEDL indicating the electrical double layer (EDL) capacitance and CB the buffer capacitance of the surface determined by the density of active OH groups on the gate oxide. The ISFET sensitivity reaches the ideal Nernst limit (59.5 mV/pH at T = 300 K) when α = 1, i.e., when CB is much larger than CEDL. This is the case, e.g., for Al2O3 and HfO2 front-gate oxides [4,5]. Indeed the device sensitivity to pH depends not only on the gate oxide material, but also on the bias of the device and the buffer conditions. As previously reported [5,6], in the case of back-gating (VG-S ≡ VBG-S) one can achieve values of ΔVTH/ΔpH beyond the Nernst's limit. The amplification factor comes from Equation (2) that simplifies as follows: where CBOX denotes the capacitance of the bulk oxide. The change in surface potential on the front-gate side translates effectively into a larger back-gate threshold voltage shift (ΔVTH,BG > Δψ0), due to the difference between the top and back oxide thicknesses [5,6]. In case of front-gating, instead, there is no amplification factor as term B of Equation (1) is reduced to 1. This amplification factor can also be tuned by changing the location and number of active gates. As reported by Jae-Hyuk et al. [7], by designing two active lateral gates, the capacitance ratio given by Equation (2) increases proportionally with the width of the device and so does the sensitivity.
To summarize, an effective strategy to maximize the pH sensitivity in terms of ΔVTH/ΔpH, consists in maximizing the asymmetry between the active gate biasing the device and the biochemical interaction occurring at the top oxide surface, by biasing the device with a back gate, or, in the case of SiO2 surfaces, by utilizing solutions with lower ionic strength. It is important to remark, however, that the back-gating configuration with electrolyte solution left electrically floating can lead to instability problems [8,9]. The SiNRs were biased to operate above threshold (VFG-S ~ 1.8 V), as it has been experimentally observed that this condition guarantees improved performances in terms of drain current stability over time. Indeed subthreshold conditions assure higher sensitivity in terms of relative change of the current with the surface potential, while above threshold there is a higher sensitivity in terms of absolute change (ΔID-S/ΔpH) of the current and a more linear response. In particular, the gate voltage was set so that the maximum variation in surface potential connected to a change in pH does not shift the FET operating point out of the chosen region of operation ( Figure S1a).
In order to maximize the absolute change of the drain current with the pH, the devices are biased in saturation (VD-S = 1.5 V) ( Figure S1b). Moreover, a high VD-S maximizes the dynamic range of the above threshold region of operation ( Figure S1c).  A conditioning cycle is performed in order to prime the front-gate oxide surface. The conditioning cycle consists in injecting the 10 µM KCl buffer solution until the current stabilizes, followed by a solution with pH 3 and pH 8, which are separated by a 10 µM KCl washing step. This conditioning of the surface improves the electrical characteristics of the device, e.g., the subthreshold swing (SS) stabilizes from 130 mV/dec to 100 mV/dec and then remains constant throughout the whole experiment. Once conditioned, the device ID-S-VFG-S characteristic only shifts with a change of the potential at the oxide/electrolyte interface. The silica surface exposed to the solution charges up and attracts a layer of counter ions to maintain the overall charge neutrality, forming an electrical double layer (EDL). The capacitance of the EDL depends on the concentration of the electrolyte and affects the drain current. In order to verify this fact, we put solutions with increasing concentration of Na2SO4 in contact with the SiNRs and monitor the change of the drain current ( Figure S4a). As shown in Figure S4b, the current increases logarithmically for increasing ionic strength of the solution.
To address this issue, the solutions with different pH were designed to minimize the differences in the total ionic strength. must be considered in Equation (5), which becomes: Since the device layout is not symmetric, RS ≠ RD. If we write RS = βRD, with β indicating the ration between the length of source and drain leads; Equation (7) becomes: By calculating the ratio ID-S, 200 mV/ID-S, 100 mV the dependence on K factor is removed and we obtain an equation with the only variable RD. Once the values of RD and RS are known, it is possible to compensate for their effect and the corrected ID-S-VFG-S obtained.
In this work, the devices operates in the saturation working region (VD-S = 1.5 V > VFG-S − VTH). The ID-S in this working regime can be expressed as: Taking into account the series resistances, Equation (9) becomes: From Equation (10) the term K can be extracted and substituted in where we denote the compensated drain current as I'D-S, which can therefore be expressed as: Figure S5 shows the result of the compensation procedure on the current sensitivity of 2 SiNRs. The spectral filtering technique reported in the work of Kirchner et al. [11] has been employed to compensate for the distortions caused by aliasing, which can impact the scaling exponent of f −γ noise [11][12][13][14]. The scaling factor γ is commonly estimated from the power-law slope of the FFT of the noise time-series. However, as these noises typically have significant power above the Nyquist frequency, measurements of their power spectra will often be severely distorted by aliasing. A spectral filtering technique is employed to correct the distortions introduced by spectral aliasing, and recovers the broadband spectrum of f −γ noises. Further details on the employed filtering method can be found in the work of Kirchner et al. [11].
Estimating the alias filter requires a model for the spectrum, so that the ratio of the signal power and the signal-plus-alias power can be estimated. The employed spectral model Smodel (f) for the noise is: This model spectrum scales as f −γ below some specified boundary frequency fBANDWIDTH, then rolls over to a steeper spectral slope at higher frequencies. The frequency fBANDWIDTH indicates the bandwidth of the measurement system, which can be assumed to be not larger than ~50 kHz. Figure S6 illustrates the effect of the filtering technique on the aliased-affected noise spectrum. The iterative algorithm evaluates the value of γ for which the sum of the noise spectrum, modeled as reported in Equation (13), and the corresponding alias best fits the experimental data. At the end of the iterative procedure, the obtained value of γ is ≈1, confirming the nature of the noise affecting the nanoribbon (flicker noise).
Since fBANDWIDTH >> fS = 10 Hz, the exact value of fBANDWIDTH has little effect on the alias-filtered spectrum. For example, changing the value of fBANDWIDTH in the range 1 kHz-1 MHz introduces a discrepancy of less than 1% in the estimation of the scaling factor γ.
Moreover, the spectral filter is conceived so as to remove the (proportional) effect of the modeled aliasing, rather than forcing the alias-filtered spectrum to conform to the model spectrum. As a consequence, mis-specification of the model spectrum has only a small effect on the results of the alias filtering procedure.
The white noise current spectral density of MOSFET transistor can be estimated as [15]: Since at the considered band the level of the white noise is more than 5 orders of magnitude smaller than the f −γ noise introduced by the nanoribbon, its impact on the aliasing is negligible.  The SID of the SiNR, compensated for the aliasing, follows a 1/f behavior. Contrary to what happens in saturation regime (VD-S = 1.5 V), the SID of the SiNR does not increase with higher voltages, but, instead, appears to stabilize. The same behavior can be seen in the gate voltage noise power spectral density (SVG), in which the noise level only slightly depends on the applied VFG-S, with even lower noise level for higher voltages ( Figure S7b). It is worth noting that according to [16] the SVG spectrum can be expressed as: where f0 represents the band at which SVG is evaluated. From Equation (15) and considering a band f0 of 1 Hz with a central frequency of 1 Hz, it is possible to estimate the density of traps NOT, which in the case of the device of Figure S7 results to be approximately 1.12·10 10 cm −2 , which is somewhat larger than similar reports in literature but not unphysical.
Using instead the equation proposed in [17]: where 1/αt = 0.1 nm is the tunneling length, we obtain NOT = 4.3·10 19 cm −3 eV −1 . This value is on the high side of those reported in literature, but not unphysical, given the very large value chosen for αt.
By plotting SID/ID-S 2 against the frequency ( Figure S7c), it is even more clear that, from an SNR perspective, it is convenient to work in strong inversion, at high voltages (VFG-S = 1.2 V). The same conclusion can be drawn when plotting the SID/ID-S 2 vs. ID-S for different sample frequencies ( Figure S7d). Moreover, the fact that SID/ID-S 2 vs. ID-S curves run parallel to the (gm/ID-S) 2 vs. ID-S, when plotted in comparable scales, supports the validity of the carrier number fluctuations (ΔN) as the dominating factor of the flicker noise [18,19]. The noise values of Figure 6c for multi-wire devices are obtained by fitting the data compensated for the aliasing. In particular, the noise level is obtained by calculating the square root of the integral of SID in the frequency range of interest (0.5 Hz-1.5 Hz). The error bars are calculated from the integrals of the prediction bounds, determined with 99.999% confidence. The noise values of single-ribbons are obtained by fitting the noise dependence of the single-ribbons of Figure 5d on the device cross-section total area (WNR + 2·tNR). The noise values and the corresponding error bars of the devices of Figure 5d are calculated as reported Figure S8. The error bars of the extrapolated data are calculated as the difference between the fit and the top/bottom bounds as shown in Figure S9. In order to evaluate the performances of the home-made Ag/AgCl pseudo-reference electrodes (REs), we compared the corresponding voltage drift over time of the RE and the one of a commercial Ag/AgCl (E255 pellet, PHYMEP). The drifts are measured vs. a double junction Ag/AgCl, (6.0726.100, Metrohm) at a concentration of 3 M ( Figure S10).