Power-to-Noise Optimization in the Design of Neural Recording Amplifier Based on Current Scaling, Source Degeneration Resistor, and Current Reuse

This article presents the design of a low-power, low-noise neural signal amplifier for neural recording. The structure reduces the current consumption of the amplifier through current scaling technology and lowers the input-referred noise of the amplifier by combining a source degeneration resistor and current reuse technologies. The amplifier was fabricated using a 0.18 μm CMOS MS RF G process. The results show the front-end amplifier exhibits a measured mid-band gain of 40 dB/46 dB and a bandwidth ranging from 0.54 Hz to 6.1 kHz; the amplifier’s input-referred noise was measured to be 3.1 μVrms, consuming a current of 3.8 μA at a supply voltage of 1.8 V, with a Noise Efficiency Factor (NEF) of 2.97. The single amplifier’s active silicon area is 0.082 mm2.


Introduction
The emerging field of Brain-Machine Interface (BMI) technology utilizes microelectrodes, microelectronics, and computational technologies and has extensive applications in neural research and neuroscience [1].Advanced microelectromechanical systems (MEMS) technology allows for the integration of multiple neural microelectrode systems onto a single silicon chip [2], which can then be implanted into the cerebral cortex.Such systems can simultaneously capture full-spectrum neural signals from multiple neurons.The subsequent analysis of these neural signals allows for the establishment of a connection between neural responses and real bodily activities, thereby facilitating brain-machine control [3].Consequently, neural recording amplifiers play a crucial role in the development of BMI technology and are considered an indispensable component.
The electrochemical effects at the electrode-tissue interface often lead to a DC offset of 1-2 V in differential recording electrodes [4].Therefore, the electrodes need to be AC coupled to the amplifiers to eliminate this offset.Local Field Potentials (LFPs), which are neural signals, typically exhibit amplitudes ranging from 20 µV to 1 mV, covering a frequency range of 1 Hz to 200 Hz.In contrast, Action Potentials (APs) generally have an amplitude of around 50 µV, but they can reach as high as 5 mV in cases of abnormal multi-unit activity; these signals can have a frequency content of up to 5 kHz [5], and occasionally, even higher.
Because neural signals have a low amplitude, noise and interference can significantly affect the recorded signals.Maintaining a low input-referred noise in the amplifier is crucial for obtaining clean neural signal recordings.Technologies commonly used to reduce the input-referred noise in amplifiers include source degeneration resistors [6], current reuse [7,8], and g m -boost [9].In fact, during the process of signal acquisition, the thermal
In this first stage of the schematic, the input signals are AC coupled through a pair of input capacitors (C in ), and a negative feedback network formed by a feedback capacitor (C f ) is applied around the OTA for operation.Hence, the closed-loop gain of the amplifier is defined by the ratio of C in /C f .The lower cutoff frequency (f L ) is given by 1/(2πR pseu C f ), while the higher cutoff frequency (f H ) is given by g m /(2πC L ), where g m represents the transconductance of the OTA, and R pseu is the pseudoresistor formed by the PMOS transistors.One advantage of this design is its ability to occupy a small area while exhibiting resistance characteristics of over 100 GΩ within a voltage difference of less than ±0.2 V [17].Additionally, the resistance value of the pseudo-resistor can be adjusted by an external voltage V tune , allowing for tunable cutoff frequencies.
The calculation formula for the input-referred noise of the amplifier is as follows: Biosensors 2024, 14, 111 where V 2 AMP is the input-referred noise of the amplifier, V 2 OTA is the input-referred noise of the OTA, C p is the parasitic capacitance within the OTA.
According to Equation (1), to achieve a low-noise amplifier, it is essential to ensure that the input capacitance C in >> C f , C p .
x FOR PEER REVIEW 3 of 17 In this first stage of the schematic, the input signals are AC coupled through a pair of input capacitors (Cin), and a negative feedback network formed by a feedback capacitor (Cf) is applied around the OTA for operation.Hence, the closed-loop gain of the amplifier is defined by the ratio of Cin/Cf.The lower cutoff frequency (fL) is given by 1/(2πRpseuCf), while the higher cutoff frequency (fH) is given by gm/(2πCL), where gm represents the transconductance of the OTA, and Rpseu is the pseudoresistor formed by the PMOS transistors.One advantage of this design is its ability to occupy a small area while exhibiting resistance characteristics of over 100 GΩ within a voltage difference of less than ±0.2 V [17].Additionally, the resistance value of the pseudo-resistor can be adjusted by an external voltage Vtune, allowing for tunable cutoff frequencies.
The calculation formula for the input-referred noise of the amplifier is as follows: where is the input-referred noise of the amplifier, is the input-referred noise of the OTA, Cp is the parasitic capacitance within the OTA.
According to Equation (1), to achieve a low-noise amplifier, it is essential to ensure that the input capacitance Cin >> Cf, Cp.
The second stage of the schematic is a Variable Gain Amplifier (VGA).The VGA is based on a CCIA topology as well, and offers two different programmable gains which are set via a programmable capacitor array.Therefore, the total gain of the amplifier can be set to ×200 and ×100.The second stage of the schematic is a Variable Gain Amplifier (VGA).The VGA is based on a CCIA topology as well, and offers two different programmable gains which are set via a programmable capacitor array.Therefore, the total gain of the amplifier can be set to ×200 and ×100.
In addition, due to the significantly lower gain of the VGA in comparison to the gain of the first-stage, the influence of the VGA on the overall amplifier's input-referred noise is correspondingly negligible.Hence, to achieve low-noise performance, it is important to design the first-stage OTA to have low input-referred noise.Section 3 describes the low-noise low-power design technologies used in the OTA.

Proposed OTA
In the OTA depicted in Figure 2, to achieve a 1:10 current scaling and reduce circuit power consumption, we apply a bias voltage V b to M 15 and M 16 .This bias voltage sets the current flowing through M 15 and M 16 at 9/10 I B .Consequently, the current of the branch transistor M 5 -M 8 is configured to be 1/10 I B .This approach enables current scaling in the circuit without requiring additional bias current consumption.The self-biased structure eliminates any additional current consumption from the individual branches that provide bias and removes the necessity for complex circuits to supply the bias voltage to the amplifier.As a result, the operating conditions of the amplifier are simplified.Furthermore, to optimize the noise of the amplifier, we employed source degeneration resistors with identical resistance values and the current mirror transistors M 5 -M 8 are identical while the size of M 15 -M 16 are also identical to mitigate matching errors that could occur when using source degeneration current mirrors with different sizes.The previous approaches to achieve current scaling involved utilizing source degeneration current mirrors with different sizes at the bottom [6,13] to regulate the current replication ratio of source degradation current.However, in the actual manufacturing process, variations and process errors can introduce matching errors when using different sizes of source degeneration current mirrors.This can result in inaccurate current replication ratios and increase the risks of equipment mismatch.Therefore, the use of different sizes of source degeneration current mirrors carries a higher risk of errors and can lead to increased equipment mismatch.To mitigate these risks, employing source degeneration current mirrors with the same size can help reduce matching errors and enhance the overall performance and reliability of the equipment.
plifier.As a result, the operating conditions of the amplifier are simplified.Furthermore, to optimize the noise of the amplifier, we employed source degeneration resistors with identical resistance values and the current mirror transistors M5-M8 are identical while the size of M15-M16 are also identical to mitigate matching errors that could occur when using source degeneration current mirrors with different sizes.The previous approaches to achieve current scaling involved utilizing source degeneration current mirrors with different sizes at the bottom [6,13] to regulate the current replication ratio of source degradation current.However, in the actual manufacturing process, variations and process errors can introduce matching errors when using different sizes of source degeneration current mirrors.This can result in inaccurate current replication ratios and increase the risks of equipment mismatch.Therefore, the use of different sizes of source degeneration current mirrors carries a higher risk of errors and can lead to increased equipment mismatch.To mitigate these risks, employing source degeneration current mirrors with the same size can help reduce matching errors and enhance the overall performance and reliability of the equipment.To minimize the input-referred noise of the amplifier, our focus lies in reducing the contribution of transistor noise.In the conventional OTA without the source degeneration resistor, the transistor produces significant noise due to its substantial channel current.In To minimize the input-referred noise of the amplifier, our focus lies in reducing the contribution of transistor noise.In the conventional OTA without the source degeneration resistor, the transistor produces significant noise due to its substantial channel current.In contrast, our design utilizes the source-degenerated NMOS transistor, comprising a transistor and a source degeneration resistor, as illustrated in Figure 2. The noise generated by a source degeneration NMOS transistor primarily arises from the resistor, resulting in a significantly lower noise contribution compared to an MOS transistor operating at the same current level.Another benefit of employing source-degenerated NMOS transistors is that the noise induced by resistors is predominantly thermal noise, while NMOS transistors tend to produce a notable amount of 1/f noise unless they are sized with a considerably large area.In our neural amplifier, the input differential pair is composed of a pair of stacked large-area PMOS transistors, which is the major noise contributor of the amplifier.
The PMOS transistors are chosen due to the fact that the 1/f noise of a PMOS transistor is one to two orders of magnitude lower than the 1/f noise of an NMOS transistor of the same size, as long as it does not significantly exceed the threshold voltage [17,18].

Maximizing G m Analysis and Noise Analysis
To achieve low input-referred noise, it is crucial to maximize the transconductance (G m ) of the OTA under a given total current.The maximum achievable G m for an OTA is typically the transconductance of the PMOS transistor in the input differential pair, which we can refer to as g m1 .Therefore, G m ≈ g m1 .Consequently, it is advantageous to operate the input transistors in the subthreshold region to maximize the g m at a given current level.This implies that the input transistors need to have a larger W/L ratio.Based on this consideration, combined with Figure 3c,d, enhancing the input differential pair through the use of current reuse technology can increase the transconductance of the input differential pair without consuming additional current.
sistors tend to produce a notable amount of 1/f noise unless they are sized with a cons erably large area.In our neural amplifier, the input differential pair is composed of a p of stacked large-area PMOS transistors, which is the major noise contributor of the amp fier.The PMOS transistors are chosen due to the fact that the 1/f noise of a PMOS transis is one to two orders of magnitude lower than the 1/f noise of an NMOS transistor of t same size, as long as it does not significantly exceed the threshold voltage [17,18].

Maximizing Gm Analysis and Noise Analysis
To achieve low input-referred noise, it is crucial to maximize the transconductan (Gm) of the OTA under a given total current.The maximum achievable Gm for an OTA typically the transconductance of the PMOS transistor in the input differential pair, wh we can refer to as gm1.Therefore, Gm ≈ gm1.Consequently, it is advantageous to operate t input transistors in the subthreshold region to maximize the gm at a given current lev This implies that the input transistors need to have a larger W/L ratio.Based on this co sideration, combined with Figure 3c,d, enhancing the input differential pair through t use of current reuse technology can increase the transconductance of the input different pair without consuming additional current.The total input-referred thermal noise can be approximately calculated by (2).
where k is the Boltzmann constant, T is the absolute temperature, and gm is the transco ductance of its transistor.To reduce the total input-referred thermal noise, gm5, gm7, gm and gm15 must be significantly less than gm1 to minimize the noise contribution of the d vices M5-M8 and M13-M16.After designing M5-M8 and M13-M16, gm5-gm8 and gm13-gm16 b come the minimum.We can analyze M5-M8, M15, and M16 in combination with Figure 4 The total input-referred thermal noise can be approximately calculated by (2).
V 2 in,thermal = [ where k is the Boltzmann constant, T is the absolute temperature, and g m is the transconductance of its transistor.To reduce the total input-referred thermal noise, g m5 , g m7 , g m13 , and g m15 must be significantly less than g m1 to minimize the noise contribution of the devices M 5 -M 8 and M 13 -M 16 .After designing M 5 -M 8 and M 13 -M 16 , g m5 -g m8 and g m13 -g m16 become the minimum.We can analyze M 5 -M 8 , M 15 , and M 16 in combination with Figure 4. Figure 4 illustrates the schematic diagram of the circuit used to determine the equivalent transconductance of a source-degenerated NMOS transistor.In Figure 4b, the opencircuit voltage (V oc ), short circuit current (i sc ), and equivalent resistance (R eq ) are defined.Assuming a small signal current of zero enters the drain of the transistor, the resulting voltage on R s is reduced to zero.This condition renders R s independent of V gs and V oc .Furthermore, the transistor's equivalent resistance is increased by a factor of (1 + g me R s ), where g me represents the effective transconductance of the transistor (accounting for the body effect).Because i sc = V oc /R eq , and V oc is not influenced by R s , the i sc decreases by the same factor as the output resistance increases.Considering the aforementioned properties, we can construct an equivalent transistor for an NMOS transistor with source degeneration, as depicted in Figure 4c.Including R s in the circuit has an overall effect of increasing the output impedance (R o ) and decreasing the equivalent transconductance (G m ).By defining G m and R o and utilizing Equations ( 3), ( 5), and ( 6), we can ensure that the open-circuit voltage of the equivalent transistor remains unaffected by R s .Using this method, we can determine the equivalent transconductance of a source-degenerated NMOS transistor, as demonstrated in Equation (7), where R o is equal to R eq .Figure 4 illustrates the schematic diagram of the circuit used to determine the equivalent transconductance of a source-degenerated NMOS transistor.In Figure 4b, the opencircuit voltage (Voc), short circuit current (isc), and equivalent resistance (Req) are defined.Assuming a small signal current of zero enters the drain of the transistor, the resulting voltage on Rs is reduced to zero.This condition renders Rs independent of Vgs and Voc.Furthermore, the transistor's equivalent resistance is increased by a factor of (1+gmeRs), where gme represents the effective transconductance of the transistor (accounting for the body effect).Because isc = Voc/Req, and Voc is not influenced by Rs, the isc decreases by the same factor as the output resistance increases.Considering the aforementioned properties, we can construct an equivalent transistor for an NMOS transistor with source degeneration, as depicted in Figure 4c.Including Rs in the circuit has an overall effect of increasing the output impedance (Ro) and decreasing the equivalent transconductance (Gm).By defining Gm and Ro and utilizing Equations ( 3), ( 5), and (6), we can ensure that the opencircuit voltage of the equivalent transistor remains unaffected by Rs.Using this method, we can determine the equivalent transconductance of a source-degenerated NMOS transistor, as demonstrated in Equation (7), where Ro is equal to Req.
According to Formula (7), the source degeneration transistor can result in a higher equivalent resistance (Ro) and a lower transconductance (Gm).This has significance in op- According to Formula (7), the source degeneration transistor can result in a higher equivalent resistance (R o ) and a lower transconductance (G m ).This has significance in optimizing the input-referred noise of the amplifier.
Table 1 illustrates the operating points for transistors in the OTA.As shown in Table 1, by operating M 1 -M 4 in the subthreshold region, we achieved a high g m /I D ratio such that g m1 is much greater than g m5 -g m8 and g m13 -g m16 , combining Figure 3, using current reuse technology to enhance the transconductance of the input transistors, with g m1 = g mos1 + g mos3.(The g mos1 is the transconductance of M 1 and the g mos3 is the transconductance of M 3 ).
As mentioned in Section 3.1, the 1/f noise (flicker noise) is also a key noise contributor in low-noise, low-frequency circuits.We mitigate the impact of flicker noise by using PMOS transistors as input devices and employing devices with large gate-source areas.The flicker noise is inversely proportional to the gate-source area, so all transistors should be made as large as possible to minimize the 1/f noise.However, as devices M 5 -M 8 and M 13 -M 16 are made larger, the total capacitance seen by the gate of M 5 -M 8 and M 13 -M 16 increase, and according to (1), when those transistors are made larger, C p increases, and the total input-referred noise of the OTA also increases.To ensure noise minimization, there is an optimal size for M 5 -M 8 and M 13 -M 16 .In our design, we decreased the size of M 5 -M 8 and M 13 -M 16 as much as possible, trading off the input-referred noise.

Noise Efficiency Factor
As mentioned in Section 1, the NEF proposed in [4] is adopted: where V ni,rms is the total input-referred rms noise voltage, I tot is the total supply current, and BW is the −3 dB bandwidth of the amplifier in hertz, respectively.The NEF limitation for MOSFET-based amplifiers stems from their current noise and maximum gm/I D [19].The input-referred rms noise of the ideal MOS transistor is expressed as where γ is the noise coefficient and g m is the transconductance of an MOS transistor.
When the transistor operates in the subthreshold region, we obtain g m = κI D /U T , and the input-referred rms noise of the ideal MOS transistor [19] is expressed as The theoretical limit of the NEF of an OTA that uses a differential pair as an input stage is when the two differential pair transistors are the only noise sources in the circuit.
The input-referred noise of the OTA is then V 2 ni,rms = 2 × V 2 mos,rms .Assuming a first-order roll-off of the frequency response, the input-referred rms noise of the ideal OTA is expressed as Combining ( 8) and ( 11), we obtain the theoretical limit for the NEF of any OTA that uses a subthreshold MOS differential pair to be Assuming a typical value of κ = 0.7 and as mentioned in Section 3.1, a 1:10 current scaling ratio is employed to lower the power consumption of the amplifier.Consequently, the total current consumption of the first stage amplifier is equivalent to 2.2 times I B. Therefore, I tot = 2.2 I D .We can conclude that the theoretical limit value of the NEF is 2.12.

Detailed Circuit Implementation
The amplifier was fabricated in the TSMC 0.18µm CMOS 1P6M process.All the source degeneration resistors are constructed using high-resistance polysilicon, with a resistance value of 186 KΩ.Metal-Insulator-Metal (MIM) capacitors are used for C in and C f , which offer high-precision capacitance for accurately defining the closed-loop gain of the amplifier.By setting the value of C in to 20 pF and C f to 200 fF, the first stage is designed to provide a gain of approximately 100 (40 dB).The second stage offers a controllable gain of x2 and x1, thus setting the total gain of the amplifier to be ×200 and ×100, the total gain adjustable (×200, ×100).Each amplifier occupies active silicon the area of 0.082 mm 2 .An on-chip bandgap reference circuit generates all the reference currents and voltages for the entire chip to minimize the use of off-chip components.A chip microphotograph of the amplifier is shown in Figure 5 (the chip measures 2 mm × 4.2 mm, and contains 64 channels of a low-noise, low-power neural amplifier, a 64 to 1 MUX, a bandgap reference, and an ADC buffer).
Biosensors 2024, 14, x FOR PEER REVIEW 8 of 17 Assuming a typical value of κ = 0.7 and as mentioned in Section 3.1, a 1:10 current scaling ratio is employed to lower the power consumption of the amplifier.Consequently, the total current consumption of the first stage amplifier is equivalent to 2.2 times IB.Therefore, Itot = 2.2 ID.We can conclude that the theoretical limit value of the NEF is 2.12.

Detailed Circuit Implementation
The amplifier was fabricated in the TSMC 0.18μm CMOS 1P6M process.All the source degeneration resistors are constructed using high-resistance polysilicon, with a resistance value of 186 KΩ.Metal-Insulator-Metal (MIM) capacitors are used for Cin and Cf, which offer high-precision capacitance for accurately defining the closed-loop gain of the amplifier.By setting the value of Cin to 20 pF and Cf to 200 fF, the first stage is designed to provide a gain of approximately 100 (40 dB).The second stage offers a controllable gain of x2 and x1, thus setting the total gain of the amplifier to be ×200 and ×100, the total gain adjustable (×200, ×100).Each amplifier occupies active silicon the area of 0.082 mm 2 .An on-chip bandgap reference circuit generates all the reference currents and voltages for the entire chip to minimize the use of off-chip components.A chip microphotograph of the amplifier is shown in Figure 5 (the chip measures 2 mm × 4.2 mm, and contains 64 channels of a low-noise, low-power neural amplifier, a 64 to 1 MUX, a bandgap reference, and an ADC buffer).

Measurement Results
Each channel of the amplifier consumes 3.8 μA from a 1.8 V supply, which can be broken down as follows.The first-stage OTA consumes 3.6 μA, and the second-stage VGA consumes 0.2 μA.We do not include the bias current (1 μA), since it can be shared by many amplifiers in the array.
Figure 6 displays the equipment used for the measurements, including the test board, along with the observed waveforms.Figure 6b-d

Measurement Results
Each channel of the amplifier consumes 3.8 µA from a 1.8 V supply, which can be broken down as follows.The first-stage OTA consumes 3.6 µA, and the second-stage VGA consumes 0.2 µA.We do not include the bias current (1 µA), since it can be shared by many amplifiers in the array.
Figure 6 displays the equipment used for the measurements, including the test board, along with the observed waveforms.Figure 6b-d show that when inputting 1 mVpp, 1 kHz ramp, sine, and artificial cardiac signals generated by the Keysight 33600 A true waveform generator, the DC measurement of the output waveform is performed using a Tektronix MSO54 Mixed Signal Oscilloscope.As mentioned in Section 1, the DC offset is an issue to be considered in a neural signal amplifier.Since the reference voltage of the amplifier is 0.9 V, it is expected that the output waveform of the amplifier will exhibit fluctuations above and below 0.9 V. Therefore, conducting DC measurements can serve as a means to verify this behavior.
waveform generator, the DC measurement of the output waveform is performed using a Tektronix MSO54 Mixed Signal Oscilloscope.As mentioned in Section 1, the DC offset is an issue to be considered in a neural signal amplifier.Since the reference voltage of the amplifier is 0.9 V, it is expected that the output waveform of the amplifier will exhibit fluctuations above and below 0.9 V. Therefore, conducting DC measurements can serve as a means to verify this behavior.The blue part is a long period of waveform, and the red part is a part of waveform captured from it for display.When sin signal/ramp signal/artificial cardiac signal is input, the output signal of the amplifier is the sin signal/ramp signal/artificial cardiac signal amplified according to the scale.
As mentioned in Section 1, taking into account the characteristics of the LFPs and APs, the −3 dB bandwidth of the amplifier should be designed to capture a wide range of neural signals.To achieve this, the high-pass corner frequency of the amplifier can be measurement when inputting a 1 mVpp 1 kHz artificial cardiac signal.The blue part is a long period of waveform, and the red part is a part of waveform captured from it for display.When sin signal/ramp signal/artificial cardiac signal is input, the output signal of the amplifier is the sin signal/ramp signal/artificial cardiac signal amplified according to the scale.
As mentioned in Section 1, taking into account the characteristics of the LFPs and APs, the −3 dB bandwidth of the amplifier should be designed to capture a wide range of neural signals.To achieve this, the high-pass corner frequency of the amplifier can be adjusted to 0.54 Hz, allowing for the recording of low-frequency signals.Additionally, a load capacitor of 8 pF was chosen to establish the low-pass corner frequency of the amplifier at 6.1 kHz, enabling the inclusion of high-frequency signals within the bandwidth.Figure 7 shows the AC frequency response of one channel of the overall amplifier.The amplifier has a measured low-pass cut-off frequency of 6.1 kHz, and its high-pass cut-off frequency is tunable from 0.54 Hz to 182 Hz by V tune , the voltage of V tune is regulated by a potentiometer.load capacitor of 8 pF was chosen to establish the low-pass corner frequency of the amplifier at 6.1 kHz, enabling the inclusion of high-frequency signals within the bandwidth.Figure 7 shows the AC frequency response of one channel of the overall amplifier.The amplifier has a measured low-pass cut-off frequency of 6.1 kHz, and its high-pass cut-off frequency is tunable from 0.54 Hz to 182 Hz by Vtune, the voltage of Vtune is regulated by a potentiometer.The measured CMRR and PSRR are shown in Figure 8.The CMRR is calculated as the ratio of the differential-mode gain to the common-mode gain.The PSRR is calculated as the ratio of the differential-mode gain to the gain from the power supply to the output.The measured CMRR and PSRR exceed 66 and 84 dB at 1 kHz, respectively.The measured CMRR and PSRR are shown in Figure 8.The CMRR is calculated as the ratio of the differential-mode gain to the common-mode gain.The PSRR is calculated as the ratio of the differential-mode gain to the gain from the power supply to the output.The measured CMRR and PSRR exceed 66 and 84 dB at 1 kHz, respectively.The measured input-referred noise spectrum of the amplifier is shown in Figure 9, which is obtained by dividing the output noise spectrum by the mid-band gain of the amplifier (at a gain of 100).The 1/f noise corner of the design was found to be roughly 22 Hz.The measured transient input-referred noise waveform is shown in Figure 10. Figure 10a records the input-referred peak-to-peak noise voltage in the frequency range 1 Hz to 6.1 kHz; the total input-referred rms noise is 3.1 μVrms integrated from 1 Hz to 6.1 kHz.The measured integrated noise is 0.96 and 2.95 μVrms in the frequency band of 1-200 Hz and 0.2 k-6.1 kHz, respectively.An input-referred peak-to-peak voltage noise of 5.9 μVpp The measured input-referred noise spectrum of the amplifier is shown in Figure 9, which is obtained by dividing the output noise spectrum by the mid-band gain of the amplifier (at a gain of 100).The 1/f noise corner of the design was found to be roughly 22 Hz.The measured transient input-referred noise waveform is shown in Figure 10. Figure 10a records the input-referred peak-to-peak noise voltage in the frequency range 1 Hz to 6.1 kHz; the total input-referred rms noise is 3.1 µVrms integrated from 1 Hz to 6.1 kHz.The measured integrated noise is 0.96 and 2.95 µVrms in the frequency band of 1-200 Hz and 0.2 k-6.1 kHz, respectively.An input-referred peak-to-peak voltage noise of 5.9 µVpp (1-200 Hz) and 18 µVpp (0.2 k-6.1 kHz) are measured, as shown in Figure 10b,c, respectively.By using (9), the NEF of the amplifier is calculated to be 2.97 from the measurement results.The power efficiency factor (PEF) that includes the supply voltage VDD is also an important parameter for evaluating the power efficiency for biomedical amplifiers.The PEF can be calculated as And the PEF of the amplifier is calculated to be 10.17. Figure 11 [6,7,9,13,[15][16][17][20][21][22][23][24][25][26][27][28][29][30][31] shows the input-referred noise versus the supply current of the amplifier.The proposed work features a low input-referred noise while achieving a competitive NEF.Table 2 compares the proposed work with state-of-the-art designs in the literature.Three different topologies of AFEs are compared.Although [20] and [32]   The power efficiency factor (PEF) that includes the supply voltage VDD is also an important parameter for evaluating the power efficiency for biomedical amplifiers.The PEF can be calculated as And the PEF of the amplifier is calculated to be 10.17. Figure 11 [6,7,9,13,[15][16][17][20][21][22][23][24][25][26][27][28][29][30][31] shows the input-referred noise versus the supply current of the amplifier.The proposed work features a low input-referred noise while achieving a competitive NEF.Table 2 compares the proposed work with state-of-the-art designs in the literature.Three different topologies of AFEs are compared.Although [20] and [32]  The power efficiency factor (PEF) that includes the supply voltage VDD is also an important parameter for evaluating the power efficiency for biomedical amplifiers.The PEF can be calculated as And the PEF of the amplifier is calculated to be 10.17.
Figure 11 [6,7,9,13,[15][16][17][20][21][22][23][24][25][26][27][28][29][30][31] shows the input-referred noise versus the supply current of the amplifier.The proposed work features a low input-referred noise while achieving a competitive NEF.Table 2 compares the proposed work with state-of-the-art designs in the literature.Three different topologies of AFEs are compared.Although [20] and [32] achieved impressive NEF (Noise Efficiency Factor) values of 1.07 and 0.86, respectively.In [20] a NEF value of 1.07 was obtained by stacking three gm cells.On the other hand, [32] utilized five differential pairs with AC-coupled inputs to achieve an NEF value of 0.86.Such aggressive stacking of g m cells results in limited headroom for each transistor.Typical amplifier designs are currently used in the industry, such as the CCIA [17] and Chopper [33] structures, as well as existing applications in the field of BMI aiming for high-resolution and high-density neural probes like Neuralpixels [34,35].The design offers several advantages.Firstly, it occupies a smaller area compared to other designs, allowing for the efficient use of limited chip real estate.Additionally, the design achieves a smaller input-referred noise, leading to improved signal quality.Moreover, it provides a larger range of −3 dB bandwidth, enabling the recording of a wider range of signals.Furthermore, the design exhibits relatively low power consumption, making it energy-efficient.Lastly, the NEF and PEF of the design are also superior under the 0.18 µm CMOS process.In [20], a NEF value of 1.07 was obtained by stacking three gm cells.On the other hand, [32] utilized five differential pairs with AC-coupled inputs to achieve an NEF value of 0.86.Such aggressive stacking of gm cells results in limited headroom for each transistor.Typical amplifier designs are currently used in the industry, such as the CCIA [17] and Chopper [33] structures, as well as existing applications in the field of BMI aiming for high-resolution and high-density neural probes like Neuralpixels [34,35].The design offers several advantages.Firstly, it occupies a smaller area compared to other designs, allowing for the efficient use of limited chip real estate.Additionally, the design achieves a smaller input-referred noise, leading to improved signal quality.Moreover, it provides a larger range of −3 dB bandwidth, enabling the recording of a wider range of signals.Furthermore, the design exhibits relatively low power consumption, making it energy-efficient.Lastly, the NEF and PEF of the design are also superior under the 0.18 μm CMOS process.

Figure 11.
Comparison with the existing amplifier designs of the input-referred noise versus the supply current of the amplifier (references: [6,7,9,13,[15][16][17][20][21][22][23][24][25][26][27][28][29][30][31]).These colored slashes represent the value of NEF, such as the pink line, where the value of NEF is 1, the area below the slash is NEF < 1, and the area above the slash is NEF > 1.The green and brown lines work the same way.For example, for the work of Tang, T, 2019, the NEF value of this work is below NEF = 2 (green line) and above NEF = 1 (pink line), which can show that its NEF value is between 1-2.The position of each work point in the picture is based on the current consumed by its design.The resulting -3dB bandwidth and the input referred noise.[6,7,9,13,[15][16][17][20][21][22][23][24][25][26][27][28][29][30][31]).These colored slashes represent the value of NEF, such as the pink line, where the value of NEF is 1, the area below the slash is NEF < 1, and the area above the slash is NEF > 1.The green and brown lines work the same way.For example, for the work of Tang, T, 2019, the NEF value of this work is below NEF = 2 (green line) and above NEF = 1 (pink line), which can show that its NEF value is between 1-2.The position of each work point in the picture is based on the current consumed by its design.The resulting −3 dB bandwidth and the input referred noise.

Conclusions
In this paper, a low-noise and low-power amplifier with a CCIA topology is proposed for neural signal acquisition.The amplifier reduces input-referred noise by stacking two PMOS transistors in combination with source degeneration resistor technology, rather than stacking multiple g m cells that consume headroom for each transistor.And the current scaling technology is used to reduce the power consumption of the amplifier.Different from the traditional current scaling technology, this design uses two separate NMOS transistors to divide the current, so as to achieve current scaling.In contrast to the traditional approach, which requires additional bias current branches, this design method is more energy efficient.The design was fabricated using the TSMC 0.18 µm MS RF G process.The measurement results demonstrate the amplifier's favorable power and noise performance.The measured −3 dB bandwidth of 0.54 Hz-6.1 kHz indicates its capability to record LFPs and APs.This architecture is well suited as a front-end amplifier for power-constrained or energy-sensitive applications, particularly in the field of biomedical implants.

Figure 1 .
Figure 1.Overall schematic of the neural amplifier.

Figure 1 .
Figure 1.Overall schematic of the neural amplifier.

Figure 2 .
Figure 2. Circuit diagram of the low-power, low-noise OTA used in this design.

Figure 2 .
Figure 2. Circuit diagram of the low-power, low-noise OTA used in this design.

Figure 3 .
Figure 3. (a) Small-signal model of a PMOS transistor.(b) Small-signal model of an NMOS tran tor.(c) Small-signal model of a PMOS transistor based on current reuse.(d) Small-signal mode an NMOS transistor based on current reuse.

Figure 3 .
Figure 3. (a) Small-signal model of a PMOS transistor.(b) Small-signal model of an NMOS transistor.(c) Small-signal model of a PMOS transistor based on current reuse.(d) Small-signal model of an NMOS transistor based on current reuse.

Figure 4 .
Figure 4. (a) An NMOS transistor with source degeneration.(b) An equivalent circuit is used to analyze NMOS transistor with source degeneration.(c) An NMOS transistor with source degeneration is equivalent to a single transistor with a smaller transconductance (Gm) and larger output impedance (Ro).

Figure 4 .
Figure 4. (a) An NMOS transistor with source degeneration.(b) An equivalent circuit is used to analyze NMOS transistor with source degeneration.(c) An NMOS transistor with source degeneration is equivalent to a single transistor with a smaller transconductance (G m ) and larger output impedance (R o ).
v oc = −g m r o v in(3)

Figure 5 .
Figure 5. Die microphotograph of the proposed neural recording amplifier ASIC.

Figure 5 .
Figure 5. Die microphotograph of the proposed neural recording amplifier ASIC.

Figure 6 .
Figure 6.(a) Test equipment and test board.(b) DC measurement when inputting a 1 mVpp, 1 kHz ramping signal.(c) DC measurement when inputting a 1 mVpp 1 kHz sine signal.(d) DC measurement when inputting a 1 mVpp 1 kHz artificial cardiac signal.The blue part is a long period of waveform, and the red part is a part of waveform captured from it for display.When sin signal/ramp signal/artificial cardiac signal is input, the output signal of the amplifier is the sin signal/ramp signal/artificial cardiac signal amplified according to the scale.

Figure 6 .
Figure 6.(a) Test equipment and test board.(b) DC measurement when inputting a 1 mVpp, 1 kHz ramping signal.(c) DC measurement when inputting a 1 mVpp 1 kHz sine signal.(d) DCmeasurement when inputting a 1 mVpp 1 kHz artificial cardiac signal.The blue part is a long period of waveform, and the red part is a part of waveform captured from it for display.When sin signal/ramp signal/artificial cardiac signal is input, the output signal of the amplifier is the sin signal/ramp signal/artificial cardiac signal amplified according to the scale.

Figure 7 .
Figure 7. Measured frequency response of the neural recording amplifier with tunable high−pass corner frequency.

Figure 7 .
Figure 7. Measured frequency response of the neural recording amplifier with tunable high−pass corner frequency.

Figure 8 .
Figure 8. CMRR and PSRR measurements of the neural recording amplifier.

Biosensors 2024 , 17 Figure 9 .
Figure 9. Measured output noise and input-referred noise spectrum of the proposed amplifier (at a gain of 100).

Figure 9 . 17 Figure 9 .
Figure 9. Measured output noise and input-referred noise spectrum of the proposed amplifier (at a gain of 100).

Figure 11 .
Figure 11.Comparison with the existing amplifier designs of the input-referred noise versus the supply current of the amplifier (references:[6,7,9,13,[15][16][17][20][21][22][23][24][25][26][27][28][29][30][31]).These colored slashes represent the value of NEF, such as the pink line, where the value of NEF is 1, the area below the slash is NEF < 1, and the area above the slash is NEF > 1.The green and brown lines work the same way.For example, for the work of Tang, T, 2019, the NEF value of this work is below NEF = 2 (green line) and above NEF = 1 (pink line), which can show that its NEF value is between 1-2.The position of each work point in the picture is based on the current consumed by its design.The resulting −3 dB bandwidth and the input referred noise.

Table 1 .
Operating points for transistors in the OTA.

Table 2 .
Performance and comparison of the proposed neural amplifier.