Improvement of the Bias Stress Stability in 2D MoS2 and WS2 Transistors with a TiO2 Interfacial Layer

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.


Introduction
The process of extreme scaling-down to reach a physical channel length limit of sub-100 nm has caused critical problems, such as a short channel effect and increased leakage current. To address these limitations, efforts have recently been made to scrutinize promising semiconducting materials. In particular, atomically thin layered transition metal dichalcogenides (TMDs) have attracted great attention due to their extraordinary electrical, optical, and mechanical properties [1][2][3][4][5][6][7][8][9]. One of their most attractive properties is the existence of a band-gap and its facile engineering. For instance, single-layer molybdenum disulfide (MoS 2 ) has a direct band-gap of~1.8 eV, and multilayer MoS 2 has an indirect band-gap of~1.2 eV [1]. The physical properties of 2D TMDs have led to their applications in various electronic devices such as transistors, memory devices, and opto-electronic devices [10][11][12][13][14][15][16][17][18]. Among them, the most promising device is the field caused effect transistor (FET), which functions as an essential switching component of display back-plane circuits [12].
However, a few challenging issues around employing 2D TMD-based FETs for practical applications have to be resolved. Fabricating large-scale, high-quality continuous 2D TMD films and the direct deposition of the gate dielectric layer on a 2D surface with a low surface energy are important issues in terms of the utilization of conventional Si fabrication infrastructures and the realization of high-mobility FETs. Furthermore, the unreliable performance of 2D TMD FETs has been a critical concern that must be preferentially addressed. Chemically and mechanically disordered surface and interface states are the origin of the performance instability of semiconductor devices, causing a large hysteresis window and a significant threshold voltage (V TH ) shift.
The passivation of the polymer layer on the 2D TMDs is an efficient countermeasure against the instability of 2D semiconductor-based FET performance [19,20]. Using a similar method, Zheng et al. reported that the hysteresis window of the 2D layered materials capped with an Al 2 O 3 was considerably reduced [20]. Meanwhile, the contact engineering strategy for modifying the interface states between a metal and a 2D semiconductor has been actively studied [21][22][23][24][25][26][27][28]. Because the operation of the 2D TMD FET is based on a modulation of the Schottky-barrier, the interface quality at the metal/TMD contact becomes more critical. Several approaches to reduce the contact resistance, including a doping technique and selection of proper work function metal, have been proposed [26,28]. Meanwhile, Fermi-level pinning usually occurs at a metal/semiconductor contact region, causing high contact resistance due to a fixed high band offset regardless of the work function value of the metal [25,26,29]. Because the interface states usually serve as carrier trapping sites, it is hard to realize the high performance of 2D TMD FETs. Thus, a reliable and simple approach for Fermi-level depinning is necessary. The corresponding result was reported for an MoS 2 device with an interfacial oxide layer [29].
Herein, the effect of the interfacial buffer layer at the metal/2D TMD (MoS 2 and WS 2 ) contact on transistor performance was experimentally and theoretically investigated. Titanium dioxide (TiO 2 ) was used as a buffer layer because its band offset with MoS 2 and WS 2 is relatively small and tunnel resistance can be minimized with the thin TiO 2 layer. By employing a TiO 2 interlayer, interface states were successfully reduced, achieving an increased drive current and the enhancement of long term bias stress stability. In addition, the role of the TiO 2 layer on MoS 2 was theoretically elucidated using a density function theory (DFT) simulation. It can be highlighted that we suggested a facile approach to achieve both higher transistor performance and stability at the same time.

Materials and Methods
A mechanical exfoliation method using scotch tape to obtain high-quality 2D TMD flakes was adopted, and then the exfoliated 2D TMD flakes (MoS 2 and WS 2 ) were transferred onto a SiO 2 (300 nm)/heavily doped Si substrate. To identify the existence of the 2D TMDs, MoS 2 was mechanically exfoliated from the bulk mineral, and the multilayer MoS 2 was characterized using Raman spectroscopy ( Figure 1a). LabRAM ARAMIS (laser wavelength: 473 nm, 50 mW) was used for Raman measurements. Two prominent peaks feature the in-plane E 1 2g mode (~384 cm −1 ) and the out-of-plane A 1g mode (~409 cm −1 ) of the MoS 2 . A frequency difference of~25 cm −1 between two vibrational modes indicates a multilayer MoS 2 . To determine the thickness of the exfoliated MoS 2 , we performed an atomic force microscopy (AFM) analysis. As shown in Figure 1b, the 92 nm-thick MoS 2 was transferred onto the SiO 2 /Si substrate using a typical scotch-tape exfoliation method.
To investigate the effect of the TiO 2 interlayer on the device's contact properties, 2D FET devices with back gate electrodes were fabricated: a control device without TiO 2 and a testing device with TiO 2 . Figure 1c shows the 3D schematic image of the FET device with the 2D TMD-TiO 2 -Ti/Au structure. The TiO 2 interfacial layer on the 2D TMDs was deposited using an atomic layer deposition (ALD) technique based on a tetrakis-dimethyl-amido-titanium (TDMAT) precursor at 200 • C. The pulse and purging times were 0.2 s and 20 s, respectively. The number of cycles were 15, resulting in a 2~3 nm thickness. The thickness of the TiO 2 layer was also optimized to avoid high tunnel resistance. The 2D TMD transistor devices were made by a conventional photolithography process. Photolithography was conducted after spin-coating of the photoresist (AZ 5214, MicroChemicals, Germany), and the metal was deposited by a physical vapor evaporator. Electron beam evaporation was selected to minimize the physical damage on the surface of the TMDs. Lift-off processes were sequentially performed to make the source and drain electrodes. The channel distance between source and drain was~3 µm. After device fabrication, the post-annealing process was conducted in a vacuum environment at 300 • C. The process of the vacuum annealing step included a 30 min ramping time to 300 • C, for a 1 h duration, and a cool down at room temperature. The electrical characterization (transfer, output, and stress measurement) was performed with a Keithley 4200-SCS (Keithley, Cleveland, OH, US). Stress measurement followed the conventional stress-measure-stress sequence for 10,000 s, which is summarized in Figure S6 of the Supplementary Materials information. Photolithography was conducted after spin-coating of the photoresist (AZ 5214, MicroChemicals, Germany), and the metal was deposited by a physical vapor evaporator. Electron beam evaporation was selected to minimize the physical damage on the surface of the TMDs. Lift-off processes were sequentially performed to make the source and drain electrodes. The channel distance between source and drain was ~3 μm. After device fabrication, the post-annealing process was conducted in a vacuum environment at 300 °C. The process of the vacuum annealing step included a 30 min ramping time to 300 °C, for a 1 h duration, and a cool down at room temperature. The electrical characterization (transfer, output, and stress measurement) was performed with a Keithley 4200-SCS (Keithley, Cleveland, OH, US). Stress measurement followed the conventional stress-measure-stress sequence for 10,000 s, which is summarized in Figure S6 of the Supplementary Materials information.  Figure 1d shows a cross-sectional high-resolution transmission electron microscopy (HRTEM) image of the MoS2-TiO2-Ti stacked structure. The lattice constant of the MoS2 was measured to be ~0.65 nm along the c-plane [0001] direction in a hexagonal close-packed crystal structure. A thin (~3 nm-thick) TiO2 layer, deposited using the atomic layer deposition process, was inserted between the Ti metal and MoS2. Interestingly, the discontinuous layers of the MoS2 layers exhibited a step-like crystal structure. Thus, it is reasonably expected that randomness in the defect density for the exposed edge planes and basal planes can cause considerable deviation from the physical interface states, thereby inducing a large difference in the electrical properties of MoS2. The structural disorder of the MoS2 surface is also a strong source for Fermi-level pinning, which caused some points of the band gap to be locked (pinned) to the Fermi-level. This made the Schottky-barrier height considerably insensitive to the metal's work function. The Fermi-level pinning phenomenon, with respect to various metals (for instance, Ti, Cr, Au, and Pd), is illustrated in Figure S1 in the Supplementary Materials information. Even in the corresponding literature studies, the existence of dangling bonds in TMD has been proven via in-depth analyses, such as scanning tunneling microscopy and inductively coupled plasma-mass spectroscopy [30][31][32][33].  A thin (~3 nm-thick) TiO2 layer, deposited using the atomic layer deposition process, was inserted between the Ti metal and MoS 2 . Interestingly, the discontinuous layers of the MoS 2 layers exhibited a step-like crystal structure. Thus, it is reasonably expected that randomness in the defect density for the exposed edge planes and basal planes can cause considerable deviation from the physical interface states, thereby inducing a large difference in the electrical properties of MoS 2 . The structural disorder of the MoS 2 surface is also a strong source for Fermi-level pinning, which caused some points of the band gap to be locked (pinned) to the Fermi-level. This made the Schottky-barrier height considerably insensitive to the metal's work function. The Fermi-level pinning phenomenon, with respect to various metals (for instance, Ti, Cr, Au, and Pd), is illustrated in Figure S1 in the Supplementary Materials information. Even in the corresponding literature studies, the existence of dangling bonds in TMD has been proven via in-depth analyses, such as scanning tunneling microscopy and inductively coupled plasma-mass spectroscopy [30][31][32][33].

Results and Discussion
To investigate the influence of a TiO 2 interfacial layer on the MoS 2 and WS 2 device performance, electrical measurements were performed. Basic electrical characterizations were carried out with a

Results and Discussion
To investigate the influence of a TiO2 interfacial layer on the MoS2 and WS2 device performance, electrical measurements were performed. Basic electrical characterizations were carried out with a Keithley 4200-SCS (Keithley, Cleveland, OH, US) analyzer. Figure 2a shows a comparison between the transfer characteristics (IDS-VBG) of the MoS2-Ti and MoS2-TiO2-Ti devices. The gate-bias sweeping ranged from −50 to 20 V at a fixed drain voltage of 0.1 V. A typical unipolar n-type behavior and a depletion mode of MoS2 transistor devices were observed. The MoS2-TiO2-Ti device with a TiO2 interfacial layer showed more enhanced performance with a higher drive on current (ION). ION values for devices without and with the TiO2 layer are 0.36 and 1.22 μA, respectively. The field effect mobility (μFE) values for MoS2-Ti and MoS2-TiO2-Ti devices were estimated to be 1.38 and 6.08 cm 2 /V·s, respectively. The transfer curves at variable drain voltages and output characteristic also confirmed the better performance of the testing devices with the TiO2 layer ( Figure S2   A more interesting result was observed on the WS2 FETs. Figure 2b shows a comparison of the IDS-VBG transfer characteristics of the WS2-Ti and WS2-TiO2-Ti structured devices. The bi-polar behavior of the WS2-Ti structured devices was observed, which is consistent with the previous results [34]. It is highly likely that the Fermi-level of the Ti metal exists within the mid-gap of WS2. The transfer curve of the WS2-TiO2-Ti structured device showed stronger n-type unipolar behavior with a higher ION current than that of the WS2-Ti device. As shown in Figure 2c, we also characterized the WS2 devices using Pd metal electrodes with a relatively high work function of ~5.1 eV to understand the mid-gap pinning and the effects of an interfacial layer. The addition of the TiO2 layer on the WS2 caused a change from a weak bipolar to a p-type unipolar behavior. This result indicates that a high Schottky-barrier can be effectively reduced by a contact engineering approach utilizing a very thin TiO2 interfacial layer. The IDS-VBG curves of the WS2 FETs at various drain voltages are also shown in Figure S4 of the Supplementary Materials information. The performance enhancement of the 2D FET devices with the interfacial TiO2 layer is attributed to the considerable reduction in the density of the diverse interface states, resulting from the direct contact between the metal and the 2D semiconductor channel. Comparison of the proposed band diagrams between the 2D TMD-Ti and 2D TMD-TiO2-Ti devices highlights the change in the Schottky-barrier height as shown in Figure S5 in the Supplementary Materials information. In principle, the theoretical Fermi-level alignment between the metal and semiconductor, called Fermi-level depinning, also creates a more effective carrier modulation of the 2D TMD FET device. For practical transistor applications, the electrical stability of the MoS2 based FET devices was examined under a long-term positive gate-bias stress condition, as shown in Figure 3a-d. Figure 3a,b shows the shift of the IDS-VBG curves during the long-term gate-bias stress test. The transfer I-V curve properties were monitored every logarithmic time interval (1, 10, 100, 1000, and 10,000 s) while continuously applying +10 V to the gate electrode. Schemes to illustrate the stress measurement set up environment and the data checking points are shown in Figure S6 of the Supplementary Materials A more interesting result was observed on the WS 2 FETs. Figure 2b shows a comparison of the I DS -V BG transfer characteristics of the WS 2 -Ti and WS 2 -TiO 2 -Ti structured devices. The bi-polar behavior of the WS 2 -Ti structured devices was observed, which is consistent with the previous results [34]. It is highly likely that the Fermi-level of the Ti metal exists within the mid-gap of WS 2 . The transfer curve of the WS 2 -TiO 2 -Ti structured device showed stronger n-type unipolar behavior with a higher I ON current than that of the WS 2 -Ti device. As shown in Figure 2c, we also characterized the WS 2 devices using Pd metal electrodes with a relatively high work function of~5.1 eV to understand the mid-gap pinning and the effects of an interfacial layer. The addition of the TiO 2 layer on the WS 2 caused a change from a weak bipolar to a p-type unipolar behavior. This result indicates that a high Schottky-barrier can be effectively reduced by a contact engineering approach utilizing a very thin TiO 2 interfacial layer. The I DS -V BG curves of the WS 2 FETs at various drain voltages are also shown in Figure S4 of the Supplementary Materials information. The performance enhancement of the 2D FET devices with the interfacial TiO 2 layer is attributed to the considerable reduction in the density of the diverse interface states, resulting from the direct contact between the metal and the 2D semiconductor channel. Comparison of the proposed band diagrams between the 2D TMD-Ti and 2D TMD-TiO 2 -Ti devices highlights the change in the Schottky-barrier height as shown in Figure  S5 in the Supplementary Materials information. In principle, the theoretical Fermi-level alignment between the metal and semiconductor, called Fermi-level depinning, also creates a more effective carrier modulation of the 2D TMD FET device.
For practical transistor applications, the electrical stability of the MoS 2 based FET devices was examined under a long-term positive gate-bias stress condition, as shown in Figure 3a-d. Figure 3a,b shows the shift of the I DS -V BG curves during the long-term gate-bias stress test. The transfer I-V curve properties were monitored every logarithmic time interval (1, 10, 100, 1000, and 10,000 s) while continuously applying +10 V to the gate electrode. Schemes to illustrate the stress measurement set up environment and the data checking points are shown in Figure S6 of the Supplementary Materials information. Even if the I DS -V BG curves in all of the MoS 2 -Ti and MoS 2 -TiO 2 -Ti devices were slightly shifted to the positive direction, the device with the TiO 2 layer showed less of a shift than that without TiO 2 , indicating more stable electrical properties compared to the control device without TiO 2 . Interestingly, in Figure 3b, the variation of I OFF values for the MoS 2 -TiO 2 -Ti stack seems more severe than that of the control MoS 2 -Ti device. The actual differences of the minimum and maximum I OFF values are 4.20 × 10 −12 A and 3.68 × 10 −10 A for MoS 2 -Ti and MoS 2 -TiO 2 -Ti, respectively. The I OFF fluctuation of all the devices was less than 1 nA, and this fluctuation was negligible in operation. Figure 3c shows a summary of the threshold voltage (V TH ) change for MoS 2 -Ti and MoS 2 -TiO 2 -Ti stacked devices as a function of stress time, which was extracted from the raw data from Figure 3a,b. The MoS 2 FET without a TiO 2 layer showed a more positive V TH shift than that of the MoS 2 FET with a TiO 2 layer. The V TH shift for the MoS 2 FET without and with a TiO 2 interfacial layer was 3.1 and 1.1 V, respectively. The TiO 2 layer could serve as a buffer layer to mitigate the interfacial damage from electrical stress. As shown in Figure 3d, we also compared the field-effect mobility (µ FE ) values for the devices without and with a TiO 2 layer. The µ FE was estimated by following equation: where g m is the maximum transconductance that can be achieved from I DS -V BG , L is the channel length, W is the channel width, V DS is the applied drain bias, and C ox is the gate oxide capacitance. information. Even if the IDS-VBG curves in all of the MoS2-Ti and MoS2-TiO2-Ti devices were slightly shifted to the positive direction, the device with the TiO2 layer showed less of a shift than that without TiO2, indicating more stable electrical properties compared to the control device without TiO2. Interestingly, in Figure 3b, the variation of IOFF values for the MoS2-TiO2-Ti stack seems more severe than that of the control MoS2-Ti device. The actual differences of the minimum and maximum IOFF values are 4.20 × 10 −12 A and 3.68 × 10 −10 A for MoS2-Ti and MoS2-TiO2-Ti, respectively. The IOFF fluctuation of all the devices was less than 1 nA, and this fluctuation was negligible in operation. Figure 3c shows a summary of the threshold voltage (VTH) change for MoS2-Ti and MoS2-TiO2-Ti stacked devices as a function of stress time, which was extracted from the raw data from Figure 3a,b. The MoS2 FET without a TiO2 layer showed a more positive VTH shift than that of the MoS2 FET with a TiO2 layer. The VTH shift for the MoS2 FET without and with a TiO2 interfacial layer was 3.1 and 1.1 V, respectively. The TiO2 layer could serve as a buffer layer to mitigate the interfacial damage from electrical stress. As shown in Figure 3d, we also compared the field-effect mobility (μFE) values for the devices without and with a TiO2 layer. The μFE was estimated by following equation: where gm is the maximum transconductance that can be achieved from IDS-VBG, L is the channel length, W is the channel width, VDS is the applied drain bias, and Cox is the gate oxide capacitance. Overall, the μFE of MoS2-TiO2-Ti device was higher than that of the MoS2-Ti device. After 10,000 s stress time, the μFE was reduced from 0.22 to 0.17 cm 2 /Vs for the device without a TiO2 layer and from 8.05 to 6.14 cm 2 /Vs for the device with a TiO2 layer. Approximately, 25% of the μFE reduction was observed for both cases. Overall, the µ FE of MoS 2 -TiO 2 -Ti device was higher than that of the MoS 2 -Ti device. After 10,000 s stress time, the µ FE was reduced from 0.22 to 0.17 cm 2 /Vs for the device without a TiO 2 layer and from 8.05 to 6.14 cm 2 /Vs for the device with a TiO 2 layer. Approximately, 25% of the µ FE reduction was observed for both cases.
Additionally, the stability of the contact region for the WS 2 -based FET devices was also determined for the effect of the interfacial TiO 2 layer on bias stress stability, as shown in Figure 4a,b. As can be seen, the transfer curves of the WS 2 -Ti contact FET device showed bipolar behavior where both electron and hole carriers contribute to the current flow of the semiconductor channel. Overall, a lower V TH shift was observed for the FET with a TiO 2 layer compared to the FET without a TiO 2 layer, indicating that the introduction of the TiO 2 interfacial layer on the WS 2 layered film is also an effective approach for improving the contact reliability of the WS 2 device, as well as the case of MoS 2 device. Specifically, the V TH shifts for the WS 2 FET without and with a TiO 2 interfacial layer were 8 and 4.3 V, respectively ( Figure 4c). As shown in Figure 4d, the change of µ FE as a function of stress time was also fitted: the mobility value was almost unchanged for the control device without a TiO 2 layer and from 0.41 to 0.18 cm 2 /Vs for the testing device with a TiO 2 layer. Nanomaterials 2019, 9, x FOR PEER REVIEW 6 of 9 Additionally, the stability of the contact region for the WS2-based FET devices was also determined for the effect of the interfacial TiO2 layer on bias stress stability, as shown in Figure 4a,b. As can be seen, the transfer curves of the WS2-Ti contact FET device showed bipolar behavior where both electron and hole carriers contribute to the current flow of the semiconductor channel. Overall, a lower VTH shift was observed for the FET with a TiO2 layer compared to the FET without a TiO2 layer, indicating that the introduction of the TiO2 interfacial layer on the WS2 layered film is also an effective approach for improving the contact reliability of the WS2 device, as well as the case of MoS2 device. Specifically, the VTH shifts for the WS2 FET without and with a TiO2 interfacial layer were 8 and 4.3 V, respectively ( Figure 4c). As shown in Figure 4d, the change of μFE as a function of stress time was also fitted: the mobility value was almost unchanged for the control device without a TiO2 layer and from 0.41 to 0.18 cm 2 /Vs for the testing device with a TiO2 layer. Indeed, the WS2 FET device was more vulnerable to electrical stress than MoS2, which might be due to greater number of interface states at the metal/semiconductor contact. The metal-induced gap states indispensably exist on the metal/semiconductor interface, which induces the instability of transistor performance. Additionally, there is a quantum mechanically long distance of 2-3 Å between the metal and 2D TMD, which increases the tunneling probability of charge carriers [35]. The more stable performance of the 2D TMD devices with an insulating TiO2 layer might be understood by a mitigation of those gap states and a reduction in physical distance.
To unveil how the TiO2 layer electronically influences the MoS2 semiconductor, we explored a theoretical simulation of electronic states for free-standing MoS2 and MoS2/TiO2 materials via a density functional theory (DFT) calculation ( Figure 5). The density of states (DOS) calculation result of the free standing MoS2 showed the existence of a forbidden gap (Figure 5a). Meanwhile, the  Indeed, the WS 2 FET device was more vulnerable to electrical stress than MoS 2 , which might be due to greater number of interface states at the metal/semiconductor contact. The metal-induced gap states indispensably exist on the metal/semiconductor interface, which induces the instability of transistor performance. Additionally, there is a quantum mechanically long distance of 2-3 Å between the metal and 2D TMD, which increases the tunneling probability of charge carriers [35]. The more stable performance of the 2D TMD devices with an insulating TiO 2 layer might be understood by a mitigation of those gap states and a reduction in physical distance.
To unveil how the TiO 2 layer electronically influences the MoS 2 semiconductor, we explored a theoretical simulation of electronic states for free-standing MoS 2 and MoS 2 /TiO 2 materials via a density functional theory (DFT) calculation ( Figure 5). The density of states (DOS) calculation result of the free standing MoS 2 showed the existence of a forbidden gap (Figure 5a). Meanwhile, the TiO 2 /MoS 2 hybrid combination featured a spin-polarized metallic behavior. The calculated DOS clearly validates that the addition of the TiO 2 layer leads to the modification of the electronical band structure of the junction region, offering the benefit of a doping effect on MoS 2 . Nanomaterials 2019, 9, x FOR PEER REVIEW 7 of 9 TiO2/MoS2 hybrid combination featured a spin-polarized metallic behavior. The calculated DOS clearly validates that the addition of the TiO2 layer leads to the modification of the electronical band structure of the junction region, offering the benefit of a doping effect on MoS2.

Conclusions
The effect of a TiO 2 interfacial layer on metal/TMD (MoS 2 and WS 2 ) contact was experimentally and theoretically studied. The advantages of a Schottky-type FET device, possibly implemented according to the value of a metal work function, were achieved in the 2D TMD devices with a TiO 2 layer. Furthermore, a more enhanced and stable electrical performance for the 2D TMD FET devices with the TiO 2 interfacial layer could be obtained under a gate-bias stress condition. The TiO 2 interfacial layer could serve as a Fermi-level de-pinning layer, reducing the density of the interface states. Additionally, the DFT calculation validates the doping effect of the TiO 2 interfacial layer on the 2D MoS 2 . The strategy of inserting a very thin insulating layer into the contact region will be also applied to diverse 2D TMD-based FET devices.

Conflicts of Interest:
The authors declare no conflict of interest.