GFET Asymmetric Transfer Response Analysis through Access Region Resistances

Graphene-based devices are planned to augment the functionality of Si and III-V based technology in radio-frequency (RF) electronics. The expectations in designing graphene field-effect transistors (GFETs) with enhanced RF performance have attracted significant experimental efforts, mainly concentrated on achieving high mobility samples. However, little attention has been paid, so far, to the role of the access regions in these devices. Here, we analyse in detail, via numerical simulations, how the GFET transfer response is severely impacted by these regions, showing that they play a significant role in the asymmetric saturated behaviour commonly observed in GFETs. We also investigate how the modulation of the access region conductivity (i.e., by the influence of a back gate) and the presence of imperfections in the graphene layer (e.g., charge puddles) affects the transfer response. The analysis is extended to assess the application of GFETs for RF applications, by evaluating their cut-off frequency.


Introduction
Two-dimensional materials (2DMs) have awakened the great interest of the nanotechnology community during the last decade [1]. Their striking physical properties, intrinsically different from their 3D counterparts, open a vast field of opportunities only partially exploited so far. Among these alternatives, 2DMs find a natural spot in electronics, where their monoatomic thickness makes them especially attractive to overcome the hurdles related to the transistor scaling-down [2].
Graphene is not only the pioneer, but also the most singular member of the 2DM family [3]. It is characterized by a gapless Dirac-cone bandstructure, where electrons and holes have symmetric dispersion relationships. The literature is abundant in Graphene Field-Effect Transistors (GFETs) [4][5][6], where this particular band structure is manifested in an ambipolar behaviour and a poor I ON /I OFF ratio (direct consequence of the easiness to switch the carrier transport from electrons to holes and vice versa). This issue jeopardizes the use of GFETs in digital electronics, although a successful demonstration has been achieved in [7]. In radio-frequency (RF), however, graphene has revealed itself as an interesting candidate [8], and devices with cut-off frequencies of hundreds of GHz have already been demonstrated [9,10], even reaching wafer scale integration [11], or being applied for flexible electronics [12,13]. The main strategies to boost GFETs performance have consisted of the

Device Simulation
A schematic depiction of the physical structure of the simulated GFET is shown in Figure 1. The graphene flake is sandwiched in between a top insulator layer, with thickness t TOX and dielectric permittivity ε TOX , and an insulating substrate, with thickness t BOX and dielectric permittivity ε BOX . Both oxides are assumed thick enough as to neglect any tunnelling current through them. A four-terminal device is considered, with a front gate extending over a length L Chn (the device channel length), giving rise to two under-lapped regions of length L Acc (the access region length) that connect it with the source and drain terminals. The back gate, when considered, extends all along the structure including the channel as well as the access regions. V FG , V BG , and V D stand for the front gate, back gate, and drain terminal biases respectively, while the source terminal, V S , is assumed to be grounded. The total resistance of this structure, R T , can be schematically split into the series combination of three resistances corresponding to the source access region (R S,Acc ), the channel region (R Chn ) and the drain access region (R D,Acc ).
To determine the I − V response of GFET devices, we have self-consistently solved the coupled Poisson, Drift-Diffusion and continuity equations [23,24]. For the device modelling, we have considered a longitudinal x − y section of the GFET, assuming invariance along the device width (z). The resulting 2D Poisson equation is given by: where V is the electrostatic potential; ρ is the net charge density in the structure, that comprises the mobile (electrons and holes) and fixed (dopants) charges; and ε is the dielectric permittivity. The Drift-Diffusion transport equation is formulated in terms of the pseudo-Fermi level (E F ) as proposed in [25]: where V E F is the potential associated with this level and n 1D (p 1D ) is the graphene electron (hole) 1D density profile. Here, µ n (µ p ) stands for the electron (hole) mobility. Due to the extreme confinement, the carriers are supposed to move only along the transport direction (x). J must comply with the continuity equation that, under steady-state conditions, is formulated as: ∇ · J = 0. Ohmic contacts are assumed at the source and drain terminals, with the Fermi level at the source grounded, E F,S = 0, and at the drain given by E F,D = −qV DS . The equation system is then iteratively solved for each set of terminal biases, until a convergence threshold is achieved for the potential and charge concentrations. In addition to the mobile charge and dopants in the graphene layer, we account for the existence of puddles [26,27]. Their associated charge density, N p , is assumed constant and added to both electron and hole charge densities [28]. In this way, puddles impact on the overall graphene layer conductivity while conserving a neutral net charge character.

Validation
To assess the capability of the numerical simulator to reproduce and explain the experimental results, we have first validated it against the devices fabricated in [29,30]. Both are GFETs based on monolayer graphene embedded between a SiO 2 layer, which acts as a substrate, and a Y 2 O 3 layer, which acts as a front gate dielectric. In both cases, this Y 2 O 3 layer is 5 nm thick while the substrate is 300 nm thick in [29], and 286 nm thick in [30]. For the device presented in [29], the distance between the source and drain contacts is 1.5 µm and the front gate length is 600 nm, while in [30] the device is 8.2 µm long and its front gate is 7 µm long. In other words, in both experimental devices the gate contact does not cover the whole region between source and drain contacts, thus creating two symmetrical under-lapped regions at both channel edges; namely, the device access regions. To reproduce the data reported in [29], the same mobility is assumed for both types of carriers, electrons and holes (µ = µ n = µ p ) with a value of 90 cm 2 /Vs, and a puddle charge density of 7·10 11 cm −2 is considered. N-type chemical doping of 10 12 cm −2 is defined for the graphene layer. To account for the graphene-metal contact resistances, which are in series with the total resistance of the structure, R T , we include two additional 100 nm long N-type doped regions (5·10 10 cm −2 ) in both source and drain ends [31]. The back gate is grounded and V DS is set to 0.1V. To fit the data presented in [30], the values used are µ =1091 cm 2 /Vs, N p = 8 · 10 11 cm −2 and the graphene layer chemical doping is set to 10 11 cm −2 . The back gate is also grounded and V DS is set to 0.05 V. The experimental and simulated transfer characteristics are shown in Figure 2a  V FG (V) Figure 2. Comparison between the simulation results and the experimental data extracted from [29] (a) and [30] (b).

Access Region Analysis
As mentioned in Section 1, the existence of access regions and puddles is a very common scenario in the experimental realization of GFETs due to the difficulties to precisely control the fabrication process in this early stage of the technology. They modify the behaviour of the transistors, in many cases determining their performance, and therefore deserving a particular attention that is usually obliterated. Hence, once the numerical simulator has been validated, we now proceed to analyse the effect of the access regions.

Including the Access Regions
To begin with, we have considered a test structure where the front gate covers the whole device length (i.e., suppressing the access regions) and compared the results with those obtained later when access regions are included. These scenarios are illustrated in Figure 1 by the dotted and dashed frames respectively. The material stack comprises a monolayer graphene sandwiched between a 3 nm thick HfO 2 layer (front gate insulator) and a 27 nm thick SiO 2 layer (back gate insulator). The front gate, which determines the channel length (L Chn ), is 100 nm long and both access regions are 35 nm long (L Acc ). Electron and hole mobilities are equal (µ = 1500 cm 2 /Vs) and no chemical doping or puddle charge density is considered in the graphene layer.
The transfer characteristic of the device without access regions is depicted in Figure 3a for different values of V DS . As can be observed, the device exhibits the ambipolar V-shaped I − V response of an ideal GFET. The minimum of the I − V curve defines the Dirac voltage (V Dirac ) that is shifted to larger V FG when V DS increases. The behaviour is perfectly symmetric with respect to V Dirac , reflecting the symmetry between electron and hole properties.
Next, the GFET including the access regions is investigated. The resulting transfer characteristic is shown in Figure 3b. Comparing Figure 3b and Figure 3a, a marked variation of the GFET response is observed. First, there is a notable decrease in the values of I DS , around a factor ×100. Second, the transfer characteristic shows a saturation trend for high |V FG | which resembles much better the experimental response. Third, and more important, the I − V characteristic is no longer symmetric with respect to V Dirac , though the mobility is identical for both kinds of carriers.  To provide insights into these changes, the resistance of the different regions of the device are calculated. Figure 4 shows their values for V DS = −0.1 V and V DS = −0.2 V. Mirror symmetric behaviour is observed for positive V DS . The access region resistances, R S,Acc and R D,Acc , show values comparable with the channel resistance, R Chn . At the Dirac voltage, where the channel resistivity is the highest, R Chn commands the series association, but still the access regions have a noticeable contribution. For |V FG − V Dirac | > 0.1 V the total resistance is mainly determined by R S,Acc and R D,Acc . Consequently, the total resistance (R T ) is not controlled just by the channel conductivity and, therefore, by the gate terminal. The weak dependence of R S,Acc and R D,Acc on V FG is reflected in the I DS trend to saturation. As the values of R S,Acc and R D,Acc are higher than the channel resistance, a larger fraction of V DS drops in the access regions. This fact reduces the potential at the channel edges with respect to the no-access-regions scenario, reducing the output current. In addition, the R Acc − V FG dependence is not symmetric, so neither are the access region potential drops, resulting into a non-symmetric reduction of the output current, that is, an asymmetric I DS − V FG curve shown in Figure 3b. This lack of equivalence between the source and drain access regions is explored in detail in the following section.

Gate Misalignment
In the previous section, we assumed that the gate is perfectly aligned in the middle of the channel leading to identical source and drain access regions (L S = L D = L Acc ) at both ends. A more realistic scenario should consider the impact of having non-equal L S and L D , enabling us to test the non-equivalent role of R S,Acc and R D,Acc on the GFET response. For this purpose, we have analysed GFETs where the top gate contact is not placed in the centre of the structure, resulting in access regions of different length. In particular, we have kept L S (or L D ) equal to 35 nm while L D (or L S ) is modified. Specifically, we considered four scenarios: (i) short source, (ii) short drain, (iii) long source and (iv) long drain. The length of the short and long regions is set to 17.5 nm and 70 nm, respectively. The I DS − V FG curves, along with the resistances R S,Acc , R D,Acc and R Chn obtained in each case, are depicted in Figure 5.  As expected, there are significant differences between devices. Shortening either the source or the drain access regions results in a higher output current ( Figure 5a) and reduces both its saturation and its asymmetry with respect to the elongated scenario ( Figure 5b). When comparing the shorter regions ( Figure 5a) it is clearly observable that the L S = 17.5 nm device (solid lines) has a more symmetric response than the L D = 17.5 nm (dashed lines). This is more evident for V DS = 0.1 V and emphasizes the role of the source access region with respect to the drain access region. An equivalent conclusion can be achieved from the elongated devices (Figure 5b). The longer L S results in an increased asymmetry between both branches. These results can be explained by analysing the resistances of the structure. Figure 5c,d show R S,Acc , R D,Acc and R Chn as a function of V FG for V DS = 0.1 V. When any access region is shortened (Figure 5c), its resistance is similar or lower than the channel resistance regardless V FG . The longer region resistance controls the total current (except for V FG close to zero). When one of the regions is enlarged this effect is emphasized. The transfer responses in Figure 5b are clearly saturated due to the dominant role in the total conductivity of the longer access region.

Impact of Electrostatic Doping and Puddles
To reduce the impact of the access regions in the overall device performance, it is possible to increase their conductivity by means of an electrostatic doping using the back-gate terminal. In the following we analyse how the back gate influences the GFET behaviour. Figure 6 shows the transfer characteristic for three different values of V BG : −1 V, 0 V and 1 V (solid lines). For V BG = 0 V the results are quite similar to the scenario without back gate. In the other two cases, depending on the polarity of V BG , electrons or holes are accumulated in the graphene layer. As a result, the P-type (N-type) branch is enhanced for V BG = −1 V (V BG = 1 V), regardless the value of V DS . As in the previous scenario, the origin of this behaviour can be traced back to the resistance associated with the access regions.  . For |V BG | = 1 V the total resistance near the Dirac voltage is dominated by R Chn . When V FG is increased above V Dirac , the symmetry of R Chn is kept since it is mostly controlled by the front gate, while the asymmetry of R S,Acc and R D,Acc is exacerbated due to the electrostatic doping, giving rise to the large asymmetry observed in the transfer response, in Figure 6. In particular, the asymmetric step-like dependence of the access resistances on V FG (for V BG = 0 V) is the result of the electrostatic competition between the front and back gates to control the access regions closer to the channel. When V FG and V BG have the same polarity, they add their electric forces to increase the carrier density in the aforementioned zones, increasing the conductivity and therefore lowering the whole access resistance. However, if V FG is opposite to V BG , both gates compete to accumulate different types of charges, resulting in a depleted region close to the channel edges that decreases the conductivity and increases the overall access region resistances. An equivalent conclusion was achieved in [26] where a strong modulation of the total resistance by two additional gates is observed, as in Figure 7.
An additional aspect that cannot be overlooked is the effect of the presence of puddles in the graphene layer [27,32]. To shed light on this issue Figure 6 includes the I DS − V FG response when a puddle charge density of N p = 10 12 cm −2 is considered (dashed lines). Two major changes are observed after including the puddles: (i) the total current is increased, and (ii) the asymmetry is clearly reduced. These changes derive from the equal contribution of puddles to the conductivity of both electrons and holes, and explain why the I − V curves of some experimental devices are reasonably symmetric close to the Dirac voltage, where the conductivity of puddles is dominant. In this situation, the conductivity of the whole graphene layer is increased for electrons and holes, in contrast with the electrostatic doping generated by the back gate. This non-selective improvement of the conductivity is translated into the resistances of the device: Figure 7 includes the R − V FG relation for N p = 10 12 cm −2 (dashed lines). The step-like behaviour of R S,Acc and R D,Acc is softened when the puddles are included, resembling the V BG = 0 V case.

RF Performance
Finally, to determine the impact of the access regions in the RF performance, we evaluate the cut-off frequency, f T , as a RF figure of merit (FoM). The value of f T is calculated as in [33,34]: where g m is the transconductance and C fg the front gate capacitance. Figure 8 shows f T as a function of V FG under two scenarios: no puddles (solid lines) and N p = 10 12 cm −2 (dash-dotted lines). To assess the impact of the access regions, the performance of the intrinsic device (structure indicated by the dotted rectangle in Figure 1) is depicted too (dashed lines). In addition, to evaluate the magnitude of the calculated values, the experimental measurements of f T reported in [35] and [36] are indicated by the arrows on the right side axis of Figure 8. Despite the device structure and the bias conditions are different, the channel lengths of these experimental devices are similar to the ones simulated here (144 nm [35] and 140 nm [36]), and therefore constitute a good reference. Importantly, a de-embedding procedure was carried out for the RF measurements of these experimental devices by using specific "short" and "open" structures with identical layouts in order to remove the effects of the parasitics associated with the pads and connections, but not the contact and access region resistances.  Including the access regions results in a quite different response compared with the intrinsic device, as the associated parasitic resistances provoke a bias dependent decay of f T . Considering the scenario without puddles, when the back gate is properly biased, f T is considerably improved. If we analyse Figure 8 in combination with Figure 7, those combinations of V FG , V BG for which the R S − V FG (R D − V FG ) curve shows its minimum values, are those for which f T shows a greater improvement. When R S (R D ) is higher, f T is spoiled with respect to the V BG = 0 V case. This relation between the access region conductivity and the improvement of the RF performance was experimentally observed in [21] where a higher f T was demonstrated when a GFET with two additional electrodes was properly biased to control such conductivity. When puddles are included, the channel conductivity increases, what reduces the control of the back-gate bias, and simultaneously results in a more symmetric f T − V FG dependence.

Conclusions
GFETs have been thoroughly studied in order to assess the impact of the access regions in the device performance. The validation of our approach against two experimental devices spotlights the importance of these regions as well as the presence of puddles to reproduce the state-of-the-art technology. When the access regions are considered, the transfer response reveals a lower, saturated and asymmetric I DS − V FG characteristic that is not observed in their absence. To explore the impact of a variable conductivity of these regions we have included a back gate in the structure able to introduce an electrostatic doping. The back gate increases the output current as well as the asymmetry of the transfer characteristic. The latter effect is explained in terms of the competition of the back and front gates that results in a depletion of the amount of carriers close to the channel edges when both biases have an opposite polarity. The influence of puddles is also theoretically investigated, observing that they reduce the asymmetry of I DS − V FG .
The analysis of the impact of the access regions and puddles have been extended to the prediction of the cut-off frequency to assess the properties of GFETs for potential RF applications. Our results reveal an important degradation of the f T − V FG relation due to access regions. The application of an appropriate back gate bias can tune the access region conductivity generating a remarkable improvement in the RF performance. The presence of puddles also mitigates this degradation, but neglects the possibility of tuning the access regions conductivity.