Gate Tunable Transport in Graphene/MoS2/(Cr/Au) Vertical Field-Effect Transistors

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS2/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert) of a Gr/MoS2/(Cr/Au) transistor is compared with planar resistance (Rplanar) of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.


Introduction
Heterostructures [1][2][3] composed of graphene and other two-dimensional (2D) crystals, such as transition metal dichalcogenides (TMDs), are of a great interest due to their fundamental and applied aspects. Extensive research has been carried out in both lateral [4][5][6] and vertical [3,[7][8][9][10][11] hetero-stacks of graphene with other two-dimensional materials. The vertical devices of two-dimensional materials open particularly promising new horizons in material research. For example, graphene vertical field-effect transistors (G-VFETs) are charming candidates for future research, as they have ultimately thin bodies of a few atomic layers, which provide ultrafast transport nearly in a few femtoseconds [12] and higher switching (on/off) ratio as compared to their lateral counterparts.
Thus far, several vertical heterostructures of graphene with other 2D materials have been proposed. For example, Britnell et al. introduced a VFET heterostructure [13] composed of two graphene electrodes and a thin hexagonal boron nitride (h-BN) layer sandwiched between them showing the on/off ratio~50. When h-BN was replaced by MoS 2 , on/off ratio was enhanced to~10 4 due to the low bandgap of MoS 2 as compared to h-BN. It was reported that tunneling transport was dominant in off-state, whereas thermionic transport played a major role in on-state in other previous studies on Gr/TMDs/Gr vertical devices [3]. Another configuration of VFETs has been investigated in which one side of TMDs was contacted with a graphene electrode, while the other was contacted with a metal electrode [7,[14][15][16][17][18][19][20][21]. In this kind of devices (Gr/TMDs/Metal), Schottky barriers at the interface between graphene and TMDs play an important role in the electrical transport. Electric field from the back-gate can modify the Schottky barrier height. These devices are superior to tunneling devices due to a large current density through the semiconducting TMDs channel [22][23][24]. Gr/TMDs/Metal devices showed a high on/off ratio and low driving voltage; therefore, they are good to use in low power consumption applications.
In previous reports, most VFETs were studied by employing the two-probe measurement configuration, which included contact electrodes as a part of the devices. This configuration always possesses contact resistance due to which intrinsic characteristics of the device were impossible to achieve. In the present paper, we have fabricated Gr/MoS 2 /(Cr/Au) VFET with various MoS 2 thickness. However, we use four-probe cross-bar geometry in this experiment to exclude contribution of electrode to the measurement. Monolayer Gr used as a bottom electrode allows back-gate electric field to tune the energy states of MoS 2 in VFET. Therefore, we could investigate the gate-dependent electrical transport in our MoS 2 VFET. Moreover, graphene contacts [25][26][27][28] can effectively decrease contact resistance because of small work function mismatch between graphene and MoS 2 . We have also measured planar transport properties of lateral MoS 2 field-effect transistors for comparison. Electronic transports in the vertical and lateral direction were discussed by analyzing the resistance components.

Device Fabrication
Our Gr/MoS 2 /(Cr/Au) VFETs were fabricated on SiO 2 /P + -Si substrate. The thickness of dielectric (SiO 2 ) was 300 nm, whereas P + -Si was used to apply back-gate voltage. In the first process, chemical vapor deposition (CVD) grown graphene was transferred on SiO 2 /Si substrate using wet transfer method [29], and a graphene Hall bar pattern was defined by using photo-lithography. Then oxygen plasma (power~50 W) was used for several minutes to etch extraneous graphene. The Raman spectrum for Gr is shown in Supplementary Materials Figure S1 (see Supplementary Materials). In Raman spectrum, 2D to G peak intensity ratio is larger than 3:1, indicating monolayer characteristics of Gr [30]. We used the scotch-tape method for mechanical exfoliation of MoS 2 [17,[31][32][33][34][35][36][37][38][39][40][41][42][43][44][45]. The suitable MoS 2 flake was selected under an optical microscope and then transferred on graphene Hall bar by using micromanipulator. Subsequently, 15-nm-thick HfO 2 films was grown by atomic layer deposition on the e-beam lithography defined area. In the last process, e-beam lithography was done to define the top electrode of Cr/Au (8/120 nm).

Measurements
Electrical measurements were performed by using Keithley 2400 source meter, Keithley 6485K picoammeter, and Keithley 2182A nanovoltmeter. All measurements were performed in vacuum at room temperature. Structural investigation and material identification were performed using Raman spectroscopy and atomic force microscopy (AFM). In Raman spectroscopy, laser wavelength of 514 nm with power below 1 mW was selected to avoid structural degradation caused by the heating effects of the laser. The nominal diameter of laser spot was 0.7 µm.

Gr/MoS 2 /(Cr/Au) Vertical Field-Effect Transistor
A schematic representation of Gr/MoS 2 /(Cr/Au) VFET is shown in Figure 1a, where the back-gate voltage is applied to control the vertical transport in MoS 2 channel. The optical micrograph of device is shown in Figure 1b. Graphene is represented by the purple color, MoS 2 by the sky blue, and HfO 2 (~15 nm thick) window by the dark blue color. We choose CVD-grown monolayer graphene despite multilayer graphene. We believe that, in case of multilayer graphene, the gate effect would be small as compared to monolayer graphene due to back-gate electric field screening, and modulation in Schottky barrier height will be more difficult as compared to monolayer graphene. HfO2 (~15 nm thick) window by the dark blue color. We choose CVD-grown monolayer graphene despite multilayer graphene. We believe that, in case of multilayer graphene, the gate effect would be small as compared to monolayer graphene due to back-gate electric field screening, and modulation in Schottky barrier height will be more difficult as compared to monolayer graphene. The alphabetic and numeric symbols indicate different contacts used for the planar and vertical transport measurement. Figure 1c shows AFM of MoS2 film, which reveals uniform surface morphology. Height profile taken by AFM shows the thickness of MoS2 to be ~44 nm in Figure 1d.
Raman spectroscopy of MoS2 on monolayer Gr was studied in comparison with MoS2 on Si/SiO2 substrate shown in Supplementary Materials Figure S2. Raman spectrum for MoS2 on Si/SiO2 substrate was represented by the black color, whereas the red color shows Raman spectrum of MoS2 on Gr. Two prominent peaks of MoS2 appeared in the wavenumber range from 380 to 420 cm −1 . These two Raman peaks belongs to in-plane (E 2g 1 ) and out of plane (A1g) vibrations of "Mo" and "S" atoms [46]. The difference between E 2g 1 and A1g Raman peaks for MoS2 on Si/SiO2 substrate amounted to Δ ≈ 24 cm −1 , indicating a multilayer nature [22]. There was a slight change in peak positions of MoS2 when stacked on Gr. This slight change was due to the relaxation of atoms on different substrate. We assume that vertical resistance (Rvert) is a cumulative effect of all the resistances including contact resistance and MoS2 channel resistance. We made a cross-junction geometry to investigate the vertical transport in Gr/MoS2/(Cr/Au). The measurements consisted of four-probe technique where two contacts were used as source and drain, while the other two for voltage measurement across VFET. Figure 1b shows the measurement configuration (I + , I − , V + , V − ) for the vertical resistance Rvert. The alphabetic and numeric symbols indicate different contacts used for the planar and vertical transport measurement. Figure 1c shows AFM of MoS 2 film, which reveals uniform surface morphology. Height profile taken by AFM shows the thickness of MoS 2 to be~44 nm in Figure 1d.
Raman spectroscopy of MoS 2 on monolayer Gr was studied in comparison with MoS 2 on Si/SiO 2 substrate shown in Supplementary Materials Figure S2. Raman spectrum for MoS 2 on Si/SiO 2 substrate was represented by the black color, whereas the red color shows Raman spectrum of MoS 2 on Gr. Two prominent peaks of MoS 2 appeared in the wavenumber range from 380 to 420 cm −1 . These two Raman peaks belongs to in-plane (E 1 2g ) and out of plane (A 1g ) vibrations of "Mo" and "S" atoms [46]. The difference between E 1 2g and A 1g Raman peaks for MoS 2 on Si/SiO 2 substrate amounted to ∆ ≈ 24 cm −1 , indicating a multilayer nature [22]. There was a slight change in peak positions of MoS 2 when stacked on Gr. This slight change was due to the relaxation of atoms on different substrate.
We assume that vertical resistance (R vert ) is a cumulative effect of all the resistances including contact resistance and MoS 2 channel resistance. We made a cross-junction geometry to investigate the vertical transport in Gr/MoS 2 /(Cr/Au). The measurements consisted of four-probe technique where two contacts were used as source and drain, while the other two for voltage measurement across VFET. Figure 1b shows the measurement configuration (I + , I − , V + , V − ) for the vertical resistance R vert .
We also measured planar resistance R planar of the same MoS 2 film using Cr/Au contacts as illustrated by numeric symbols 1, 2, 3, 4 in Figure 1b. Figure 2a shows a schematic diagram of Gr/MoS 2 /(Cr/Au) VFET, where R int and R c represent interlayer resistance between stacked layer of MoS 2 and contact resistance, respectively. Figure 2b represents vertical resistance (R vert ) of Gr/MoS 2 /(Cr/Au) VFET as a function of the back-gate voltage (V bg ). In this experiment, the current flows from Gr to the top Cr/Au contact through semiconducting MoS 2 channel. The electrical characteristics are strongly modified by V bg . To understand the physics of the transport mechanism, there are lot of factors that should be keep in mind e.g., Schottky barrier height, barrier width etc. It is a well-known concept that electrical transport in TMD's based field effect transistors (FET) is governed by either tunneling or thermionic emission. Tunneling is due to passing of carriers through barrier height and is a temperature-independent quantity. However, thermionic emission is highly reliant on temperature. Tunneling current depends upon barrier width, and if the barrier width is too large, we cannot observe tunneling current. Here, our average MoS 2 thickness is 50 nm (barrier width~50 nm). Usually, to observe tunneling mechanism, the barrier width should be ≤5 nm [47]. So, we can firmly say that in our experiment, electrical transport is not caused by tunneling. However, the low value of current observed at V bg < 0 in our Gr/MoS 2 heterostructure's transport property (shown in Supplementary Materials Figure S3c) is due to gate leakage current and not by the tunneling that is a very well-known phenomenon in Si-based field effect transistors. The Gr/MoS 2 junction is completely in off state at low V bg due to the presence of large Schottky barrier height (SBH), which is why we observed large resistance at that point. We also measured planar resistance Rplanar of the same MoS2 film using Cr/Au contacts as illustrated by numeric symbols 1, 2, 3, 4 in Figure 1b. Figure 2a shows a schematic diagram of Gr/MoS2/(Cr/Au) VFET, where Rint and Rc represent interlayer resistance between stacked layer of MoS2 and contact resistance, respectively. Figure 2b represents vertical resistance (Rvert) of Gr/MoS2/(Cr/Au) VFET as a function of the back-gate voltage (Vbg). In this experiment, the current flows from Gr to the top Cr/Au contact through semiconducting MoS2 channel. The electrical characteristics are strongly modified by Vbg. To understand the physics of the transport mechanism, there are lot of factors that should be keep in mind e.g., Schottky barrier height, barrier width etc. It is a well-known concept that electrical transport in TMD's based field effect transistors (FET) is governed by either tunneling or thermionic emission. Tunneling is due to passing of carriers through barrier height and is a temperature-independent quantity. However, thermionic emission is highly reliant on temperature. Tunneling current depends upon barrier width, and if the barrier width is too large, we cannot observe tunneling current. Here, our average MoS2 thickness is 50 nm (barrier width~50 nm). Usually, to observe tunneling mechanism, the barrier width should be ≤5 nm [47]. So, we can firmly say that in our experiment, electrical transport is not caused by tunneling. However, the low value of current observed at Vbg < 0 in our Gr/MoS2 heterostructure's transport property (shown in Supplementary Materials Figure S3c) is due to gate leakage current and not by the tunneling that is a very well-known phenomenon in Si-based field effect transistors. The Gr/MoS2 junction is completely in off state at low Vbg due to the presence of large Schottky barrier height (SBH), which is why we observed large resistance at that point.  On the other hand, Deshun Qu et al. reported that "S" vacancies in MoS 2 play an important role in r int [48]. The importance of "S" atoms was further elaborated for the vertical carrier transport by orbital overlapping between "S" atoms in adjacent layers [49,50].

Resistance Analysis of Gr/MoS 2 /(Cr/Au) VFET
R vert in the measurement configuration of Figure 2a can be considered as the sum of interface resistance between Gr and MoS 2 (R Gr/MoS 2 ), total channel resistance of individual layers of MoS 2 (R TCR-V ), interlayer resistance (R int ) of MoS 2 , and interface resistance (R SBH ) between Cr/Au electrode and MoS 2 . So, the vertical resistance (R vert ) is given by Equation (1).
where total interlayer resistance (R int ) is given by R int = Nr int , where N is the total number of layers in MoS 2 and r int is the interlayer resistance between two consecutive layers of MoS 2 . As the thickness of MoS 2 increases, R int increases, and then R vert increases as well. In the vertical transport, r int is a non-negligible quantity in the thick MoS 2 channel. Another important factor that should be elaborated here is the channel resistance itself. In the vertical transport, R TCR-V increases with an increase of the thickness of MoS 2 channel. Since both R int and R TCR-V increase with increasing MoS 2 thickness, R vert shows the dependence of MoS 2 thickness. However, the resistance of planar or vertical device depends on cross-sectional area, so it is better to examine resistivity instead of resistance. Figure 2d shows ρ planar and ρ vert as a function of MoS 2 thickness. As another important component of R vert , we discuss R Gr/MoS 2 which is the interface resistance between Gr and MoS 2 . We analyze R Gr/MoS 2 within 2D thermionic emission theory, where the Schottky barrier height is given by Equation (2).
where k B is the Boltzmann's constant, A* is effective Richardson constant and we choose A* = 54 Acm −2 K −2 for MoS 2 [51]. We extracted Schottky barrier height at T = 300 K from I ds -V ds curves shown in Supplementary Materials Figure S3. J rev (=I ds /A junc ) is the reverse saturation current density at V ds = −0.5 V, where we see a beginning of saturation of I ds . A junc (=200 µm 2 ) is the junction area of Gr/MoS 2 . Barrier height decreases with an increase of V ds or V bg (see Figure 3a,b). Φ B ranges from 1.10 to 0.78 eV for the interface between monolayer Gr and 53-nm-thick ML-MoS 2 . On the other hand, Deshun Qu et al. reported that "S" vacancies in MoS2 play an important role in rint [48]. The importance of "S" atoms was further elaborated for the vertical carrier transport by orbital overlapping between "S" atoms in adjacent layers [49,50].

Resistance Analysis of Gr/MoS2/(Cr/Au) VFET
Rvert in the measurement configuration of Figure 2a can be considered as the sum of interface resistance between Gr and MoS2 (R Gr MoS 2 ⁄ ), total channel resistance of individual layers of MoS2 (RTCR-V), interlayer resistance (Rint) of MoS2, and interface resistance (RSBH) between Cr/Au electrode and MoS2. So, the vertical resistance (Rvert) is given by Equation (1).
where total interlayer resistance (Rint) is given by R int = Nr int , where N is the total number of layers in MoS2 and rint is the interlayer resistance between two consecutive layers of MoS2. As the thickness of MoS2 increases, Rint increases, and then Rvert increases as well. In the vertical transport, rint is a nonnegligible quantity in the thick MoS2 channel. Another important factor that should be elaborated here is the channel resistance itself. In the vertical transport, RTCR-V increases with an increase of the thickness of MoS2 channel. Since both Rint and RTCR-V increase with increasing MoS2 thickness, Rvert shows the dependence of MoS2 thickness. However, the resistance of planar or vertical device depends on cross-sectional area, so it is better to examine resistivity instead of resistance. Figure 2d shows ρ and ρ as a function of MoS2 thickness. As another important component of Rvert, we discuss R Gr MoS 2 ⁄ which is the interface resistance between Gr and MoS2. We analyze R Gr MoS 2 ⁄ within 2D thermionic emission theory, where the Schottky barrier height is given by Equation (2).
where k B is the Boltzmann's constant, A* is effective Richardson constant and we choose A* = 54 Acm −2 K −2 for MoS2 [51]. We extracted Schottky barrier height at T = 300 K from Ids-Vds curves shown in Supplementary Materials Figure S3. Jrev (=Ids/Ajunc) is the reverse saturation current density at Vds = −0.5 V, where we see a beginning of saturation of Ids. Ajunc (=200 µm 2 ) is the junction area of Gr/MoS2. Barrier height decreases with an increase of Vds or Vbg (see Figure 3a,b). Φ B ranges from 1.10 to 0.78 eV for the interface between monolayer Gr and 53-nm-thick ML-MoS2. Moreover, planar resistance (R planar ) of the MoS 2 channel was measured by using the electrodes labelled as numeric letters in Figure 1b. While current was applied between 1 and 2, voltage was measured between 3 and 4. Figure 2c shows R planar as a function of V bg . As V bg increases from −30 to 40 V, R planar rapidly decreases, indicating MoS 2 is a n-type semiconductor. The MoS 2 channel thickness dependence of R planar at V bg = −10 V is shown in Figure 2d. As MoS 2 flake thickness increases, R planar decreases in contrast to R vert. We can analyze R planar as R TCR-P in 4-probe measurement configuration. Here, R TCR-P represents the in-plane resistance of MoS 2 . As the thickness of MoS 2 channel increases, more layers can contribute to the planar electrical transport, so that total planer channel resistance, R TCR-P decreases. To have an estimate of contact resistivity, we employed transmission line method (TLM) on 51 nm-thick MoS 2 flake and extracted contact resistivity to be 0.14 MΩ µm at V bg = −10 V as shown in Supplementary Materials Figure S4b. The contact resistivity is smaller than the planar resistivity of MoS 2 channel itself. So, it is obvious that there are other factors contributing to the total in-plane resistance other than contacts. The back-gate voltage-dependent contact resistivity was also estimated using TLM method as shown in Supplementary Materials Figure S4d. The contact resistivity decreases with V bg and has a low value in the positive region of V bg due to the increasing carrier channels.
In lateral devices, the source and drain contacts are directly attached to top surface of MoS 2 . Therefore, the charge carriers will flow from source to drain mainly through a few top layers of MoS 2 due to the interlayer resistance [52,53]. Moreover, since the thickness of MoS 2 flake in the lateral device is~50 nm (about 76 layers), the back-gate electric field will not affect much on the charge carrier transport. This could be the reason of a low R planer for thick MoS 2 channel in the lateral devices.

Vertical Transport of (Cr/Au)/Mos 2 /(Cr/Au) Vertical Field-Effect Transistor
We have studied vertical transport in (Cr/Au)/MoS 2 /(Cr/Au) VFET, the schematic representation of which is shown in Figure 4a, and inset of Figure 4b shows the scanning electron microscope image. The thickness of MoS 2 is about 48 nm. While current bias is applied between 4 and 3, voltage is measured between 2 and 1. Figure 4b shows R vert as a function of V bg at room temperature. It shows similar characteristics as Gr/MoS 2 /(Cr/Au) VFET, but with a low R vert , which may be due to the low interface resistance between Cr/Au and MoS 2 . The strong screening of electric field by the bottom Cr/Au electrode creates a weaker dependence on V bg . The I-V characteristics show almost ohmic behavior at different back-gate voltages (see Figure 4c).  Figure 2c shows Rplanar as a function of Vbg. As Vbg increases from −30 to 40 V, Rplanar rapidly decreases, indicating MoS2 is a n-type semiconductor. The MoS2 channel thickness dependence of Rplanar at Vbg = −10 V is shown in Figure 2d. As MoS2 flake thickness increases, Rplanar decreases in contrast to Rvert. We can analyze Rplanar as RTCR-P in 4-probe measurement configuration.
Here, RTCR-P represents the in-plane resistance of MoS2. As the thickness of MoS2 channel increases, more layers can contribute to the planar electrical transport, so that total planer channel resistance, RTCR-P decreases. To have an estimate of contact resistivity, we employed transmission line method (TLM) on 51 nm-thick MoS2 flake and extracted contact resistivity to be 0.14 MΩ µm at Vbg = −10 V as shown in Supplementary Materials Figure S4b. The contact resistivity is smaller than the planar resistivity of MoS2 channel itself. So, it is obvious that there are other factors contributing to the total in-plane resistance other than contacts. The back-gate voltage-dependent contact resistivity was also estimated using TLM method as shown in Supplementary Materials Figure S4d. The contact resistivity decreases with Vbg and has a low value in the positive region of Vbg due to the increasing carrier channels.
In lateral devices, the source and drain contacts are directly attached to top surface of MoS2. Therefore, the charge carriers will flow from source to drain mainly through a few top layers of MoS2 due to the interlayer resistance [52,53]. Moreover, since the thickness of MoS2 flake in the lateral device is ~50 nm (about 76 layers), the back-gate electric field will not affect much on the charge carrier transport. This could be the reason of a low Rplaner for thick MoS2 channel in the lateral devices.

Vertical Transport of (Cr/Au)/Mos2/(Cr/Au) Vertical Field-Effect Transistor
We have studied vertical transport in (Cr/Au)/MoS2/(Cr/Au) VFET, the schematic representation of which is shown in Figure 4a, and inset of Figure 4b shows the scanning electron microscope image. The thickness of MoS2 is about 48 nm. While current bias is applied between 4 and 3, voltage is measured between 2 and 1. Figure 4b shows Rvert as a function of Vbg at room temperature. It shows similar characteristics as Gr/MoS2/(Cr/Au) VFET, but with a low Rvert, which may be due to the low interface resistance between Cr/Au and MoS2. The strong screening of electric field by the bottom Cr/Au electrode creates a weaker dependence on Vbg. The I-V characteristics show almost ohmic behavior at different back-gate voltages (see Figure 4c).  Although Rvert of (Cr/Au)/MoS2/(Cr/Au) VFET in Figure 4(b) decreases as Vbg is increased, the relative change of Rvert is rather small. To compare the relative change of Rvert we obtain Rvert/R0 as a function of Vbg, where R0 at Vbg = −10 V is taken as a reference resistance. Figure 5a shows Rvert/R0 as a function of Vbg for Gr/MoS2/(Cr/Au) and (Cr/Au)/MoS2/(Cr/Au) VFETs. The thickness of MoS2 is 50 nm and 48 nm for Gr/MoS2/(Cr/Au) and (Cr/Au)/MoS2/(Cr/Au) VFETs, respectively. Of note, Vbg does not significantly affect transport characteristics in (Cr/Au)/MoS2/(Cr/Au) VFET, because the bottom Cr/Au electrode effectively screens the electric field from the Vbg application. However, Rvert/R0 has a strong dependence on Vbg in Gr/MoS2/(Cr/Au) devices, due to the weak screening of the electric field by bottom monolayer Gr. For comparison, we also present Rplanar/R0 as a function of Vbg in Figure 5b. A rapid increase of Rplanar/R0 below Vbg = −30 V indicates the threshold voltage of n-type MoS2 channel in our devices. The dependence of Rplanar/R0 on Vbg is much larger than VFETs, asMoS2 channel is directly affected by Vbg application in ordinary planar geometry.
In the positive region of Vbg, both resistances in planar (in-plane) and vertical configuration show a similar dependence of Vbg. However, at negative Vbg, we find different dependences of Vbg as seen in Figure 5a,b. In Figure 5a Rvert/R0 shows an exponential dependence of Vbg for Gr/MoS2/(Cr/Au) VFET with 50 nm-thick MoS2 flake. This might be due to the gate-voltage dependent density of states in graphene, which affects the interface resistance between graphene and MoS2. In case of (Cr/Au)/MoS2/(Cr/Au) VFET with 50 nm-thick MoS2, there exists large screening effect by the bottom Cr/Au electrode that does not allow the back-gate electric field to influence on the electronic transport. On the other hand, in case of planar 48 nm-thick MoS2 FET of Figure 5b, we have source/drain (Cr/Au) electrodes directly on the lateral channel of MoS2. At a particular negative Vbg, the channel transport is in off-state, so resistance increases rapidly at Vbg below the threshold voltage. Although R vert of (Cr/Au)/MoS 2 /(Cr/Au) VFET in Figure 4b decreases as V bg is increased, the relative change of R vert is rather small. To compare the relative change of R vert we obtain R vert /R 0 as a function of V bg , where R 0 at V bg = −10 V is taken as a reference resistance. Figure 5a shows R vert /R 0 as a function of V bg for Gr/MoS 2 /(Cr/Au) and (Cr/Au)/MoS 2 /(Cr/Au) VFETs. The thickness of MoS 2 is 50 nm and 48 nm for Gr/MoS 2 /(Cr/Au) and (Cr/Au)/MoS 2 /(Cr/Au) VFETs, respectively. Of note, V bg does not significantly affect transport characteristics in (Cr/Au)/MoS 2 /(Cr/Au) VFET, because the bottom Cr/Au electrode effectively screens the electric field from the V bg application. However, R vert /R 0 has a strong dependence on V bg in Gr/MoS 2 /(Cr/Au) devices, due to the weak screening of the electric field by bottom monolayer Gr. For comparison, we also present R planar /R 0 as a function of V bg in Figure 5b. A rapid increase of R planar /R 0 below V bg = −30 V indicates the threshold voltage of n-type MoS 2 channel in our devices. The dependence of R planar /R 0 on V bg is much larger than VFETs, asMoS 2 channel is directly affected by V bg application in ordinary planar geometry.
In the positive region of V bg , both resistances in planar (in-plane) and vertical configuration show a similar dependence of V bg . However, at negative V bg , we find different dependences of V bg as seen in Figure 5a,b. In Figure 5a R vert /R 0 shows an exponential dependence of V bg for Gr/MoS 2 /(Cr/Au) VFET with 50 nm-thick MoS 2 flake. This might be due to the gate-voltage dependent density of states in graphene, which affects the interface resistance between graphene and MoS 2 . In case of (Cr/Au)/MoS 2 /(Cr/Au) VFET with 50 nm-thick MoS 2 , there exists large screening effect by the bottom Cr/Au electrode that does not allow the back-gate electric field to influence on the electronic transport. On the other hand, in case of planar 48 nm-thick MoS 2 FET of Figure 5b, we have source/drain (Cr/Au) electrodes directly on the lateral channel of MoS 2 . At a particular negative V bg , the channel transport is in off-state, so resistance increases rapidly at V bg below the threshold voltage.

Conclusions
In the present study, we performed four probe measurements using cross-junction geometry of Gr/MoS2/(Cr/Au) VFETs. We were able to achieve gate-tunable transport characteristics in VFETs. Since the bottom Gr allows the electric field to reach MoS2 channel, the vertical resistance (Rvert) of Gr/MoS2/(Cr/Au) VFET can be effectively modified by Vbg. The vertical transport characteristics are examined as compared to those of the ordinary lateral MoS2 field-effect transistor. Rvert increases as the thickness of MoS2 increases, whereas Rplanar decreases. The increase of Rvert in the thicker MoS2 film can be attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of excess of charge carriers available in upper layers connected directly to source/drain contacts and cumulative contribution of low Rint from the lower layers. In planer geometry only, layers attached near to channel layer (on which source/drain electrodes are constructed) are the main source of the conduction mechanism. Schottky barrier height at Gr/MoS2 interface can be analyzed from the Ids-Vds curve. The Schottky barrier height decreases as Vbg or Vds increases. Vbg does not affect transport characteristics much in (Cr/Au)/MoS2/(Cr/Au) VFET, because the bottom Cr/Au electrode effectively screens the electric field from the Vbg application. However, a strong dependence on Vbg in Gr/MoS2/(Cr/Au) devices was observed due to the weak screening of electric field by bottom Gr. We believe that gate tunable VFET will serve as one of important components for future 2D materials electronics.

Conclusions
In the present study, we performed four probe measurements using cross-junction geometry of Gr/MoS 2 /(Cr/Au) VFETs. We were able to achieve gate-tunable transport characteristics in VFETs. Since the bottom Gr allows the electric field to reach MoS 2 channel, the vertical resistance (R vert ) of Gr/MoS 2 /(Cr/Au) VFET can be effectively modified by V bg . The vertical transport characteristics are examined as compared to those of the ordinary lateral MoS 2 field-effect transistor. R vert increases as the thickness of MoS 2 increases, whereas R planar decreases. The increase of R vert in the thicker MoS 2 film can be attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS 2 film because of excess of charge carriers available in upper layers connected directly to source/drain contacts and cumulative contribution of low R int from the lower layers. In planer geometry only, layers attached near to channel layer (on which source/drain electrodes are constructed) are the main source of the conduction mechanism. Schottky barrier height at Gr/MoS 2 interface can be analyzed from the I ds -V ds curve. The Schottky barrier height decreases as V bg or V ds increases. V bg does not affect transport characteristics much in (Cr/Au)/MoS 2 /(Cr/Au) VFET, because the bottom Cr/Au electrode effectively screens the electric field from the V bg application. However, a strong dependence on V bg in Gr/MoS 2 /(Cr/Au) devices was observed due to the weak screening of electric field by bottom Gr. We believe that gate tunable VFET will serve as one of important components for future 2D materials electronics.