Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs

Abstract

Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore’s Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels. In this work, we overcome this long-standing bottleneck by introducing a co-design strategy that integrates a small-diameter HiPco CNT channel with a novel asymmetric gate architecture. This approach strategically reshapes the channel electrostatics to simultaneously suppress the gate-induced drain leakage (GIDL) effect and preserve excellent carrier transport. The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating an ultralow off-current of 10 fA/µm, an on-current of 1.08 mA/µm, and a record on–off ratio of 1.1 × 10¹¹ for back-gated CNTFETs at the 90 nm node. The design exhibits outstanding scalability: at the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device achieves 3 mA/µm on-current and 6 pA/µm off-current, maintaining an on–off ratio of 5 × 10⁸. This work establishes a scalable pathway toward femtoampere-level CNT CMOS, addressing the static power challenge in future nano-electronics.

1. Introduction

The relentless pursuit of Moore’s Law has driven the search for semiconductor materials that can sustain device scaling beyond silicon’s limits. Among these, semiconducting carbon nanotubes (CNTs) stand out due to their exceptional carrier mobility and near-ballistic transport, enabling field-effect transistors (FETs) with superior electrostatic control and high drive currents at aggressively scaled nodes [1,2,3,4,5,6,7,8,9,10,11]. This has led to the experimental demonstration of high-performance CNT FETs with gate lengths as short as 5 nm, validating their potential for ultimately scaled electronics [11].

Current state-of-the-art CNTFETs mainly employ single-walled carbon nanotubes (SWCNTs) with a bandgap E_g ≤ 0.6 eV. While these devices often report excellent on-state currents exceeding 1 mA/µm at a drain-source bias of −0.5 V, the corresponding off-state leakage is rarely mentioned. Narrow-bandgap CNT FETs typically present off-state currents above 100 nA/µm, significantly exceeding the sub-10 nA/µm benchmark of modern silicon technology [12,13,14,15,16,17]. Importantly, when the operating voltage rises above 1.0 V, this leakage grows sharply. The behavior is dominated by the combined effects of band-to-band tunneling (BTBT) and Schottky-barrier tunneling at the metal-CNT contacts [18,19]. These two tunneling mechanisms create a double-barrier effect, which makes off-state leakage difficult to control. This poses a significant challenge for practical implementation and energy-efficient digital integration.

Researchers face several technical challenges in tackling the issue of leakage current. Firstly, doping-based electrostatic control is unviable, as the LDD approach—essential in silicon—is precluded by the doping-resistant sp² lattice of CNTs. Secondly, L-shaped contact or multi-gate designs can modulate the leakage, their structural complexity introduces severe integration challenges, parasitic penalties, and ultimately a hard scalability barrier below 50 nm [20,21]. Thirdly, the tunneling suppression achieved by using small-diameter CNTs comes at the cost of a widened bandgap, which reduces the density of states and carrier injection efficiency, potentially limiting the maximum on-current [22]. Consequently, achieving ultralow off-state currents while maintaining a steep subthreshold swing (SS < 60 mV/dec) remains a central challenge.

To break this fundamental limitation, we introduce a co-design strategy that integrates a high-purity, small-diameter HiPco CNT channel with a novel asymmetric gate architecture. In contrast to conventional approaches that rely on drain engineering or feedback-gate structures to suppress short-channel effects via drain-side electrostatic modulation, this proposed strategy is dominated by source-side barrier control. By enhancing the electrostatic coupling between the gate and the source, the source-side gate control capability is strengthened. As a result, the barrier height in the off state becomes more stable. Meanwhile, the influence of the drain electric field on the barrier is significantly weakened. This attenuation suppresses thermionic emission and diminishes drain-induced barrier lowering (DIBL). The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating breakthrough performance. At the 90 nm node, the proposed device achieves an ultralow off-state current of 10 fA/µm, a high on-state current of 1.08 mA/µm, and a record on–off ratio of 1.1 × 10¹¹. Furthermore, the design exhibits outstanding scalability. At the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device delivers an on-current of 3 mA/µm and an off-current of 6 pA/µm, maintaining an on–off ratio of 5 × 10⁸. The NMOS exhibits the same performance, demonstrating excellent symmetry with the PMOS. This work provides a critical solution to the static power challenge.

2. Experiment

To validate our simulation framework, we fabricate top-gated p-type CNT FETs with a 90 nm gate length. Figure 1c shows a cross-sectional high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) image of the device structure. We employ high-purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a relatively large bandgap of 0.71~0.85 eV, derived from HiPco CNTs (small-diameter: 1.0–1.2 nm), as shown in Figure 1a [23]. The CNT spectral plot is shown in Figure 1b. The channel is formed by a network of HiPco CNTs with a density of approximately 30 CNTs/µm. Palladium (Pd) source/drain contacts are placed 50 nm from the gate edge. The gate stack consisted of a TiN with a 4 nm HfO₂/2 nm AlON dielectric bilayer, where AlON served as a passivation layer. Figure 1d displays the cross-sectional bright-field (BF) TEM microstructure of the gate stack. The detailed preparation process is provided in the Appendix A.

The measured transfer characteristics of the fabricated devices are shown in Figure 2a. Compared with a narrow-bandgap (~0.56 eV) CNT device shown in Figure 2b [24], the HiPCo CNT PMOS exhibits nearly two orders of magnitude lower off-state while delivering a high on-state current of ~200 µA/µm at V_DS = −1.5 V. The off-state leakage remains below 1 nA/µm with week dependence on V_DS, indicating effective suppression of the gate-induced drain leakage (GIDL). These experimental results confirm the advantage of using small-diameter semiconducting CNTs for low-leakage transistor applications.

3. Results and Discussion

3.1. Simulation Methodology

Our physical models and parameters were calibrated against the experimental data of the fabricated device (Figure 1c). All simulations were performed using the two-dimensional (2D) Sentaurus TCAD platform. Carrier transport in the CNT channel was modeled using the classical drift–diffusion (DD) framework. To account for off-state leakage at the drain side, a nonlocal band-to-band tunneling (BTBT) model was employed along the transport direction. Carrier mobility in the CNT channel was modeled using the Sentaurus Mobility module, which includes field-dependent mobility (Enormal), high-field velocity saturation, the Caughey–Thomas low-to-high-field transition, and quasi-Fermi gradient effects [25]:

$${\mu }_{n,p}={\mu }_{low}{\left[{\displaystyle \frac{1}{1+{\left(\frac{{\mu }_{low}}{v_{sat n,p}}E\right)}^{\beta }}}\right]}^{\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$\beta $}\right.}$$

(1)

where ${\mu }_{low}$ denotes the low-field electron (hole) mobility. E is the parallel electric field. v_{sat n,p} represents the electron (hole) saturation velocity in high fields, and β is a fitting parameter. This formulation accounts for both low-field and high-field transport while incorporating the influence of carrier density variations. Carrier injection at the source and drain contacts was treated using a semiclassical tunneling model based on the WKB approximation, which captures both thermionic emission and tunneling transport across the metal–CNT interfaces. The effect of interface trap states at the gate dielectric interface was included using an interface trap model. The carrier concentration in semiconducting HiPico CNTs was calculated under nondegenerate conditions using a one-dimensional density-of-states model that accounts for the Van Hove singularities at the band edges. The effective density of states is expressed as [26,27]:

$$N_C\approx {\displaystyle \frac{g_0}{4}}\sqrt{\pi kT{E}_g}$$

(2)

where $g_0={2 \mathrm{n}\mathrm{m}}^{-1}{\mathrm{e}\mathrm{V}}^{-1}$ is the CNT material constant, k is the Boltzmann constant, T is the temperature, and E_g is the CNT bandgap. The carrier concentration is then given by Equation (3). The effective mass m* of the CNT is taken as Equation (4) [26,27].

$$n=2N_{c}exp\left({\displaystyle \frac{E_F-E_C}{kT}}\right)$$

(3)

$$m^{*}={\displaystyle \frac{{4\hslash }^2{E}_g}{3\gamma a^2\left(2\gamma +E_g\right)}}$$

(4)

where γ = 3.1 eV is the nearest-neighbor overlap energy. $\hslash$ is the reduced Planck’s constant and a = 2.46 Å is the lattice constant.

Using the above physical models and parameters (

Table 1. Parameters used for model calibration.

Parameter	HiPco CNT PFET
Gate length (Lg)	90 nm
Gate oxide thickness (Tox)	6 nm
Diameter (dCNT)	1.15 nm
Bandgap (Eg)	0.74 eV
Affinity (eV)	4.1 eV
Effective mass (m*)	0.06 m0
Mobility of channel (μ0)	$1\times {10}^4$ cm2/($\mathrm{V}\cdot \mathrm{s}$)
Effective density of states (Nc)	$0.24\times {10}^5$ cm−1
Saturation velocity (vsat)	$1.1\times {10}^7$ cm/s
Contact work function (${\varphi }_{\mathrm{m}}$)	5.1 eV
Gate work function (${\varphi }_G$)	5.1 eV

), we constructed a TCAD device model. The model is calibrated using the 90 nm top-gate CNT-FET measurements (Figure 2a), the simulated results show excellent agreement with experiments, as shown in Figure 3a, validating the model’s accuracy. The calibration primarily targets intrinsic CNT transport and metal–CNT contact physics, which are material-dependent and therefore transferable across different device geometries and stack configurations. Leveraging this model, we explored the design space of 130 nm back-gated CNT PMOS devices shown in Figure 3b. The source/drain contacts are defined with Pd, while the gate control was achieved with an HfO₂ dielectric, and the device stability was ensured by an AlON passivation layer.

We conducted a systematic investigation into the geometric determinants of off-state leakage, aiming to establish clear guidelines for optimizing CNT FET performance. Adjusting the Gate-to-Drain (L_GD) and Gate-to-Source (L_GS) spacing provides an effective means to mitigate off-state leakage by modulating electric field distributions. Increasing L_GD under a fixed L_GS of 50 nm introduces an extended electric field buffer region. This buffer attenuates the drain-field penetration into the gated channel, thereby significantly weakening the drain-induced barrier lowering (DIBL) effect and suppressing the associated tunneling current. Quantitatively, extending L_GD to 125 nm reduces the off-state leakage by up to five orders of magnitude shown in Figure 4a. Figure 4b shows the tunneling probability near the drain for different L_GD values while the device is in the off-state.

Conversely, in a back-gated architecture with fixed L_GD of 50 nm, reducing L_GS strongly enhances the gate’s electrostatic control over the source-side channel potential. This short-range coupling suppresses the lateral spread of the DIBL effect near the source. As shown in Figure 4c, by minimizing L_GS from 50 nm to 0 nm, achieves a current leakage reduction of three orders of magnitude. The corresponding band diagram is shown in Figure 4d. When the LGS is shortened, the potential barrier at the source end is raised and becomes more stable. This higher barrier raises the energy threshold for thermionic emission. As a result, carrier injection in the off-state is drastically reduced. At the nanoscale, the relative placement of the gate with respect to the source and drain becomes a critical factor.

3.2. Geometric Effects on Off-State Leakage

We propose an asymmetric back-gated CNT PMOS(NMOS) architecture integrating high-purity small diameter HiPco CNT channels. The channel in both types of devices is formed by a network of HiPco CNTs with a density of approximately 30 CNTs/µm. The Source and Drain metals differ between the two devices, with Scandium (Sc) in NMOS and Palladium (Pd) in PMOS. The gate metal stack consisted of a TiN with a 5 nm HfO₂ dielectric bilayer, where AlON served as a passivation layer. As illustrated in Figure 5a, the gate is positioned adjacent to the source. Based on the above device structure, we perform a symmetry analysis on devices with a gate length (L_g) of 130 nm and a total channel length (L_ch) of 230 nm, in order to evaluate the impact of different gate placements on device performance. This design suppresses the off-state current by around five orders of magnitude in both NMOS and PMOS devices as shown in Figure 5c,d. The underlying physical mechanism is elucidated in Figure 5b. Firstly, it raises and stabilizes the carrier injection barrier at the source, thereby limiting the initial carrier influx into the channel. Secondly, it extends and broadens the potential barrier near the drain. Notably, the asymmetric devices exhibit a reduced subthreshold swing, from approximately 85 mV/dec for the symmetric devices to ~64 mV/dec, indicating enhanced gate control and a corresponding improvement in switching speed.

To evaluate the sensitivity of placing the gate near the source, we define the gate-source overlap length (L_OV) as the physical distance between the gate edge and the source side of the channel. Subsequent simulations focused on its effect on device performance. Figure 6a,b show the transfer curves. When L_OV exceeds 20 nm, the reduction in off-state leakage becomes marginal. The results indicate that the device enters a field-controlled saturation regime. This regime is characterized by the fact that further increasing the L_OV neither significantly enhances electrostatic control near the source. In practical device fabrication, small deviations in gate placement within this range of L_OV have a limited impact on performance. This indicates that the design is tolerant to placement variations and provides a key reference for future device iterations.

To clearly illustrate the combined effect of CNT diameter and gate architecture on the off-state current (Ioff), We design three sets of comparative simulations. In these simulations, all key parameters, including L_g, L_ch, V_DS, and dielectric stack, were kept constant. Only the CNT diameter and gate symmetry were varied to isolate their respective effects. The simulation results are summarized in

Table 2. Benchmarks of 130 nm L_g CNT PMOS with different device structures under V_DS = −1 V.

Structure	dCNT (nm)	Eg (eV)	Ioff (A/μm)	Ion/Ioff
Symmetric gate	1.5	~0.56	5.2 × 10−9	2.4 × 104
Symmetric gate	1.1	~0.74	6.8 × 10−11	8 × 105
Asymmetric gate	1.1	~0.74	3.4 × 10−17	1.7 × 1012

. Reducing the CNT diameter alone lowers the off-state current by roughly two orders of magnitude. This reduction is mainly caused by the larger bandgap that small-diameter CNTs possess. The widened bandgap effectively suppresses both thermionic and tunneling leakage. On this basis, introducing an asymmetric gate further reduces the leakage current by more than five orders of magnitude, indicating that the asymmetric gate can modulate the electrostatic field distribution to further suppress carrier leakage and significantly enhance off-state performance.

To quantitatively assess the scalability of proposed strategy, we further develop a model of carbon-nanotube (CNT) array transistors. Device currents per unit width are normalized to a CNT line density of ~125 CNTs µm⁻¹ [21], and we simulate the electrical characteristics of asymmetric back-gated CNT field-effect transistors (FETs) of both p-type and n-type, for gate lengths ranging from 28 nm to 130 nm. The device geometries at different technology nodes were obtained by geometric scaling from a 130 nm reference structure, where all characteristic lengths (L_ch, L_OV, and L_GD) were scaled proportionally by the same factor, while the intrinsic CNT transport and contact parameters were kept unchanged. The key scaled parameters and corresponding simulation results for each node are summarized in

Table 3. Scaled parameters of each node with corresponding simulation results.

Lg (nm)	Lov (nm)	LGD (nm)	Lch (nm)	Tox (nm)	Ion/Ioff	SS (mV/dec)
28	6	30	52	3.5	108	85
45	10	60	95	5	108	78
90	20	120	190	5	1011	65

. Figure 7a,b plot the transfer characteristics. At the aggressively scaled 28 nm node (with corresponding L_OV = 6 nm and L_GD = 30 nm), the device maintains an on/off ratio greater than 10⁸ and an SS of ~85 mV/dec.

4. Conclusions

An empirically calibrated TCAD framework is developed for accurate simulation of back-gated small-diameter CNTFETs. Using this framework, the geometric origins of off-state leakage, particularly gate-induced drain leakage are analyzed. A source-aligned asymmetric gate design effectively suppresses short-channel effects by reshaping the channel electrostatics, leading to more than five orders of magnitude reduction in off-state current compared with conventional symmetric gates at a gate length of 130 nm. The proposed structure shows excellent scalability, maintaining an on/off ratio above and a near-ideal subthreshold swing (~85 mV/dec) at a gate length of 28 nm, indicating a viable path toward femtoampere-level CNT CMOS technology.