High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET

This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si0.8Ge0.2 FinFET, and Si0.8Ge0.2/Si SL FinFET, were comprehensively compared with HfO2 = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si0.8Ge0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SSavg) of 88 mV/dec, the highest maximum transconductance (Gm, max) of 375.2 μS/μm, and the highest ON–OFF current ratio (ION/IOFF), approximately 106 at VOV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal–oxide–semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si0.8Ge0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si0.8Ge0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.


Introduction
As CMOS technology scales down, Si-based FinFET technology will eventually reach its physical and electrical limits. To scale transistors, it is necessary to enhance the mobility of the channel. One approach to achieving this is through the use of high-mobility channel materials, such as SiGe [1,2], Ge [3,4], and GeSn [5,6], as well as strain engineering [7,8]. By applying mechanical stress to the channel region of the transistor, carrier mobility can be increased by modifying the band structure. Compressive strained SiGe is a promising alternative to Si in pFETs due to its superior hole mobility, which can enhance device drive current and transconductance (G m ) [9][10][11]. On the other hand, tensile strained Si is proposed for enhancing effective electron mobility in nFETs [12][13][14]. Previous research has demonstrated that SiGe super-lattice-like heterostructures with a buried channel within bulk FinFETs can improve channel mobility and drive current, while also inhibiting short channel effects (SCEs) that are typically observed in conventional Si FinFET and SiGe FinFET devices [15]. The SiGe/Si super-lattice-like heterostructure induces an intrinsic strain effect on the high-mobility SiGe layer, resulting in even higher carrier mobility than traditional Si channels. Moreover, the heterostructure can be seamlessly integrated into existing FinFET technology, as it is compatible with current fabrication processes. This paper presents the fabrication of a super-lattice channel FinFET using a Si 0.8 Ge 0.2 /Si heterostructure. The epitaxy mono-crystallinity and full strain of the Si 0.8 Ge 0.2 /Si superlattice structure were confirmed through various material analyses. Conventional Si FinFET and Si 0.8 Ge 0.2 FinFET were also prepared as references for device characteristic comparison. The results showed that the Si 0.8 Ge 0.2 /Si super-lattice FinFETs exhibit superior electrical characteristics in both N-and P-type devices. The potential use of the Si 0.8 Ge 0.2 /Si superlattice FinFETs in CMOS inverters and the voltage transfer characteristics (VTCs) were also investigated. In addition, the Si 0.8 Ge 0.2 /Si super-lattice FinFET was simulated using the Sentaurus technology computer-aided design (TCAD) simulator with the state of the art. Overall, these results demonstrate that these devices are promising candidates for CMOS scaling.  Figure 1b,c, respectively. First, the monocrystalline Si layer of an 8" SOI wafer was thinned down to the thickness of 25 nm, serving as the bottom layer. Then, a 5 nm thick Si 0.8 Ge 0.2 layer was grown epitaxially, followed by two cycles of epitaxy consisting of a 5 nm thick Si layer/5 nm thick Si 0. 8  existing FinFET technology, as it is compatible with current fabrication processes. This paper presents the fabrication of a super-lattice channel FinFET using a Si0.8Ge0.2/Si heterostructure. The epitaxy mono-crystallinity and full strain of the Si0.8Ge0.2/Si super-lattice structure were confirmed through various material analyses. Conventional Si FinFET and Si0.8Ge0.2 FinFET were also prepared as references for device characteristic comparison. The results showed that the Si0.8Ge0.2/Si super-lattice FinFETs exhibit superior electrical characteristics in both N-and P-type devices. The potential use of the Si0.8Ge0.2/Si super-lattice FinFETs in CMOS inverters and the voltage transfer characteristics (VTCs) were also investigated. In addition, the Si0.8Ge0.2/Si super-lattice FinFET was simulated using the Sentaurus technology computer-aided design (TCAD) simulator with the state of the art. Overall, these results demonstrate that these devices are promising candidates for CMOS scaling. Figure 1a depicts the fabrication process flow of the Si0.8Ge0.2/Si SL FinFET device. The structural and A-A' cross-sectional schemes of the Si0.8Ge0.2/Si SL FinFET are illustrated in Figure 1b,c, respectively. First, the monocrystalline Si layer of an 8" SOI wafer was thinned down to the thickness of 25 nm, serving as the bottom layer. Then, a 5 nm thick Si0.8Ge0.2 layer was grown epitaxially, followed by two cycles of epitaxy consisting of a 5 nm thick Si layer/5 nm thick Si0.8Ge0.2 by LPCVD. The final total height of the Si0.8Ge0.2/Si SL stack was approximately 48 nm. For a fair comparison, conventional Si and Si0.8Ge0.2 FinFETs were also fabricated.  The active layer of the device was defined using e-beam lithography (EBL), and the pattern was transferred through reactive ion etching (RIE). After chemical cleaning, a 4 nm thick HfO 2 layer was deposited as the gate dielectric layer using atomic layer deposition (ALD). Subsequently, the gate electrode was formed by depositing an 80 nm thick TiN metal using physical vapor deposition (PVD), and the pattern was transferred through EBL and RIE. For the N-type devices, the source/drain (S/D) regions were implanted with phosphorus at a dose of 1 × 10 15 cm −2 and energy of 15 keV, and for P-type devices, the S/D regions were implanted with boron at a dose of 1 × 10 15 cm −2 and energy of 12 keV. Rapid thermal annealing (RTA) was performed at 550 • C for 30 s in a nitrogen atmosphere to activate the dopants. Finally, the device fabrication was completed by performing oxide passivation, contact holes, and metallization processes.  Figure 2b, where the a three-stacked epi-layer SL structure has a total fin height (F H ) of 48 nm. Figure 2c displays an enlarged view of the 1 nm thick SiO 2 interfacial layer and 4.1 nm thick HfO 2 gate insulator. The corresponding energy-dispersive X-ray spectroscopy (EDX) mapping is presented in Figure 3a. Clear separation of the Si 0.8 Ge 0.2 and Si epi-layers can be observed in the EDX mapping in Figure 3b-g, which also show the distributions of the elements including Si, Ge, Hf, O, Ti, and N.

Results and Discussion
The active layer of the device was defined using e-beam lithography (EBL), and the pattern was transferred through reactive ion etching (RIE). After chemical cleaning, a 4 nm thick HfO2 layer was deposited as the gate dielectric layer using atomic layer deposition (ALD). Subsequently, the gate electrode was formed by depositing an 80 nm thick TiN metal using physical vapor deposition (PVD), and the pattern was transferred through EBL and RIE. For the N-type devices, the source/drain (S/D) regions were implanted with phosphorus at a dose of 1 × 10 15 cm −2 and energy of 15 keV, and for P-type devices, the S/D regions were implanted with boron at a dose of 1 × 10 15 cm −2 and energy of 12 keV. Rapid thermal annealing (RTA) was performed at 550 °C for 30 s in a nitrogen atmosphere to activate the dopants. Finally, the device fabrication was completed by performing oxide passivation, contact holes, and metallization processes.    To verify the crystallinity of the Si0.8Ge0.2/Si SL heterostructure, nanobeam diffraction (NBD) analysis was performed, with a focus on each layer. The NBD patterns according To verify the crystallinity of the Si 0.8 Ge 0.2 /Si SL heterostructure, nanobeam diffraction (NBD) analysis was performed, with a focus on each layer. The NBD patterns according to the focusing point from the top to the bottom layer of the Si 0.8 Ge 0.2 /Si SL FinFET are presented in Figure 4a-f. The sharp diffraction patterns reveal that the six Si 0.8 Ge 0.2 /Si SL layers are single-crystalline and epitaxially grown. Figure 5 shows the Raman spectra of Si, Si 0.8 Ge 0.2 , and Si 0.8 Ge 0.2 /Si SL samples to analyze the strain effect. Both Si 0.8 Ge 0.2 and Si 0.8 Ge 0.2 /Si SL samples exhibit the Si-Si vibration mode, attributed to tensile strained Si, with lower wavenumbers than the c-Si peak (Figure 5a) [16], with the Si 0.8 Ge 0.2 /Si SL sample exhibiting more tensile strain. Furthermore, the Ge-Ge and Si-Ge vibration modes of the Si 0.8 Ge 0.2 /Si SL samples were observed to shift to higher wavenumbers compared to the Si 0.8 Ge 0.2 sample, indicating that the Si 0.8 Ge 0.2 layers in the Si 0.8 Ge 0.2 /Si SL sample are more compressively strained (Figure 5b).

Results and Discussion
XRD reciprocal space mapping (RSM) was used to analyze the Si 0.8 Ge 0.2 /Si SL sample at the (004) and (224) planes. The X-ray reflection from Si 0.8 Ge 0.2 /Si and Si appeared at the same in-plane wave vector, indicating that they have the same in-plane lattice constant (Figure 6a,b) [17]. This indicated that the Si 0.8 Ge 0.2 in the Si 0.8 Ge 0.2 /Si SL sample is fully compressively strained since the lattice constant of single crystal Si and Ge are 5.43 Å and 5.66 Å, respectively. The mole fraction of Ge in SiGe layers, which is approximately 20%, was determined by XRD through Vegard's law [18].  Figure 4a-f. The sharp diffraction patterns reveal that the six Si0.8Ge0.2/Si SL layers are single-crystalline and epitaxially grown. Figure 5 shows the Raman spectra of Si, Si0.8Ge0.2, and Si0.8Ge0.2/Si SL samples to analyze the strain effect. Both Si0.8Ge0.2 and Si0.8Ge0.2/Si SL samples exhibit the Si-Si vibration mode, attributed to tensile strained Si, with lower wavenumbers than the c-Si peak (Figure 5a) [16], with the Si0.8Ge0.2/Si SL sample exhibiting more tensile strain. Furthermore, the Ge-Ge and Si-Ge vibration modes of the Si0.8Ge0.2/Si SL samples were observed to shift to higher wavenumbers compared to the Si0.8Ge0.2 sample, indicating that the Si0.8Ge0.2 layers in the Si0.8Ge0.2/Si SL sample are more compressively strained (Figure 5b). XRD reciprocal space mapping (RSM) was used to analyze the Si0.8Ge0.2/Si SL sample at the (004) and (224) planes. The X-ray reflection from Si0.8Ge0.2/Si and Si appeared at the same in-plane wave vector, indicating that they have the same in-plane lattice constant (Figure 6a,b) [17]. This indicated that the Si0.8Ge0.2 in the Si0.8Ge0.2/Si SL sample is fully compressively strained since the lattice constant of single crystal Si and Ge are 5.43 Å and 5.66 Å, respectively. The mole fraction of Ge in SiGe layers, which is approximately 20%, was determined by XRD through Vegard's law [18].   (Figure 8a-c). The Si0.8Ge0.2/Si SL FinFETs exhibit the lowest SSavg,P = 93.3 mV/dec, SSavg,N = 88.0 mV/dec atc, where SS was extracted from every adjacent measured point. Due to the strain effect of the super-lattice structure, the Si0.8Ge0.2/Si SL FinFET has the highest ION and reflects on the high ION/IOFF of approximately 10 6 . The ID is normalized by the footprint width, and VTH is extracted at a constant ID of 10 −7 A/µm. ION is extracted at VOV = VD = ±0.5 V. All electrical characteristics were determined using Keithley 4200A at room temperature. Figure 9a shows that the Si0.8Ge0.2/Si SL FinFET has a drive current (VOV = VD = ±0.5 V) of 124.6 µA/µm, which is 141.8% and 55.6% higher than that of the Si FinFET and Si0.8Ge0.2 FinFET, respectively, for the P-type. In Figure 9b, the drive current for the Si0.8Ge0.2/Si SL FinFET is 92.5 µA/µm, which is 52.7% and 61.1% higher than that of the Si FinFET and  (Figure 8a-c). The Si0.8Ge0.2/Si SL FinFETs exhibit the lowest SSavg,P = 93.3 mV/dec, SSavg,N = 88.0 mV/dec atc, where SS was extracted from every adjacent measured point. Due to the strain effect of the super-lattice structure, the Si0.8Ge0.2/Si SL FinFET has the highest ION and reflects on the high ION/IOFF of approximately 10 6 . The ID is normalized by the footprint width, and VTH is extracted at a constant ID of 10 −7 A/µm. ION is extracted at VOV = VD = ±0.5 V. All electrical characteristics were determined using Keithley 4200A at room temperature. Figure 9a shows that the Si0.8Ge0.2/Si SL FinFET has a drive current (VOV = VD = ±0.5 V) of 124.6 µA/µm, which is 141.8% and 55.6% higher than that of the Si FinFET and Si0.8Ge0.2 FinFET, respectively, for the P-type. In Figure 9b, the drive current for the Si0.8Ge0.2/Si SL FinFET is 92.5 µA/µm, which is 52.7% and 61.1% higher than that of the Si FinFET and Si0.8Ge0.2 FinFET, respectively, for the N-type. Figure 10a,b show that the Si0.8Ge0.2 SL    Figure 9a shows that the Si 0.8 Ge 0.2 /Si SL FinFET has a drive current (V OV = V D = ±0.5 V) of 124.6 µA/µm, which is 141.8% and 55.6% higher than that of the Si FinFET and Si 0.8 Ge 0.2 FinFET, respectively, for the P-type. In Figure 9b, the drive current for the Si 0.8 Ge 0.2 /Si SL FinFET is 92.5 µA/µm, which is 52.7% and 61.1% higher than that of the Si FinFET and Si 0.8 Ge 0.2 FinFET, respectively, for the N-type. Figure 10a Figure 11b, the drive current (VOV = VD = ±0.7 V) of the Si0.8Ge0.2/Si SL FinFET CMOS inverter is 245.9 µA/µm and 176.8 µA/µm for the P-and N-type Si0.8Ge0.2/Si SL FinFET, respectively. Figure 11c depicts the voltage transfer characteristic (VTC) of the Si0.8Ge0.2/Si SL FinFET CMOS inverter, with a maximum gain of 91 v/v by varying the supply voltage from 0.6 V to 1.2 V, as shown in Figure 11d.  To confirm the potential of the proposed approach in contributing to the development of future technology nodes, the Sentaurus TCAD simulator was applied for simulation. The simulation parameters of the devices, including LG = 15 nm and FW = 5 nm, were selected based on the current state of the art [19]. The gate insulator utilized was HfO2 with a thickness of 4 nm, and the total fin height was set to 48 nm to match the experimental conditions of this study. Figure 12a displays the calibrated ID-VG characteristic of the Si0.8Ge0.2/Si SL FinFET with LG = 60 nm and FW = 30 nm for both the P-and N-type, between experimental data and the TCAD simulation results. In Figure 12b, the ID-VG characteristics of the Si0.8Ge0.2/Si SL, Si0.8Ge0.2, and Si FinFET devices are compared. The results indicate that compared to the Si FinFET and Si0.8Ge0.2 FinFET, the saturation current of the Si0.8Ge0.2/Si SL FinFET exhibits the highest value of 7.26 × 10 −5 for the P-type and 3.8 × 10 −5 for the N-type. Figure 12c presents the simulated Si0.8Ge0.2/Si SL FinFET, which exhibits SSavg,P = 66.1 mV/dec and SSavg,N = 66.5 mV/dec, with values of DIBLP = 31.8 mV/V and DIBLN = 65.4 mV/V. In Figure 12d, the drive current (VOV = VD = ±0.7 V) of the Si0.8Ge0.2/Si SL FinFET is 87.4 µA/µm for the P-type and 52.8 µA/µm for the N-type. While GAAFET has the advantage of better scaling, its complex fabrication and low yield make it less practical for certain applications. As an alternative, the Si0.8Ge0.2/Si SL FinFET can extend FinFET technology to more particle applications. To confirm the potential of the proposed approach in contributing to the development of future technology nodes, the Sentaurus TCAD simulator was applied for simulation. The simulation parameters of the devices, including L G = 15 nm and F W = 5 nm, were selected based on the current state of the art [19]. The gate insulator utilized was HfO 2 with a thickness of 4 nm, and the total fin height was set to 48 nm to match the experimental conditions of this study. Figure 12a displays the calibrated I D -V G characteristic of the Si 0.8 Ge 0.2 /Si SL FinFET with L G = 60 nm and F W = 30 nm for both the P-and N-type, between experimental data and the TCAD simulation results. In Figure 12b, the I D -V G characteristics of the Si 0.8 Ge 0.2 /Si SL, Si 0.8 Ge 0.2 , and Si FinFET devices are compared. The results indicate that compared to the Si FinFET and Si 0.8 Ge 0.2 FinFET, the saturation current of the Si 0.8 Ge 0.2 /Si SL FinFET exhibits the highest value of 7.26 × 10 −5 for the P-type and 3.8 × 10 −5 for the N-type. Figure 12c presents the simulated Si 0.8 Ge 0.2 /Si SL FinFET, which exhibits SS avg,P = 66.1 mV/dec and SS avg,N = 66.5 mV/dec, with values of DIBL P = 31.8 mV/V and DIBL N = 65.4 mV/V. In Figure 12d, the drive current (V OV = V D = ±0.7 V) of the Si 0.8 Ge 0.2 /Si SL FinFET is 87.4 µA/µm for the P-type and 52.8 µA/µm for the N-type. While GAAFET has the advantage of better scaling, its complex fabrication and low yield make it less practical for certain applications. As an alternative, the Si 0.8 Ge 0.2 /Si SL FinFET can extend FinFET technology to more particle applications. Nanomaterials 2023, 12, x FOR PEER REVIEW 10 of 12

Conclusions
The Si0.8Ge0.2/Si SL FinFET and CMOS inverter were both fabricated and characterized to evaluate their high-mobility channel achieved through the strain effect. The crystallinity and strain effect were confirmed through the implementation of NBD, Raman scattering, and XRD RSM. Si0.8Ge0.2/Si SL FinFETs exhibit remarkable electrical characteristics, including SSavg = 88 mV/dec, Gm, max = 375.2 µS/µm, and the highest ION/IOFF, approximately 10 6 , when compared to conventional Si and Si0.8Ge0.2 FinFETs. The Si0.8Ge0.2/Si SL FinFET CMOS inverter exhibits SSavg,P = 87.6 mV/dec, SSavg,N = 96.4 mV/dec, the DIBL values of DIBLP = 15.6 mV/V and DIBLN = 49.9 mV/V, and high ION/IOFF greater than 10 6 at VD = ±0.5V, with a maximum gain of 91 v/v by varying the supply voltage from 0.6 V to 1.2 V. The simulation of the Si0.8Ge0.2/Si SL FinFET with the state of the art demonstrates the potential for extending FinFET technology. The purposed Si0.8Ge0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, making it a promising alternative for extending future nanoelectronics applications.

Conclusions
The Si 0.8 Ge 0.2 /Si SL FinFET and CMOS inverter were both fabricated and characterized to evaluate their high-mobility channel achieved through the strain effect. The crystallinity and strain effect were confirmed through the implementation of NBD, Raman scattering, and XRD RSM. Si 0.8 Ge 0.2 /Si SL FinFETs exhibit remarkable electrical characteristics, including SS avg = 88 mV/dec, G m, max = 375.2 µS/µm, and the highest I ON /I OFF , approximately 10 6 , when compared to conventional Si and Si 0.8 Ge 0.2 FinFETs. The Si 0.8 Ge 0.2 /Si SL FinFET CMOS inverter exhibits SS avg,P = 87.6 mV/dec, SS avg,N = 96.4 mV/dec, the DIBL values of DIBL P = 15.6 mV/V and DIBL N = 49.9 mV/V, and high I ON /I OFF greater than 10 6 at V D = ±0.5V, with a maximum gain of 91 v/v by varying the supply voltage from 0.6 V to 1.2 V. The simulation of the Si 0.8 Ge 0.2 /Si SL FinFET with the state of the art demonstrates the potential for extending FinFET technology. The purposed Si 0.8 Ge 0.2 /Si strained SL FinFET is fully compatible with the CMOS technology platform, making it a promising alternative for extending future nanoelectronics applications.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author.