The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.


Introduction
With the characteristic size of integrated circuits (ICs) scaling down to the nanoscale range, the core transistor structures have gradually evolved into gate-all-around nanosheet FET (GAA NSFET) [1].The GAA structure exhibits excellent electrostatic performance compared to FinFET technology [2].At the same time, the nanosheet channel with a vertically stacked structure shows great performance advantages [3].However, the confined geometry and low thermal conductivity materials, such as gate oxide and HfO 2 , greatly hinder heat transport, leading to a severe self-heating effect (SHE) [4][5][6][7].The thermal conductivity of Si active regions decreases significantly due to intensified phonon scattering.Then, the thermal conductivity of the source/drain (S/D) causes an additional decrease due to heavy doping and the SiGe alloy material adopted.In addition, the nanosheet channels are floated and isolated from the substrate, making it difficult to transport heat.Due to the gate stack structure, phonon-boundary scattering is intensified.These factors lead to SHE issues being prominent in NSFET.The SHE can cause degradation of electrical performance and bring about reliability issues, ultimately decreasing the device's lifetime significantly [8][9][10][11][12].Some researchers have conducted a series of investigations into SHE issues, including compact models, optimization technologies, and self-heating mechanisms [13][14][15][16][17][18][19].In addition, the multiple lateral stacks are fabricated in NSFETs for high performance.The self-heating will be exacerbated due to the rising current in the lateral stack structure [7].This is one aspect of thermal issues.
On the other hand, the core transistors work in practical application circuits.The electrical performance is inevitably affected by ambient temperature (T amb ), where the T amb includes those from inside the chip and the surrounding environment.The high T amb can change the temperature-sensitivity threshold voltage (V th ) and introduce variability in the on-state current.At the same time, the T amb plays a crucial role in thermal properties, such as thermal conductivity, lattice temperature rise, and thermal resistance (R th ) [20][21][22][23][24][25].Some researchers have analyzed the electrothermal characteristics of FinFETs with multiple fins under the impact of T amb [20,23,26].However, few studies focus on the research of T amb on NSFET with different numbers of lateral stacks (N stack ).In addition, there are few works on the geometry effect in NSFETs with different N stack s.Therefore, we performed a symmetrical investigation on the electrothermal performance of NSFETs with different N stack s under the T amb impact.Furthermore, the geometry effect with different N stack s is also studied.
In this paper, the T amb -dependent SHE in NSFETs with different N stack s is symmetrically measured and analyzed.The rest of the article is divided into three parts.Section 2 discusses the fabrication of NMOS and PMOS in detail.In Section 3, the current variation with different N stack s is explored.Then, the geometry effect with different gate lengths is further analyzed based on the backscattering model.In addition, the simulations are conducted for verification.Finally, the conclusion is given in Section 4.

Device Fabrication
The integration process flow design of the NSFET is summarized in Figure 1a, where the NSFET was grown on {100} bulk Si substrates.This process flow is based on the conventional fabrication process [27].The fabrication adopts the gate last process.Before the stacked nanosheets were formed, B and P were implanted to suppress the bottom parasitic channel in the ground plane process for NMOS and PMOS, respectively [28].The stacked GeSi/Si layers were formed using the epitaxy process.The nanosheet channels are stacked vertically with three layers (N ch = 3).In this step, the reduced pressure chemical vapor deposition was used to grow the periodical GeSi/Si multilayer with 16 nm Ge 0.3 Si 0.7 and 10 nm Si.Then, the fin array was carried out using spacer image transfer (SIT) technology, which was formed using a SiN x hard mask.For high-performance desire, the stacked nanosheets were fabricated with multiple lateral stacks in this step, as shown in Figure 1b.The number of parallel nanorails of lateral stacks is defined as N stack .The N stack is 2, 4, 8, 16, and 32.Next, the shallow trench isolation (STI) was formed to decrease the leakage current between the devices.Meanwhile, the rapid annealing process was performed to make the film compact.Then, a dummy gate was fabricated with amorphous Si to protect the nanosheets.After the deposition of amorphous Si, the chemical mechanical planarization (CMP) was used to perform the planarization process.The dummy gate image was formed using deposition and etch of Si 3 N 4 hard mask.The inner spacer formation was a key process that was deposited using SiN x and etched using reactive ion etching (RIE).After this, the in-situ doping process with highly doped doses and the activation process were carried out to form S/D. The zero-level interlayer dielectric (ILD0) with SiN x is used to avoid the over-etch phenomenon.After the dummy gate removal, GeSi was selectively removed using the wet-etched technique.After forming the thin gate oxide layer, the HfO 2 was deposited and the nanosheet was surrounded by different metal stacks.The atom-layer-deposition technology (ALD) was used to deposit the multilayer HK/MG films, and the CMP was performed to achieve gate separation.Finally, the tungsten contact and the BEOL process were fabricated to complete the NSFETs.
the CMP was performed to achieve gate separation.Finally, the tungsten contact and the BEOL process were fabricated to complete the NSFETs.Through the measurement of transmission electron microscopy (TEM), Figure 2 shows the fabricated channel structure of NSFETs, which can be seen that the NSFETs are successfully fabricated according to the process flow.The nanosheets are separated using HK/MG, and the STI is formed near the sub-fin.The width of the sub-fin is similar to that of the nanosheet.The nanosheet width (WNS) is about 30 nm, and the nanosheet thickness (TNS) is about 10 nm.The gate length (LG) is 30, 40, 60, and 500 nm.Then, energy-dispersive spectroscopy (EDS) is used to exhibit the distribution of elements in NSFETs, as shown in Figure 3.It shows that Ge has been completely removed, and the nanosheets are separated from each other.Each nanosheet is surrounded by Hf and oxide elements.This indicates that the nanosheets can be well controlled using bias voltages.At the same time, it can be seen that Al, Ti, N, and Ta elements are deposited surrounding the nanosheets, and the W element has been wrapped to the Si nanosheets.Through the measurement of transmission electron microscopy (TEM), Figure 2 shows the fabricated channel structure of NSFETs, which can be seen that the NSFETs are successfully fabricated according to the process flow.The nanosheets are separated using HK/MG, and the STI is formed near the sub-fin.The width of the sub-fin is similar to that of the nanosheet.The nanosheet width (W NS ) is about 30 nm, and the nanosheet thickness (T NS ) is about 10 nm.The gate length (L G ) is 30, 40, 60, and 500 nm.Then, energy-dispersive spectroscopy (EDS) is used to exhibit the distribution of elements in NSFETs, as shown in Figure 3.It shows that Ge has been completely removed, and the nanosheets are separated from each other.Each nanosheet is surrounded by Hf and oxide elements.This indicates that the nanosheets can be well controlled using bias voltages.At the same time, it can be seen that Al, Ti, N, and Ta elements are deposited surrounding the nanosheets, and the W element has been wrapped to the Si nanosheets.
Nanomaterials 2023, 13, x FOR PEER REVIEW 3 of 12 the CMP was performed to achieve gate separation.Finally, the tungsten contact and the BEOL process were fabricated to complete the NSFETs.Through the measurement of transmission electron microscopy (TEM), Figure 2 shows the fabricated channel structure of NSFETs, which can be seen that the NSFETs are successfully fabricated according to the process flow.The nanosheets are separated using HK/MG, and the STI is formed near the sub-fin.The width of the sub-fin is similar to that of the nanosheet.The nanosheet width (WNS) is about 30 nm, and the nanosheet thickness (TNS) is about 10 nm.The gate length (LG) is 30, 40, 60, and 500 nm.Then, energy-dispersive spectroscopy (EDS) is used to exhibit the distribution of elements in NSFETs, as shown in Figure 3.It shows that Ge has been completely removed, and the nanosheets are separated from each other.Each nanosheet is surrounded by Hf and oxide elements.This indicates that the nanosheets can be well controlled using bias voltages.At the same time, it can be seen that Al, Ti, N, and Ta elements are deposited surrounding the nanosheets, and the W element has been wrapped to the Si nanosheets.

Electrothermal Performance of Different Numbers of Stacks under the Impact of Ambient Temperature
Since the measurement is dependent on ambient temperature (Tamb), the Tamb-dependent SHE in NSFETs is measured using the Agilent B1500 semiconductor parameter analyzer (Agilent Technologies, Santa Clara, CA, USA).The Tamb varies from −50 °C to 125 °C in a 25 °C step.
As shown in Figure 4, the transfer characteristic curves exhibit a variation in drain current (IDS) as the Tamb increases for NMOS and PMOS.The threshold voltages (Vths) are 300 mV and −300 mV at Tamb = 25 °C of room temperature (Trt) for NMOS and PMOS, respectively.The Vth is extracted using the constant current method.As the Tamb increases, the |Vth| decreases because the carrier concentration is positively correlated with the Tamb.In Figure 4a, the IDS of NMOS shows an increasing trend.Meanwhile, the IDS of PMOS also shows an increasing trend at a lower |VGS|.However, it exhibits a reverse temperature dependence at a larger |VGS|, as shown in Figure 4b.This is because the effect of the Vth reduction exceeds that of the mobility degradation in NMOS.However, the effect of the |Vth| reduction is inferior to that of the mobility degradation at a larger |VGS| in PMOS.Moreover, the IDS of PMOS is higher than that of NMOS at a larger |VGS|.The current degradation indicates that the higher current is more severely impacted by Tamb.In addition, it is found that the zero-temperature coefficient bias point (VZTC) occurs in PMOS, where the VZTC represents the bias voltage point that the IDS is independent of the Tamb [29].In addition, there are two VZTC under Tamb = −50~25 °C range and Tamb = 25~125 °C range.

Electrothermal Performance of Different Numbers of Stacks under the Impact of Ambient Temperature
Since the measurement is dependent on ambient temperature (T amb ), the T ambdependent SHE in NSFETs is measured using the Agilent B1500 semiconductor parameter analyzer (Agilent Technologies, Santa Clara, CA, USA).The T amb varies from −50 As shown in Figure 4, the transfer characteristic curves exhibit a variation in drain current (I DS ) as the T amb increases for NMOS and PMOS.The threshold voltages (V th s) are 300 mV and −300 mV at T amb = 25 • C of room temperature (T rt ) for NMOS and PMOS, respectively.The V th is extracted using the constant current method.As the T amb increases, the |V th | decreases because the carrier concentration is positively correlated with the T amb .In Figure 4a, the I DS of NMOS shows an increasing trend.Meanwhile, the I DS of PMOS also shows an increasing trend at a lower |V GS |.However, it exhibits a reverse temperature dependence at a larger |V GS |, as shown in Figure 4b.This is because the effect of the V th reduction exceeds that of the mobility degradation in NMOS.However, the effect of the |V th | reduction is inferior to that of the mobility degradation at a larger |V GS | in PMOS.Moreover, the I DS of PMOS is higher than that of NMOS at a larger |V GS |.The current degradation indicates that the higher current is more severely impacted by T amb .In addition, it is found that the zero-temperature coefficient bias point (V ZTC ) occurs in PMOS, where the V ZTC represents the bias voltage point that the I DS is independent of the T amb [29].In addition, there are two V ZTC under T amb = −50~25 • C range and T amb = 25~125 • C range.To analyze the origin of the IDS variation, the temperature coefficients of IDS per stack (β) are extracted, as shown in Figure 6. Figure 6a shows that β in NMOS decreases in the negative direction under Tamb above Trt when Nstack is from 4 to 32.This is induced by the coupling mechanism with the impact of the SHE and Tamb.As the Nstack increases, the thermal crosstalk is enhanced in stacked nanosheets, where the thermal crosstalk is part of the SHE.The SHE can intensify phonon-electron scattering, and then counteract the partial effect of Tamb, resulting in reduced IDS degradation.In Section 3.3, the simulation results will further verify the speculation.The β in NMOS with Nstack = 2 is the lowest [Figure 6a].To explore the T amb -dependent relation, Figure 5 shows that the I DS variations with different N stack s under the impact of T amb are extracted relative to the I DS at T amb = −50 • C, and the gate overdrive voltage (V ov = V GS − V th ) is 0.43 V and −0.43 V for NMOS and PMOS, respectively.The I DS degradation of NMOS is lower than that of PMOS.At high T amb , The NMOS with N stack = 4 shows the largest I DS degradation, and other multiple stacks have minor differences.The devices with N stack = 2 have the lowest I DS degradation at high T amb in Figure 5a.PMOS shows a different trend when N stack increases, as shown in Figure 5b.The PMOS with N stack = 2 shows the largest I DS degradation, and other multiple stacks have minor differences.The PMOS with N stack = 32 shows the lowest I DS degradation.The I DS variation in NMOS with N stack = 4 and PMOS with N stack = 2 may be induced by random structure irregularities.To analyze the origin of the IDS variation, the temperature coefficients of IDS per stack (β) are extracted, as shown in Figure 6. Figure 6a shows that β in NMOS decreases in the negative direction under Tamb above Trt when Nstack is from 4 to 32.This is induced by the coupling mechanism with the impact of the SHE and Tamb.As the Nstack increases, the thermal crosstalk is enhanced in stacked nanosheets, where the thermal crosstalk is part of the SHE.The SHE can intensify phonon-electron scattering, and then counteract the partial effect of Tamb, resulting in reduced IDS degradation.In Section 3.3, the simulation results will further verify the speculation.The β in NMOS with Nstack = 2 is the lowest [Figure 6a].To analyze the origin of the I DS variation, the temperature coefficients of I DS per stack (β) are extracted, as shown in Figure 6. Figure 6a shows that β in NMOS decreases in the negative direction under T amb above T rt when N stack is from 4 to 32.This is induced by the coupling mechanism with the impact of the SHE and T amb .As the N stack increases, the thermal crosstalk is enhanced in stacked nanosheets, where the thermal crosstalk is part of the SHE.The SHE can intensify phonon-electron scattering, and then counteract the partial effect of T amb , resulting in reduced I DS degradation.In Section 3.3, the simulation results will further verify the speculation.The β in NMOS with N stack = 2 is the lowest [Figure 6a].This can be caused by difficult heat transport due to the smaller contact area between nanosheets and the S/D region, leading to severe thermal crosstalk.Meanwhile, the β under T amb below 0 • C is basically larger than that under T amb above T rt .This is because the impact of thermal crosstalk is weakened by enhanced heat transport ability.This can be caused by difficult heat transport due to the smaller contact area between nanosheets and the S/D region, leading to severe thermal crosstalk.Meanwhile, the β under Tamb below 0 °C is basically larger than that under Tamb above Trt.This is because the impact of thermal crosstalk is weakened by enhanced heat transport ability.Figure 6b shows that the β in PMOS is larger than that in NMOS.The carrier scattering intensifies by Tamb because the current density (JDS) in PMOS is larger than that in NMOS.The PMOS with Nstack = 2 exhibits the largest β.This reverse behavior is due to the highest JDS in PMOS with Nstack = 2 compared to NMOS.In addition, the difference of β when Nstack = 4~32 is small.This is because the difference in JDS of PMOS is small, and thus the difference in thermal crosstalk is relatively insignificant.
Then, the temperature coefficient of Vth (η) is extracted, as shown in Figure 7.The η in NMOS under Tamb above Trt rapidly decreases in the negative direction with Nstack first, and then the velocity of decrease gradually slows down [Figure 7a].The η of NMOS with Nstack = 16 is the lowest.This is because the thermal crosstalk becomes severe; therefore, the impact of Tamb is mitigated.However, it increases when the Nstack grows to 32.This can be explained by the heat transport ability that the contact area between nanosheets and S/D regions gradually increases with Nstack, and then the enhanced thermal crosstalk effect is weakened.Therefore, the η with Nstack = 32 increases.The η in NMOS under Tamb below 0 °C rapidly decreases first, and then increases with Nstack = 16.The η in PMOS exhibits a similar trend compared with that in NMOS [Figure 7b].However, the η value is larger.L G = 500 nm NMOS Figure 6.L G = 500 nm, (a) V DS = 0.9 V, V ov = 0.59 V, the temperature coefficients of I DS per stack in NMOS, (b) V DS = −0.9V, V ov = −0.59V, the temperature coefficients of I DS per stack in PMOS under different T amb ranges.
Figure 6b shows that the β in PMOS is larger than that in NMOS.The carrier scattering intensifies by T amb because the current density (J DS ) in PMOS is larger than that in NMOS.The PMOS with N stack = 2 exhibits the largest β.This reverse behavior is due to the highest J DS in PMOS with N stack = 2 compared to NMOS.In addition, the difference of β when N stack = 4~32 is small.This is because the difference in J DS of PMOS is small, and thus the difference in thermal crosstalk is relatively insignificant.
Then, the temperature coefficient of V th (η) is extracted, as shown in Figure 7.The η in NMOS under T amb above T rt rapidly decreases in the negative direction with N stack first, and then the velocity of decrease gradually slows down [Figure 7a].The η of NMOS with N stack = 16 is the lowest.This is because the thermal crosstalk becomes severe; therefore, the impact of T amb is mitigated.However, it increases when the N stack grows to 32.This can be explained by the heat transport ability that the contact area between nanosheets and S/D regions gradually increases with N stack , and then the enhanced thermal crosstalk effect is weakened.Therefore, the η with N stack = 32 increases.The η in NMOS under T amb below 0 • C rapidly decreases first, and then increases with N stack = 16.The η in PMOS exhibits a similar trend compared with that in NMOS [Figure 7b].However, the η value is larger.This can be caused by difficult heat transport due to the smaller contact area between nanosheets and the S/D region, leading to severe thermal crosstalk.Meanwhile, the β under Tamb below 0 °C is basically larger than that under Tamb above Trt.This is because the impact of thermal crosstalk is weakened by enhanced heat transport ability.Figure 6b shows that the β in PMOS is larger than that in NMOS.The carrier scattering intensifies by Tamb because the current density (JDS) in PMOS is larger than that in NMOS.The PMOS with Nstack = 2 exhibits the largest β.This reverse behavior is due to the highest JDS in PMOS with Nstack = 2 compared to NMOS.In addition, the difference of β when Nstack = 4~32 is small.This is because the difference in JDS of PMOS is small, and thus the difference in thermal crosstalk is relatively insignificant.
Then, the temperature coefficient of Vth (η) is extracted, as shown in Figure 7.The η in NMOS under Tamb above Trt rapidly decreases in the negative direction with Nstack first, and then the velocity of decrease gradually slows down [Figure 7a].The η of NMOS with Nstack = 16 is the lowest.This is because the thermal crosstalk becomes severe; therefore, the impact of Tamb is mitigated.However, it increases when the Nstack grows to 32.This can be explained by the heat transport ability that the contact area between nanosheets and S/D regions gradually increases with Nstack, and then the enhanced thermal crosstalk effect is weakened.Therefore, the η with Nstack = 32 increases.The η in NMOS under Tamb below 0 °C rapidly decreases first, and then increases with Nstack = 16.The η in PMOS exhibits a similar trend compared with that in NMOS [Figure 7b].However, the η value is larger.The relation between the I DS variation and the η based on the temperature-dependent backscattering model is also further analyzed.In the temperature-dependent backscattering model [30,31], the I DS formula is defined using (1), and the linear relation of I DS and T amb is given using (2).Finally, the analytic expression for α concerning temperature is given using (3): In the equations, Q inj is the inverse layer density near the source region; ν th is the thermal injection velocity at the thermal source; λ 0 is the mean-free path; l 0 is the critical distance when the carriers travel over a KT layer from the thermal source, where K and T are Boltzmann constant and temperature, respectively; and V th0 is the threshold voltage at referenced temperature −50 • C. The α includes the backscattering coefficient term and the voltage-dependence term.In Figure 7, the η in PMOS is higher than that in NMOS significantly, and thus the second term of (3) becomes larger.This leads to a greater degradation of the I DS in PMOS compared to NMOS when T amb increases, as shown in Figure 5.
As a special thermal phenomenon, the V ZTC of PMOS is extracted in Figure 8.It is shown that the V ZTC of PMOS decreases in the negative direction under T amb above T rt when N stack grows from 4 to 32.The result can be explained by the coupling mechanism with the impact of the SHE and T amb .As the N stack increases, the current variation comes to balance at lower |V GS | due to the effect of V th and mobility.However, the V ZTC under T amb below T rt is 0.1 V higher than that under higher T amb in the negative direction.This is because the SHE plays a lesser role in the case of T amb below T rt .Therefore, the effect of V th and mobility compensate at a higher V GS for the lower T amb .The investigation of V ZTC is useful to explore the working voltage in real applications.
The relation between the IDS variation and the η based on the temperature-dependen backscattering model is also further analyzed.In the temperature-dependent backscatter ing model [30,31], the IDS formula is defined using (1), and the linear relation of IDS and Tamb is given using (2).Finally, the analytic expression for α concerning temperature i given using (3): In the equations, Qinj is the inverse layer density near the source region; νth is the ther mal injection velocity at the thermal source; λ0 is the mean-free path; l0 is the critical dis tance when the carriers travel over a KT layer from the thermal source, where K and T ar Boltzmann constant and temperature, respectively; and Vth0 is the threshold voltage at ref erenced temperature −50 °C.The α includes the backscattering coefficient term and th voltage-dependence term.In Figure 7, the η in PMOS is higher than that in NMOS signif icantly, and thus the second term of (3) becomes larger.This leads to a greater degradatio of the IDS in PMOS compared to NMOS when Tamb increases, as shown in Figure 5.
As a special thermal phenomenon, the VZTC of PMOS is extracted in Figure 8.It i shown that the VZTC of PMOS decreases in the negative direction under Tamb above T when Nstack grows from 4 to 32.The result can be explained by the coupling mechanism with the impact of the SHE and Tamb.As the Nstack increases, the current variation comes t balance at lower |VGS| due to the effect of Vth and mobility.However, the VZTC under Tam below Trt is 0.1 V higher than that under higher Tamb in the negative direction.This is be cause the SHE plays a lesser role in the case of Tamb below Trt.Therefore, the effect of V and mobility compensate at a higher VGS for the lower Tamb.The investigation of VZTC i useful to explore the working voltage in real applications.

Electrothermal Performance of Different Gate
Lengths with Different N stack s under the Impact of T amb explore the geometry effect, we further analyze the impact of gate lengths on electrical performance with different N stack s, as shown in Figure 9.As L G increases, the degradation of I DS becomes severe.This can be explained by the temperature-dependent backscattering model.
As the L G increases, the channel potential decreases, and then l 0 increases.Thus, the first term of (3) declines.This is an inverse result with the I DS degradation [Figure 9a].Furthermore, the η is extracted, as shown in Figure 9b.The η increases in the negative direction as the L G increases at V DS = 0.9 V. Therefore, the I DS degradation is the result of both terms.At the same time, when the N stack increases at V DS = 0.9 V, the devices with L G = 30, 40 nm show that the η decreases in the negative direction first, then, increases, similar to the trend of devices with L G = 500 nm.Remarkably, when V DS = 0.9 V, the slope of η with N stack located in the 8 and 16 range is negative first, and then positive when the L G increases from 30 nm to 500 nm.
As the LG increases, the channel potential decreases, and then l0 increases.Thus, the first term of (3) declines.This is an inverse result with the IDS degradation [Figure 9a].Furthermore, the η is extracted, as shown in Figure 9b.The η increases in the negative direction as the LG increases at VDS = 0.9 V. Therefore, the IDS degradation is the result of both terms.At the same time, when the Nstack increases at VDS = 0.9 V, the devices with LG = 30, 40 nm show that the η decreases in the negative direction first, then, increases, similar to the trend of devices with LG = 500 nm.Remarkably, when VDS = 0.9 V, the slope of η with Nstack located in the 8 and 16 range is negative first, and then positive when the LG increases from 30 nm to 500 nm.
In addition, the IDS degradation in short gate length devices at VDS = 0.9 V is higher than that at VDS = 0.1 V.The difference gradually becomes larger with Tamb, and the device with LG = 30 nm has the largest difference.Figure 9b shows that the η increases in the negative direction as the VDS increases, and thus the second term of (3) becomes larger.Then, the λ0/l0 also increases with larger VDS, and the first term of (3) becomes larger.Finally, the IDS degradation is higher with larger VDS.

Simulation Verification
The coupling mechanism with the impact of the SHE and Tamb is verified using the simulation method.To clarify the SHE clearly, the 16 nm gate length devices are simulated.The simulated devices are 3 nm node NSFETs, referring to [1].The electrothermal parameters are set according to [32], where the LG, WNS, and TNS are set to 16, 20, and 6 nm, respectively.The nanosheets adopt three layers of vertically stacked structure.All simulations are performed using Sentaurus TCAD tools [33].The SHE is calculated with the thermodynamic model (TD model).Figure 10a shows that the IDS with the SHE is lower than that without the SHE at larger VGS.At VGS = VDS = 0.7 V, the on-state IDS (ION) degradation with the SHE is lower than that without the SHE as Tamb increases, as shown in Figure 10b.The results indicate that the SHE weakened the impact of Tamb.As the Nstack increases, the η declines in the negative direction as shown in Figure 11.At the same time, the β decreases with Nstack.This further verifies that the coupling heat counteracts the partial effect of Tamb.In addition, the I DS degradation in short gate length devices at V DS = 0.9 V is higher than that at V DS = 0.1 V.The difference gradually becomes larger with T amb , and the device with L G = 30 nm has the largest difference.Figure 9b shows that the η increases in the negative direction as the V DS increases, and thus the second term of (3) becomes larger.Then, the λ 0 /l 0 also increases with larger V DS , and the first term of (3) becomes larger.Finally, the I DS degradation is higher with larger V DS .

Simulation Verification
The coupling mechanism with the impact of the SHE and T amb is verified using the simulation method.To clarify the SHE clearly, the 16 nm gate length devices are simulated.The simulated devices are 3 nm node NSFETs, referring to [1].The electrothermal parameters are set according to [32], where the L G , W NS , and T NS are set to 16, 20, and 6 nm, respectively.The nanosheets adopt three layers of vertically stacked structure.All simulations are performed using Sentaurus TCAD tools [33].The SHE is calculated with the thermodynamic model (TD model).Figure 10a shows that the I DS with the SHE is lower than that without the SHE at larger V GS .At V GS = V DS = 0.7 V, the on-state I DS (I ON ) degradation with the SHE is lower than that without the SHE as T amb increases, as shown in Figure 10b.The results indicate that the SHE weakened the impact of T amb .As the N stack increases, the η declines in the negative direction as shown in Figure 11.At the same time, the β decreases with N stack .This further verifies that the coupling heat counteracts the partial effect of T amb .
To further investigate thermal characteristics, the thermal resistance (R th ) and the maximum lattice temperature rise (∆T max ) with respect to T amb are extracted.The R th is defined using (4), where total heat includes Joule heat, Peltier heat, Tompson heat, and recombination heat [34].To further investigate thermal characteristics, the thermal resistance (Rth) and the maximum lattice temperature rise (∆Tmax) with respect to Tamb are extracted.The Rth is defined using (4), where total heat includes Joule heat, Peltier heat, Tompson heat, and recombination heat [34].
The ∆Tmax and Rth in the devices with Nstack = 1 under Tamb = 300 K are 149 K and 2.59 K/µW, respectively, as shown in Figure 12.In Figure 12a, the ∆Tmax decreases with Tamb.However, the lattice temperature gradually increases.This explains why IDS with the SHE is lower at larger VGS [Figure 10a].At the same time, the ∆Tmax increases when Nstack is from 1 to 2 first, and then has a minor variation when Nstack is from 2 to 4. This can be explained by the Rth variation with Nstack.In Figure 12b, the Rth per stack decreases with Tamb.This is because the ∆Tmax reduction ratio exceeds the ION degradation.Then, the Rth per stack increases when Nstack is from 1 to 2, and then the rising speed increases when Nstack is from 2 to 4. This is induced by the coupling effect.The rising Rth causes an increase in lattice temperature, leading to a decrease in current density, eventually, the ∆Tmax variation is low when Nstack is from 2 to 4 compared to that when Nstack is from 1 to 2. In addition, when the Tamb increases, the Rth decreases significantly in the devices with Nstack = 4 compared to that with Nstack = 1 and 2. This is because the coupling heat is more severe in the devices with Nstack = 4.These results verify that the SHE counteracts the partial effect of Tamb.To further investigate thermal characteristics, the thermal resistance (Rth) and the maximum lattice temperature rise (∆Tmax) with respect to Tamb are extracted.The Rth is defined using (4), where total heat includes Joule heat, Peltier heat, Tompson heat, and recombination heat [34].
The ∆Tmax and Rth in the devices with Nstack = 1 under Tamb = 300 K are 149 K and 2.59 K/µW, respectively, as shown in Figure 12.In Figure 12a, the ∆Tmax decreases with Tamb.However, the lattice temperature gradually increases.This explains why IDS with the SHE is lower at larger VGS [Figure 10a].At the same time, the ∆Tmax increases when Nstack is from 1 to 2 first, and then has a minor variation when Nstack is from 2 to 4. This can be explained by the Rth variation with Nstack.In Figure 12b, the Rth per stack decreases with Tamb.This is because the ∆Tmax reduction ratio exceeds the ION degradation.Then, the Rth per stack increases when Nstack is from 1 to 2, and then the rising speed increases when Nstack is from 2 to 4. This is induced by the coupling effect.The rising Rth causes an increase in lattice temperature, leading to a decrease in current density, eventually, the ∆Tmax variation is low when Nstack is from 2 to 4 compared to that when Nstack is from 1 to 2. In addition, when the Tamb increases, the Rth decreases significantly in the devices with Nstack = 4 compared to that with Nstack = 1 and 2. This is because the coupling heat is more severe in the devices with Nstack = 4.These results verify that the SHE counteracts the partial effect of Tamb.The ∆T max and R th in the devices with N stack = 1 under T amb = 300 K are 149 K and 2.59 K/µW, respectively, as shown in Figure 12.In Figure 12a, the ∆T max decreases with T amb .However, the lattice temperature gradually increases.This explains why I DS with the SHE is lower at larger V GS [Figure 10a].At the same time, the ∆T max increases when N stack is from 1 to 2 first, and then has a minor variation when N stack is from 2 to 4. This can be explained by the R th variation with N stack .In Figure 12b, the R th per stack decreases with T amb .This is because the ∆T max reduction ratio exceeds the I ON degradation.Then, the R th per stack increases when N stack is from 1 to 2, and then the rising speed increases when N stack is from 2 to 4. This is induced by the coupling effect.The rising R th causes an increase in lattice temperature, leading to a decrease in current density, eventually, the ∆T max variation is low when N stack is from 2 to 4 compared to that when N stack is from 1 to 2. In addition, when the T amb increases, the R th decreases significantly in the devices with N stack = 4 compared to that with N stack = 1 and 2. This is because the coupling heat is more severe in the devices with N stack = 4.These results verify that the SHE counteracts the partial effect of T amb .

Conclusions
In this paper, the impact of Tamb on the SHE in NSFET with different Nstacks is investigated.The results show that the NMOS with Nstack = 2 has the lowest IDS degradation, and the IDS degradation of PMOS with Nstack = 32 is lower than that with Nstack = 2.The results show that the IDS degradation is lowest in the NMOS with Nstack = 2 and the PMOS with Nstack = 32 when the Tamb is at a high level.Due to the coupling mechanism with the impact of the SHE and Tamb, the η exhibits a decrease trend first, and then an increase trend with Nstack when the Tamb is higher than Trt.Remarkably, the VZTC of PMOS decreases with Nstack > 4 in the negative direction when Tamb is higher than Trt.Based on the backscattering theory, the IDS degradation ratio decreases when the LG becomes shorter.Meanwhile, the IDS degradation decreases at VDS = 0.1 V compared to that at VDS = 0.9 V in short gate length devices.Finally, the simulations verify that the SHE counteracts the partial effect of Tamb.The work explores the electrothermal characteristics when NSFETs with different Nstacks work under the impact of Tamb and provides design guidelines for real applications.

Figure 1 .
Figure 1.(a) Process flow of GAA NSFETs adopting the gate last process.(b) Schematic of the NSFET with multiple lateral stacks along the nanosheet width direction.

Figure 2 .Figure 1 .
Figure 2. The TEM image of GAA NSFETs in this work.The nanosheets are separated from each other.

Figure 1 .
Figure 1.(a) Process flow of GAA NSFETs adopting the gate last process.(b) Schematic of the NSFET with multiple lateral stacks along the nanosheet width direction.

Figure 2 .Figure 2 .
Figure 2. The TEM image of GAA NSFETs in this work.The nanosheets are separated from each other.

Figure 3 .
Figure 3.The EDS images of NSFETs in this work.The top figures illustrate W, Si, and O elements.The middle figures illustrate Hf, Ti, and N elements.The bottom figures illustrate Al, Ta, and Ge elements.Ge has been removed completely.

Figure 3 .
Figure 3.The EDS images of NSFETs in this work.The top figures illustrate W, Si, and O elements.The middle figures illustrate Hf, Ti, and N elements.The bottom figures illustrate Al, Ta, and Ge elements.Ge has been removed completely.

Figure 4 .
Figure 4. Experimental temperature dependence of transfer characteristics at LG = 500 nm, Nstack = 2, (a) VDS = 0.9 V for NMOS and (b) VDS = −0.9V for PMOS.It shows two VZTC under Tamb = −50~25 °C range and Tamb = 25~125 °C range.To explore the Tamb-dependent relation, Figure 5 shows that the IDS variations with different Nstacks under the impact of Tamb are extracted relative to the IDS at Tamb = −50 °C, and the gate overdrive voltage (Vov = VGS − Vth) is 0.43 V and −0.43 V for NMOS and PMOS, respectively.The IDS degradation of NMOS is lower than that of PMOS.At high Tamb, The NMOS with Nstack = 4 shows the largest IDS degradation, and other multiple stacks have minor differences.The devices with Nstack = 2 have the lowest IDS degradation at high Tamb in Figure 5a.PMOS shows a different trend when Nstack increases, as shown in Figure 5b.The PMOS with Nstack = 2 shows the largest IDS degradation, and other multiple stacks have minor differences.The PMOS with Nstack = 32 shows the lowest IDS degradation.The IDS variation in NMOS with Nstack = 4 and PMOS with Nstack = 2 may be induced by random structure irregularities.

Figure 5 .
Figure 5. (a) IDS variations of NMOS with different Nstacks under the impact of Tamb relative to the IDS at Tamb = −50 °C, (b) IDS variations of PMOS with different Nstacks under the impact of Tamb relative to the IDS at Tamb = −50 °C.

Figure 5 .
Figure 5. (a) IDS variations of NMOS with different Nstacks under the impact of Tamb relative to the IDS at Tamb = −50 °C, (b) IDS variations of PMOS with different Nstacks under the impact of Tamb relative to the IDS at Tamb = −50 °C.

Figure 5 .
Figure 5. (a) I DS variations of NMOS with different N stack s under the impact of T amb relative to the I DS at T amb = −50 • C, (b) I DS variations of PMOS with different N stack s under the impact of T amb relative to the I DS at T amb = −50 • C.

Figure 7 .
Figure 7. L G = 500 nm, the temperature coefficients of V th (η) with different N stack s in (a) NMOS and (b) PMOS under different T amb ranges.

Figure 9 .
Figure 9. (a) IDS variations with different gate lengths under the impact of Tamb relative to the IDS at Tamb = −50 °C.(b) The temperature coefficients of Vth with different gate lengths when the Nstack increases.

Figure 9 .
Figure 9. (a) I DS variations with different gate lengths under the impact of T amb relative to the I DS at T amb = −50 • C. (b) The temperature coefficients of V th with different gate lengths when the N stack increases.

Figure 10 .
Figure 10.(a) The transfer characteristics of NSFET (Nstack = 1) with/without the SHE as the Tamb increases from 300 K to 400 K, (b) IDS variations relative to the IDS at Tamb = 300 K with/without the SHE when VGS = VDS = 0.7 V.

Figure 11 .
Figure 11.The temperature coefficients of Vth and the temperature coefficients of IDS per stack with different Nstacks.

Figure 10 . 12 Figure 10 .
Figure 10.(a)The transfer characteristics of NSFET (N stack = 1) with/without the SHE as the T amb increases from 300 K to 400 K, (b) I DS variations relative to the I DS at T amb = 300 K with/without the SHE when V GS = V DS = 0.7 V.

Figure 11 .
Figure 11.The temperature coefficients of Vth and the temperature coefficients of IDS per stack with different Nstacks.

Figure 11 .
Figure 11.The temperature coefficients of V th and the temperature coefficients of I DS per stack with different N stack s.