A 37–40 GHz 6-Bits Switched-Filter Phase Shifter Using 150 nm GaN HEMT

In this paper, we present a 6-bit phase shifter designed and fabricated using the 150 nm GaN HEMT process. The designed phase shifter operates within the n260 (37~40 GHz) band, as specified in the 5G NR standard, and employs the structure of a switched-filter phase shifter. By serially connecting six single-bit phase shifters, ranging from 180° to 5.625°, the designed phase shifter achieves a phase range of 360°. The fabricated phase shifter exhibits a minimum insertion loss of 5 dB and an RMS phase error of less than 5.36° within the 37 to 40 GHz. This phase shifter is intended for seamless integration with high-power RF circuits.


Introduction
With the emergence and widespread adoption of the 5th generation communication (5G), the 3rd Generation Partnership Project (3GPP) has established millimeter wave frequency bands, such as n257 (26.5~29.5 GHz) and n260 (37~40 GHz), as standards for 5G New Radio (NR).These defined frequency bands are now being adopted by numerous countries, necessitating the support for mmWave systems to enable cross-network roaming of User Equipment (UE) devices [1,2].In high-frequency wireless communication systems, phased arrays play a crucial role in effectively concentrating the transmitter output power.It is crucial to provide appropriate phase and amplitude control signals to individual array elements [3].Phased array systems utilize beam steering techniques to enhance the signal-to-noise ratio (SNR) and achieve spatial selectivity [4].
Phase shifter (PS) is one the most important elements in a phase array system.To facilitate beam steering, it is essential to have phase shifters at each Radio Frequency (RF) front-end.These phase shifters adjust the phase according to the control signal, enabling coverage of up to 360 degrees of phase adjustment.Fluctuations in gain and input/output reflection within different phase states affect channel quality.Moreover, when considering the number of channels, power consumption, and die size, a phase shifter must achieve a balance among phase resolution, die area, and input/output reflection to ensure optimal performance, efficiency, and cost [5].
The GaN (Gallium Nitride) process finds extensive application in high-power, highfrequency scenarios.Gallium Nitride (GaN), known for its higher breakdown strength, faster switching speed, enhanced thermal conductivity, and lower on-resistance, has led to the development of power devices that outperform their silicon-based counterparts [6,7].These attributes make GaN highly versatile in high-power, high-frequency applications.GaN-based phase shifters are currently in development, aiming for seamless integration into other RF circuits, particularly high-power amplifiers (PAs).These GaN-based phase shifters demonstrate exceptional characteristics, including high-power handling capacity, outstanding efficiency, and robust linearity [8][9][10].Phase shifters can be categorized into two main types: passive phase shifters [5,[11][12][13][14][15][16][17][18] and active phase shifters [19][20][21].Active phase shifters offer a signal gain advantage, but their gain stage must meet stringent linearity requirements in an RF front-end.While this linearity can be improved by increasing DC power consumption, it comes at the cost of reduced power efficiency.Active phase shifters rely primarily on a vector summing technique, and any phase or amplitude mismatches can significantly degrade their accuracy.Refs.describe vector sum phase shifters, which often exhibit high-power consumption [19][20][21].On the other hand, passive phase shifters have distinct advantages, including minimal power consumption and exceptional linearity.When integrated at the transmit/receive (TRx) points within a phased array system, their bidirectional capability can reduce the total number of required phase shifters through efficient sharing [22].However, it is worth noting that passive phase shifters may introduce some insertion loss and often require multiple bits to achieve the desired phase resolution.In conclusion, passive phase shifters are a suitable choice for high-power RF systems where linearity is critical.
The passive phase shifter (PS) can be categorized into several types: transmission line type [16], load-adjusted reflective type [17,18], all-pass network type [11], passive vector sum modulator [5], and switched filter type [12][13][14][15].Among these topologies, the transmission line type occupies a larger chip area due to considerations of wavelength.In contrast, the load-adjusted reflective type of passive PS boasts a compact design; however, its single-order structure places limits on achievable phase-shifting ranges.The all-pass network (APN) type showcases exceptional bandwidth performance in lower-frequency designs.The passive vector sum modulator (PVSPS) offers superior phase resolution.Nevertheless, its intricate structure and high insertion loss, attributed to the utilization of an X-attenuator, introduce significant drawbacks.Switched filter-type PS (STPS) has no limitations in phase shift range, is suitable for high-frequency applications, and features a simple structure.There is a concern regarding chip area because each phase shifting stage includes inductors.Unlike CMOS, compound processes such as GaN have a higher Q factor due to wider spacing between substrates and lower transmission loss.These characteristics facilitate the design and utilization of inductors [23][24][25].GaN processes are also suitable for the implementation of switch-filter type phase shifters due to the simplified structural design methods required due to constraints on available metal layers.
In this paper, we present a phase shifter designed for high-power phased array systems operating in the n260 (37~40 GHz) frequency band in line with the 5G NR standard.The designed phase shifter employs a structure and process suitable for high-power systems and consists of a 6-bit STPS (Switched-Type Phase Shifter) configuration.It has been finely tuned to minimize insertion loss and phase error.The phase shifter was fabricated and measured using a 150 nm GaN HEMT process.

Design of 6-Bits Switched-Type Phase Shifter
The switched-type phase shifter (STPS) operates by controlling multiple single-bit phase shifters (SBPS) using a digital control signal to achieve the desired overall phase adjustment.This involves arranging each SBPS in a series configuration.The STPS is built around a foundational 180 • SBPS circuit and requires multiple bits to achieve precise beam steering.However, limitations related to insertion loss and the physical size of each SBPS impact its configuration.Additionally, variations in performance and phase errors result from the phase control and the positioning of individual SBPS units.Consequently, a comprehensive design approach is necessary to consider all possible phase control states.
As depicted in Figure 1, the block diagram showcases a 6-bit phase shifter design.By arranging six SBPS units in series, spanning from 180 • to 5.625 • , a beam steering range of 360 • is attainable with a resolution of 5.625 • .The phase shifter's sequence is structured as 11.25 • /22.5 • /180 • /90 • /5.625 • /45 • .This order takes into account phase shifter performance and input/output return loss, and since the characteristics of 90 • and 180 • SBPS are sensitive, they are located in the center.and input/output return loss, and since the characteristics of 90° and 180° SBPS are sensitive, they are located in the center.A delay element used within the delay path can adopt an LC filter structure comprising T and Pi types.The choice was made to employ the LCL structure, forming a low-pass T-type filter, given its suitability for the relevant frequency band and implementation considerations.GaN HEMT processes offer the advantage of using inductors with high Q values and more than twice the inductance over the same length compared to CMOS processes.Consequently, opting for an LCL-based T-type filter is advantageous.To capture the influence of parasitic elements, electromagnetic (EM) simulations were conducted for the complete layout.
Figure 2 presents a schematic of an SBPS featuring a low-pass T-type filter, along with the corresponding equivalent circuit contingent upon the selected path.Transistor M1 is chosen to have a suitably low on-resistance in the bypass state, while the values of L1 and C1 are established to ensure the desired phase in the delay state, as determined by Equation ( 1).Transistors M2 and L2 are configured to either open or short node 'a' based on the selected state.
All SBPS units, except for the 180° configuration, were designed using a single filter.However, a single filter-based phase shifter is limited to achieve phase delay more than 90° [26].Therefore, two 90° phase shifters were arranged in series to achieve the 180° SBPS configuration. Figure 3 displays a photomicrograph of a phase shifter designed for the n260 (37-40 GHz) frequency band, manufactured utilizing the 150 nm GaAs HEMT process.The size of the phase shifter is 2.82 × 1.19 mm 2 , encompassing RF and DC pads.For phase shift control, the control voltage was applied through wire bonding to a printed circuit board (PCB).Furthermore, on-wafer measurements were conducted using a Ground-Signal-Ground (GSG) probe tip for RF signal.A delay element used within the delay path can adopt an LC filter structure comprising T and Pi types.The choice was made to employ the LCL structure, forming a low-pass T-type filter, given its suitability for the relevant frequency band and implementation considerations.GaN HEMT processes offer the advantage of using inductors with high Q values and more than twice the inductance over the same length compared to CMOS processes.Consequently, opting for an LCL-based T-type filter is advantageous.To capture the influence of parasitic elements, electromagnetic (EM) simulations were conducted for the complete layout.
Figure 2 presents a schematic of an SBPS featuring a low-pass T-type filter, along with the corresponding equivalent circuit contingent upon the selected path.Transistor M1 is chosen to have a suitably low on-resistance in the bypass state, while the values of L1 and C1 are established to ensure the desired phase in the delay state, as determined by Equation ( 1).Transistors M2 and L2 are configured to either open or short node 'a' based on the selected state.
and input/output return loss, and since the characteristics of 90° and 180° SBPS are sensitive, they are located in the center.A delay element used within the delay path can adopt an LC filter structure comprising T and Pi types.The choice was made to employ the LCL structure, forming a low-pass T-type filter, given its suitability for the relevant frequency band and implementation considerations.GaN HEMT processes offer the advantage of using inductors with high Q values and more than twice the inductance over the same length compared to CMOS processes.Consequently, opting for an LCL-based T-type filter is advantageous.To capture the influence of parasitic elements, electromagnetic (EM) simulations were conducted for the complete layout.
Figure 2  All SBPS units, except for the 180° configuration, were designed using a single filter.However, a single filter-based phase shifter is limited to achieve phase delay more than 90° [26].Therefore, two 90° phase shifters were arranged in series to achieve the 180° SBPS configuration. Figure 3 displays a photomicrograph of a phase shifter designed for the n260 (37-40 GHz) frequency band, manufactured utilizing the 150 nm GaAs HEMT process.The size of the phase shifter is 2.82 × 1.19 mm 2 , encompassing RF and DC pads.For phase shift control, the control voltage was applied through wire bonding to a printed circuit board (PCB).Furthermore, on-wafer measurements were conducted using a Ground-Signal-Ground (GSG) probe tip for RF signal.All SBPS units, except for the 180 • configuration, were designed using a single filter.However, a single filter-based phase shifter is limited to achieve phase delay more than 90 • [26].Therefore, two 90 • phase shifters were arranged in series to achieve the 180 • SBPS configuration.
Figure 3 displays a photomicrograph of a phase shifter designed for the n260 (37-40 GHz) frequency band, manufactured utilizing the 150 nm GaAs HEMT process.The size of the phase shifter is 2.82 × 1.19 mm 2 , encompassing RF and DC pads.For phase shift control, the control voltage was applied through wire bonding to a printed circuit board (PCB).Furthermore, on-wafer measurements were conducted using a Ground-Signal-Ground (GSG) probe tip for RF signal.
The control voltage is set to 0 V when the transistor is active and ranges from −2.5 V to −5 V when it is inactive.The characteristics of the off-state transistor vary depending on the control voltage.The minimum root mean square (RMS) phase error was attained when the control signal operated at −3 V. Since there was not a significant impact on the matching characteristics and insertion loss based on the off-state control voltage, we selected −3 V to minimize the RMS phase error.The control voltage is set to 0 V when the transistor is active and ranges from −2.5 V to −5 V when it is inactive.The characteristics of the off-state transistor vary depending on the control voltage.The minimum root mean square (RMS) phase error was attained when the control signal operated at −3 V. Since there was not a significant impact on the matching characteristics and insertion loss based on the off-state control voltage, we selected −3 V to minimize the RMS phase error.

Fabrication and Measurement
Figure 4 illustrates the input and output return loss (S11 and S22) of the fabricated STPS for various phase steps of each bit.The input return loss (S11) pertains to the input of the 11.25-degree phase shifter, while the output return loss (S22) pertains to the output of the 45-degree phase shifter.These results reveal that the return loss remains better than 10.7 dB across different phase states.Figure 5 displays the insertion loss (S21) of STPS for various phase states, including the insertion loss when delay paths from 0 to 180 degrees are added.Notably, as all phase shifters are transitioned into the delayed state, the insertion loss decreases, approaching a level closely resembling the simulation results.This behavior is primarily attributed to two factors.

Fabrication and Measurement
Figure 4 illustrates the input and output return loss (S11 and S22) of the fabricated STPS for various phase steps of each bit.The input return loss (S11) pertains to the input of the 11.25-degree phase shifter, while the output return loss (S22) pertains to the output of the 45-degree phase shifter.These results reveal that the return loss remains better than 10.7 dB across different phase states.Figure 5 displays the insertion loss (S21) of STPS for various phase states, including the insertion loss when delay paths from 0 to 180 degrees are added.Notably, as all phase shifters are transitioned into the delayed state, the insertion loss decreases, approaching a level closely resembling the simulation results.This behavior is primarily attributed to two factors.The control voltage is set to 0 V when the transistor is active and ranges from −2.5 V to −5 V when it is inactive.The characteristics of the off-state transistor vary depending on the control voltage.The minimum root mean square (RMS) phase error was attained when the control signal operated at −3 V. Since there was not a significant impact on the matching characteristics and insertion loss based on the off-state control voltage, we selected −3 V to minimize the RMS phase error.

Fabrication and Measurement
Figure 4 illustrates the input and output return loss (S11 and S22) of the fabricated STPS for various phase steps of each bit.The input return loss (S11) pertains to the input of the 11.25-degree phase shifter, while the output return loss (S22) pertains to the output of the 45-degree phase shifter.These results reveal that the return loss remains better than 10.7 dB across different phase states.Figure 5 displays the insertion loss (S21) of STPS for various phase states, including the insertion loss when delay paths from 0 to 180 degrees are added.Notably, as all phase shifters are transitioned into the delayed state, the insertion loss decreases, approaching a level closely resembling the simulation results.This behavior is primarily attributed to two factors.Firstly, the significant insertion loss, caused by the 90-degree and 180-degree bit bypass transistors, is a key contributor.This limitation stems from the utilization of smaller transistors in the 90-degree bit bypass circuit.Furthermore, the 180-degree bit comprises two 90-degree bits, amplifying its impact.Secondly, the modeling from the Process Design Kit (PDK) appears to have played a role.It is worth noting that we employed the transistor model provided by the PDK, initially designed up to 26.5 GHz, with discrepancies becoming more pronounced at higher frequencies.Additionally, the capacitors used in the delay circuit were based on the PDK model.Firstly, the significant insertion loss, caused by the 90-degree and 180-degree bit bypass transistors, is a key contributor.This limitation stems from the utilization of smaller transistors in the 90-degree bit bypass circuit.Furthermore, the 180-degree bit comprises two 90-degree bits, amplifying its impact.Secondly, the modeling from the Process Design Kit (PDK) appears to have played a role.It is worth noting that we employed the transistor model provided by the PDK, initially designed up to 26.5 GHz, with discrepancies becoming more pronounced at higher frequencies.Additionally, the capacitors used in the delay circuit were based on the PDK model.
However, the inductor, crucial for generating delay, was reasonably well-simulated through electromagnetic (EM) simulation.Moreover, since the delay circuit was constructed as an LCL network, the influence of the inductor was relatively significant.Consequently, the results obtained for the delay path closely aligned with the simulation.Figure 6a displays the measured phase response of the STPS across 64 phase steps.Figure 6b presents the simulated input 1-dB compression points for various phase steps of each bit.The simulation demonstrates an IP1dB exceeding 10 dBm within the operating frequency band.Notably, a substantial variation in IP1dB is observed in the 37~38 GHz. Figure 7a reveals that the measured and calculated RMS gain error falls within the range of 1.69 to 3.21 dB.Notably, it becomes evident that the variation in insertion loss is more significant at 37 GHz compared to 40 GHz, depending on the phase state.In Figure 7b, it is evident that the RMS phase error for the measured STPS is limited to less than 5.36°.Analyzing Figure 6a, it becomes apparent that each phase aligns after 38 GHz within the operating band.However, a notable observation is the non-constant phase spacing at 37 GHz.Considering the results presented in Figures 5-7, it suggests that the fabricated phase shifter shifted to a higher frequency band than initially targeted.However, the inductor, crucial for generating delay, was reasonably well-simulated through electromagnetic (EM) simulation.Moreover, since the delay circuit was constructed as an LCL network, the influence of the inductor was relatively significant.Consequently, the results obtained for the delay path closely aligned with the simulation.Figure 6a displays the measured phase response of the STPS across 64 phase steps.Figure 6b presents the simulated input 1-dB compression points for various phase steps of each bit.The simulation demonstrates an IP1dB exceeding 10 dBm within the operating frequency band.Notably, a substantial variation in IP1dB is observed in the 37~38 GHz. Figure 7a reveals that the measured and calculated RMS gain error falls within the range of 1.69 to 3.21 dB.Notably, it becomes evident that the variation in insertion loss is more significant at 37 GHz compared to 40 GHz, depending on the phase state.In Figure 7b, it is evident that the RMS phase error for the measured STPS is limited to less than 5.36 • .Analyzing Figure 6a, it becomes apparent that each phase aligns after 38 GHz within the operating band.However, a notable observation is the non-constant phase spacing at 37 GHz.Considering the results presented in Figures 5-7, it suggests that the fabricated phase shifter shifted to a higher frequency band than initially targeted.Table 1 presents a performance comparison between the fabricated phase shifter and previous studies.In contrast to other phase shifters, this study achieves a high resolution of 5.625°, good insertion loss per unit bit.Table 1 presents a performance comparison between the fabricated phase shifter and previous studies.In contrast to other phase shifters, this study achieves a high resolution of 5.625 • , good insertion loss per unit bit.

Conclusions
In this paper, a phase shifter was designed and fabricated to operate within the 5G NR standard n260 frequency range (37~40 GHz) using the 150 nm GaN HEMT process.The fabricated phase shifter is structured as a 6-bit switch filter, demonstrating impressive performance metrics: an RMS phase error of less than 5.36 degrees, an RMS gain error of under 3.21 dB, and a robust IP1dB exceeding 10 dBm.This high IP1dB value proves advantageous for seamless integration with high-power RF circuits.

Figure 2 .
Figure 2. Schematic of (a) single-bit phase shifter with low-pass T-type; (b) bypass state; (c) delay state.
presents a schematic of an SBPS featuring a low-pass T-type filter, along with the corresponding equivalent circuit contingent upon the selected path.Transistor M1 is chosen to have a suitably low on-resistance in the bypass state, while the values of L1 and C1 are established to ensure the desired phase in the delay state, as determined by Equation (1).Transistors M2 and L2 are configured to either open or short node 'a' based on the selected state.

Figure 2 .
Figure 2. Schematic of (a) single-bit phase shifter with low-pass T-type; (b) bypass state; (c) delay state.

Figure 2 .
Figure 2. Schematic of (a) single-bit phase shifter with low-pass T-type; (b) bypass state; (c) delay state.

Figure 5 .
Figure 5. Insertion loss due to delay.

Figure 5 .
Figure 5. Insertion loss due to delay.

Table 1 .
Performance Summary and Comparison with the State-of-the-Art Phase Shifters.