Probing the Electronic and Opto-Electronic Properties of Multilayer MoS2 Field-Effect Transistors at Low Temperatures

Transition metal dichalcogenides (TMDs)-based field-effect transistors (FETs) are being investigated vigorously for their promising applications in optoelectronics. Despite the high optical response reported in the literature, most of them are studied at room temperature. To extend the application of these materials in a photodetector, particularly at a low temperature, detailed understanding of the photo response behavior of these materials at low temperatures is crucial. Here we present a systematic investigation of temperature-dependent electronic and optoelectronic properties of few-layers MoS2 FETs, synthesized using the mechanical exfoliation of bulk MoS2 crystal, on the Si/SiO2 substrate. Our MoS2 FET show a room-temperature field-effect mobility μFE ~40 cm2·V−1·s−1, which increases with decreasing temperature, stabilizing at 80 cm2·V−1·s−1 below 100 K. The temperature-dependent (50 K < T < 300 K) photoconductivity measurements were investigated using a continuous laser source λ = 658 nm (E = 1.88 eV) over a broad range of effective illuminating laser intensity, Peff (0.02 μW < Peff < 0.6 μW). Photoconductivity measurements indicate a fractional power dependence of the steady-state photocurrent. The room-temperature photoresponsivity (R) obtained in these samples was found to be ~2 AW−1, and it increases as a function of decreasing temperature, reaching a maximum at T = 75 K. The optoelectronic properties of MoS2 at a low temperature give an insight into photocurrent generation mechanisms, which will help in altering/improving the performance of TMD-based devices for various applications.


Introduction
Owing to the success of synthesis and applications of graphene and graphene-based materials, the scientific community has started to explore the possibility of isolating 2D atomic layers from other layered materials to investigate fundamental physics in noncarbon-based 2D crystals as well as for developing them in future electronic and optoelectronic applications. Recent advances in this area have shown that several other materials, such as hexagonal boron nitride (h-BN), transition metal di-chalcogenides (TMDCs), including MoS 2 and WS 2 , and group III-VI layered semiconductors (e.g., GaSe, InSe, etc.), can be easily exfoliated from bulk crystals or grown using the CVD technique from a single to a few atomic layers [1][2][3][4]. In addition to the 2D structure, these materials also cover a wide range of the spectrum, from the insulator to semiconductors as far as the electrical properties are concerned [4][5][6][7]. For example, hexagonal B-N has a layered structure very similar to graphene, but with a very large band gap [5], whereas TMDs MX 2 (M=Mo, W, Re, etc.) have band gap ranges from 0.8 eV to 3 eV and tunable as a function of the number of layers [6]. Some of these crystals, such as MoS 2 , MoSe 2 , WS 2 , WSe 2 , etc., show indirect to direct band gap transition when they swift from a bulk to single-atomic-layer structure due to the quantum confinement effect [7]. On the other hand, InSe [8][9][10], ReS 2 [11], ReSe 2 [12] etc., show direct band gap independent to the number of layers. The magnitude of the band gap weakly depends upon the number of layers for ReS 2 , where single-layer ReS 2 shows a gap at 1.5 eV and 1.58 eV for monolayer [11]. Most of the TMDCs have moderate bandgap, which results in a higher ON/OFF current ratio exceeding 10 7 and small subthreshold voltage swing~70 mV/decade when exploited as FETs [13]. Apart from FET applications, semiconducting TMDCs also exhibit superior optoelectronic properties, which strongly depend on the number of layers [14]. Additionally, some TMDCs are also strongly correlated electronic materials, exhibiting properties like metal-insulator quantum phase transition, superconductivity, Mott insulator, etc. [15][16][17].
Among the several abovementioned TMDs, the most extensively studied TMD material is MoS 2, with thickness ranging from monolayer to several tens of layers [18]. Monolayer MoS 2 -based FET deices show electronic mobility 200 cm 2 ·V −1 ·s −1 along with a very high ON/OFF ratio of 10 8 [13]. Apart from FET applications, numerous studies show strong photo-response properties of 2D-MoS 2 -based photodetectors with high photo-responsivity and detectivity [19,20]. However, performances of thin MoS 2 -based photodetectors are mainly limited by low light absorption (5-10%) [20]. Further, most of the past studies are primarily focused on the room temperature as well as low-temperature electronic transport properties of either monolayer or bilayer MoS 2 -based devices. We have shown in our previous study using indium-selenide-based FET [9] that both the transport mechanism as well as key figures of the merits of an FET device fabricated using a 2D-layered material depends on the number of layers. Additionally, other factors such as surface-induced trap charges, defects inside the MoS 2 channel, etc., also result in detrimental photo-response properties, such as short carrier lifetime and persistent photoconductance [21]. In comparison, multilayer MoS 2 -based devices have several advantageous features, e.g., high density of states resulting in a high drive current as well as tunable electrical properties (n-type and p-type) [22]. However, multilayer MoS 2 -based FETs and corresponding photodetection properties have not been extensively studied. In this work, we have fabricated FET devices based on several-layers-thick MoS 2 and have systematically studied their electronic and photo-response properties. Multilayer MoS 2 FETs show n-type behavior with room-temperature electronic mobility~40 cm 2 ·V −1 ·s −1 . The electronic mobility increases by almost double~80 cm 2 ·V −1 ·s −1 at low temperatures. We further found that maximum photo-responsivity reaches up to~10 A/W at low temperatures while operating the FETs under the ON condition.

Synthesis and Device Fabrication
A few layers of MoS 2 were obtained using a mechanical exfoliation technique from commercially available bulk MoS 2 crystal (SPI Supplies). The exfoliated flakes/thin layers crystals were subsequently transferred on to a chosen substrate for device fabrication. For device fabrication, we chose a suitable MoS 2 flake. Using an optical microscope, a TEM square mesh grid (Electron Microscopy Sciences, Hatfield, PA, USA) was placed carefully on the top of the flake. This mesh grid works as a shadow mask for thermal deposition to put in direct electrical contacts. In this method, we do not use any photoresist or polymers and avoid further fabrication-process-related impurities which may lead to detrimental device performances [23]. After placing this shadow mask, the system was then mounted inside the thermal evaporator. We deposited Cr (10 nm)/Au (100 nm) for the contacts at the chamber pressure 10 −6 Torr. The height of the MoS 2 flake was measured using atomic force microscopy,~9-10 nm thick, which corresponds to~13-15 layers of MoS 2 . After deposition of the metal electrodes, the devices were annealed at a high temperature in an inert atmosphere.

Results and Discussion
Three terminal field-effect transistor (FET) measurements were performed on the as prepared MoS 2 devices (described in the previous section) under high vacuum~10 −6 Torr and at different sample temperatures 20 K ≤ T ≤ 280 K. To achieve the FET operation, a small d.c voltage (V d ) of 100 mV was applied between the source and drain contacts. The gate voltage was swept between −80 V and +80 V, and the corresponding drain-source currents (I d ) were recorded. The fabricated devices were initially used to measure the electrical properties at room temperature. Figure 1a shows the schematic of the device with a laser light illuminating the whole device from the top. Figure 1b shows the optical micrograph image containing the 9-10 nm thick MoS 2 device (inset). The channel length and width of the devices is~10 µm and~13 µm, respectively.

Results and Discussion
Three terminal field-effect transistor (FET) measurements were performed on the as prepared MoS2 devices (described in the previous section) under high vacuum ~10 −6 Torr and at different sample temperatures 20 K ≤ T ≤ 280 K. To achieve the FET operation, a small d.c voltage (Vd) of 100 mV was applied between the source and drain contacts. The gate voltage was swept between −80 V and +80 V, and the corresponding drain-source currents (Id) were recorded. The fabricated devices were initially used to measure the electrical properties at room temperature. Figure 1a shows the schematic of the device with a laser light illuminating the whole device from the top. Figure 1b shows the optical micrograph image containing the 9-10 nm thick MoS2 device (inset). The channel length and width of the devices is ~10 μm and ~13 μm, respectively. We used Keithley 2400 SMU to measure the drain-to-source current (Id) by biasing the drain-to-source voltage (Vd), while gate voltages were applied using another Keithley 2410 SMU. The drain-to-source current (Id) as a function of the drain-to-source voltage (Vd) at several gate voltages (Vg) is shown in Figure 1c. The Id-Vd data look linear despite the Schottky barrier between the MoS2 and Cr metal interface due to higher thermionic emission processes at room temperature. The low-temperature Id-Vd data are presented later in this section, which reveal that the metal-semiconductor contacts are indeed of We used Keithley 2400 SMU to measure the drain-to-source current (I d ) by biasing the drain-to-source voltage (V d ), while gate voltages were applied using another Keithley 2410 SMU. The drain-to-source current (I d ) as a function of the drain-to-source voltage (V d ) at several gate voltages (V g ) is shown in Figure 1c. The I d -V d data look linear despite the Schottky barrier between the MoS 2 and Cr metal interface due to higher thermionic emission processes at room temperature. The low-temperature I d -V d data are presented later in this section, which reveal that the metal-semiconductor contacts are indeed of Schottky type. Figure 1d shows the FET transfer characteristics of our MoS 2 device at 300 K temperature, showing I d as a function of V g at V d = 100 mV. A typical n-type transistor operation was observed with a threshold gate voltage (V th )~−60 V. The drain-source current I d reaches to the maximum saturation value of~2 µA for gate voltages, V g > 60 V and remains~10 nA for V g < −60 V. From this, we estimated the ON/OFF ratio to be~10 2 . The low ON/OFF ratio can be attributed to the higher thickness of the MoS 2 with a lower bandgap. The red line shows the linear fit of the I d -V g characteristics plot and was used to extract the field-effect mobility of the device using the MOSFET transconductance formula given below, where L is the channel length, W is channel width, and C is the capacitance per unit area of the gate dielectric. This n-type FET operation has been previously observed in many mechanically exfoliated single-layer MoS 2 devices. The field-effect electronic mobility was calculated from the linear region by using Equation (1) with an oxide layer thickness of 1000 nm. At 300 K, the field-effect mobility is~46 cm 2 ·V −1 ·s −1 . This mobility value is similar to the previously obtained room-temperature mobilities of multilayered MoS 2 devices [24] and higher than single-layer MoS 2 devices [13,15]. However, with appropriate contact engineering, these mobility values can be further improved [25][26][27][28].
This higher mobility is mainly due to the higher density of states and lower Schottky barrier/Ohmic contacts found in the case of our multilayer MoS 2 device. Figure 2a shows the low-temperature FET transfer characteristics at different temperatures. We have calculated the back-gated field-effect mobilities at different temperatures, keeping the source-drain voltage constant (100 mV), as shown in Figure 2b. The mobility increases further up to~80 cm 2 ·V −1 ·s −1 as the temperature reaches 50 K, which is generally attributed to reduced phonon scattering [29]. To further confirm the charge transport mechanism process in our MoS2 device plotted the natural logarithm of the conductance as a function of T −1/3 for different b gate voltages, as shown in Figure 2c. Here we found that the charge transport for our M device follows 2D VRH mechanisms, as given by Equation (2), over a wide range of The charge carrier transport in 2D semiconductors is mainly dependent on the carrier density or equivalently on the Fermi energy level E F [30][31][32][33]. When the charge carrier density is "very-low", the Fermi level E F lies in the bandgap region without any mobile carriers. In this case, the system remains in a disorder-driven strongly localized insulating phase. In the case of an n-type semiconductor, the application of a positive gate-bias moves the Fermi level towards the conduction band edge. This results in the generation of mobile electrons by filling up the localized states by thermal excitation. Further increment in the gate bias shifts the Fermi level above the mobility edge, and thus the band transport becomes more dominant. Finally, when the carrier density becomes "very-high", a strong apparent metallic phase is observed. At higher temperatures and at "very-high" doping level, the charge carrier transport is often influenced by the phonon effects and by shortand long-range scatterers, such as defects and charged impurities. The transition from the insulating state to the conducting state involves gradual progressive filling of the localized states or band edge disordered states arising from impurities and/or structural defects. At the intermediate carrier density level, charge carrier conduction occurs via the hopping of charge carriers through the localized states [34][35][36][37]. These type of conduction mechanisms can be described by the variable range hopping (VRH) model, which can be expressed by the following equation [34,38]: where the exponent γ = 1/(d + 1), d is the dimension of the system (d = 1 for 1D system and d = 2 for 2D systems), m = 0.8 is an empirical constant, T is the temperature, T0 is the characteristic temperature, and σ (n, T) is the 2D conductivity.
To further confirm the charge transport mechanism process in our MoS 2 devices, we plotted the natural logarithm of the conductance as a function of T −1/3 for different back-gate voltages, as shown in Figure 2c. Here we found that the charge transport for our MoS 2 device follows 2D VRH mechanisms, as given by Equation (2), over a wide range of temperatures 50 K ≤ T ≤ 300 K. These 2D VRH mechanisms further support mobility T −1/3 dependence, similar to the results found in monolayer MoS 2 devices [34].
In crystalline MoS 2 , the presence of a high density of localized states in the band-gap region leads to hopping transport when the Femi level moves through them upon changing the gate voltages. According to previous results [34], the physical origin of these localized states in MoS 2 films is connected to the random potential fluctuations from the trapped charges at the MoS 2 -SiO 2 interface. Since the screening of these trapped charges is relatively poor due to the large band gap of MoS 2 , a considerably long band tail thus exists from the interfacial traps which are randomly occupied during the processing of the device. For a 2D system with parabolic energy bands, if the main source of disorder arises from the randomly occupied interfacial traps, the scattering mechanisms are also expected to be dominated by charge impurity scattering [39]. This will further lead to: σ ∝ n (for screen coulomb impurity) (3a) σ ∝ n 2 (for bare Coulomb impurity) (3b) Therefore, to understand the scattering mechanism in our devices, we have plotted the conductance σ as a function of the change in the back-gate voltage (∆V g ) at different temperatures, as shown in Figure 2d. We found that for our MoS 2 devices towards the higher gate voltages, σ almost follows the power law expression σ~∆V g 2 for all different temperatures, which indicates scattering from almost unscreened charge impurities in our MoS 2 devices.

Optoelectronic Transport
The optoelectronic properties of MoS 2 FET were investigated by using a continuous wave laser with an illumination wavelength λ = 658 nm (E = 1.88 eV) and a spot size of 3 mm in diameter. A larger laser spot size helps reduces photo-thermal effects, such as the photo-thermoelectric effect, photo-bolometric effect, etc., as both contacts are illuminated alike [40]. Additionally, laser illumination intensity (P laser ) is scaled to an effective laser illumination intensity (P eff ) owing to a larger laser spot size as P eff = P laser × A device /A spot , where A device is the area of a device and A spot is the area of a laser spot. Room-temperature optoelectronic transport measurements of an MoS 2 FET are shown in Figure 3. A continuous laser was switched ON and OFF for an interval of~10 s, and the corresponding drain currents were measured. With the data shown in Figure 3a,b, it can be estimated that the decay response times of this device studied are very fast, perhaps of the order of a few seconds; however, due to the limitation of the measurement system, an accurate determination of this parameter was not possible. Photocurrents (I ph ) were estimated as a difference between the drain current under laser illumination (laser on) and the drain current under a dark current (laser off) as I ph = I d,laser ON − I d,laser OFF . The timedependent response of the photocurrent at V g = 0 V and various V g 's is shown in Figure 3a,b, respectively. It was observed that the photocurrent reverts to the drain current under dark conditions as soon as the laser is switched off, implying the presence of only a photoconductive/photogating effect. lifetime of minority charge carriers [43]. As light intensity increases, trap states gradually start filling up. At certain light intensities, all the trap states are filled, and a further increase in intensity will result in the generation of minority carriers that cannot be trapped. As a result of this, τm decreases, thus reducing the gain and the responsivity [43]. For MoS2 FET, a maximum R = 2 AW −1 at 300 K can be obtained at Peff = 0.02 μW and Vg = 40 V. When the gain > 1, quantum efficiency (η) is known as the external quantum efficiency (EQE) and is defined as EQE = R (h × c)/(e × λ) = R × 1240/λ. We found a maximum EQE of ~380% at Peff = 0.02 μW and Vg = 40 V. Temperature plays an important role in determining the strength of traps states. Thus, to emphasize the role of traps states on the photogeneration mechanism, we studied the optoelectronic properties at a low temperature (50 K < T < 300 K). Photocurrents at all studied temperatures show similar behaviors as that of those at room temperature. The The photocurrent (I ph ) extracted for three different applied gate voltages (V g = −40 V, 0 V, 40 V) is plotted as the function Peff in log-log scale, as shown in Figure 3c. The photocurrent follows power law dependence on the effective laser illumination intensity as I ph ∝ (P eff ) γ . The value of the exponent is 0 ≤ γ ≤ 1, indicating the presence/absence of trap states in FET. In the absence of trap states, the exponent, γ = 1, and photocurrent generation mechanism follow a pure photoconductive effect. In the presence of trap states, the exponent becomes fractional (γ < 1) and the photocurrent mechanism manifests into a trap-dominated photoconductive effect, commonly known as the photogating effect. It should be noted that crossover of a photo generation mechanism from photoconductive to photogating because of an increased applied gate voltage has been observed in various 2D materials, such as In 2 Se 3 [40], CuIn 7 Se 11 [41], and ReSe 2 [42], which indicates that trap states can be modulated. However, the fractional value of γ for all gate voltages (in Figure 3c) indicates that the trap states in MoS 2 FET have a strong influence on the optoelectronic properties of MoS 2 FETs.
The photo-responsivity (commonly known as responsivity) of a phototransistor can be estimated by R = I ph /P eff . The responsivity as a function of P eff in log-log scale for three different applied gate voltages is shown in Figure 3d. In the case of a pure photoconductiongenerated photocurrent (where photoconductive gain is absent), responsivity will have an upper limit, given by R = (η × e × λ)/(h × c) = η × λ/1240, where η is the quantum efficiency, e is the electron charge, h is the plank's constant, and c is the speed of light [43,44]. For a laser with λ = 658 nm, a maximum R of 0.53 A W −1 can be achieved for η = 1 (100% conversion). For MoS 2 FET, responsivity values greater than 0.52 (as seen in Figure 3d) indicate that the gain > 1. Gain can be estimated as τ m /τ d , where τ m is the minority carrier lifetime and τ d is the carrier drift or transit time [45]. For gain > 1, τm > τd, which means that minority carriers are immobile and trapped. This results in a trap-dominated photoconductive effect. As seen in Figure 3d, the responsivity decreases as the effective laser intensity increases, and this could be attributed to a decrease in the average carrier lifetime of minority charge carriers [43]. As light intensity increases, trap states gradually start filling up. At certain light intensities, all the trap states are filled, and a further increase in intensity will result in the generation of minority carriers that cannot be trapped. As a result of this, τ m decreases, thus reducing the gain and the responsivity [43]. For MoS 2 FET, a maximum R = 2 AW −1 at 300 K can be obtained at P eff = 0.02 µW and V g = 40 V. When the gain > 1, quantum efficiency (η) is known as the external quantum efficiency (EQE) and is defined as EQE = R (h × c)/(e × λ) = R × 1240/λ. We found a maximum EQE of~380% at P eff = 0.02 µW and V g = 40 V.
Temperature plays an important role in determining the strength of traps states. Thus, to emphasize the role of traps states on the photogeneration mechanism, we studied the optoelectronic properties at a low temperature (50 K < T < 300 K). Photocurrents at all studied temperatures show similar behaviors as that of those at room temperature. The time-dependent response of the photocurrent (at various V g 's) measured at the lowest temperature is shown in Figure 4a, and the photocurrent reverts to the drain current under the dark condition as soon as the laser is switched OFF. Responsivity is a function of P eff at constant V g = 40 V, and all the temperature studies are shown in Figure 4b. Responsivity increased as temperature decreased, indicating strong trapped states.
Peff at constant Vg = 40 V, and all the temperature studies are shown in Figure 4b. Responsivity increased as temperature decreased, indicating strong trapped states. The temperature dependence of γ and R is shown in Figure 4c,d, respectively. It is observed that as temperature decreases, gamma decreases, and, correspondingly, responsivity increases for all the studied gate voltages (Vg's). A strong dependence of γ and R have been observed in various 2D-materials-based FETs, and this was studied in detail in the case of ReSe2 [42]. A clear correlation between R and γ was observed, where lower γ corresponds to higher R. These parameters are determined by trap states, and these traps can be modulated by temperature and gate voltages. In a semiconductor where the steadystate Fermi level is away from the valence band, this results in mid-gap states being available for trapping. Lowering the temperature results in carrier freeze out and strongly trapped minority carriers, resulting in a strong photogating effect. Thus, responsivity increases at lower temperatures.

Conclusions
In conclusion, here we have presented the detailed temperature-dependent electronic and optoelectronic properties of few-layers MoS2 FETs. Our MoS2 FETs show mobility μFE ~40 cm 2 ·V −1 ·s −1 at room temperature and 80 cm 2 ·V −1 ·s −1 below 100 K. The temperature-dependent (50 K < T < 300 K) photoconductivity measurements show the room-temperature photoresponsivity (R) to be ~2 AW −1 , and this increases as a function of decreasing temperature. Photoconductivity measurements indicate a fractional power dependence on The temperature dependence of γ and R is shown in Figure 4c,d, respectively. It is observed that as temperature decreases, gamma decreases, and, correspondingly, responsivity increases for all the studied gate voltages (V g 's). A strong dependence of γ and R have been observed in various 2D-materials-based FETs, and this was studied in detail in the case of ReSe 2 [42]. A clear correlation between R and γ was observed, where lower γ corresponds to higher R. These parameters are determined by trap states, and these traps can be modulated by temperature and gate voltages. In a semiconductor where the steady-state Fermi level is away from the valence band, this results in mid-gap states being available for trapping. Lowering the temperature results in carrier freeze out and strongly trapped minority carriers, resulting in a strong photogating effect. Thus, responsivity increases at lower temperatures.

Conclusions
In conclusion, here we have presented the detailed temperature-dependent electronic and optoelectronic properties of few-layers MoS 2 FETs. Our MoS 2 FETs show mobility µ FE~4 0 cm 2 ·V −1 ·s −1 at room temperature and 80 cm 2 ·V −1 ·s −1 below 100 K. The temperature-dependent (50 K < T < 300 K) photoconductivity measurements show the room-temperature photoresponsivity (R) to be~2 AW −1 , and this increases as a function of decreasing temperature. Photoconductivity measurements indicate a fractional power dependence on the steady-state photocurrent, indicating trap-controlled optoelectronics properties. Understanding the optoelectronic properties of MoS 2 at low temperatures will help in altering/improving the performance of TMD-based devices for various applications. Further, these studies may lead to the development of broadband photodetectors, as shown