Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.


Introduction
The technology of 2D planar scaling is now facing major limitations, and in order to extend the semiconductor roadmap, 3D sequential integration, which consists of stacking transistors on top of each other, has been envisioned [1,2]. As its name suggests, transistor layers are processed sequentially, i.e., the top tier is processed and stacked above the already fabricated bottom tier in 3D sequential integration. This technology can enhance circuit density and functionality without the requirement of further reduction in device dimensions. To maintain the integrity of what is below, namely the bottom devices, interconnections and bonding interface, the thermal budget for top-tier fabrication is required to be no more than 550 • C [3][4][5].
However, source/drain (S/D) activation is typically performed by spike annealing at high temperature (≥1000 • C). Decreasing thermal budget will impair CMOS device performance. Much work has been undertaken to circumvent the thermal budget limitation. For instance, nanosecond laser annealing (NLA) [6] and solid-phase epitaxial regrowth (SPER) [7] were used to activate S/D as the alternatives to high-temperature spike annealing and low-temperature materials, such as poly-Si [8,9], Ge [10,11], III-V [12,13] and transparent amorphous oxide [14,15] were implemented to replace monocrystalline Si as the channel of top-tier devices. Particularly interesting is the exploration of junctionless MOSFETs as the top-tier devices with the elimination of S/D activation [16,17]. Even though impressive device performances have been achieved with such approaches, there remain several issues. NLA and SPER often incur high process cost and low throughput, and low-temperature materials are not fully compatible with current Si technology, leading to a risk of poor yield at a large scale. Additionally, junctionless devices need an extra-high-temperature (≥1000 • C) annealing to activate the channel before the top silicon layer transfer, which is likely to induce mobility degradation and threshold voltage (V TH ) variation. Hence, low-temperature devices based on Si technology may be further developed.
Schottky S/D MOSFETs, using metal silicide to replace doped silicon as S/D [18], hold an inherent superiority in process thermal budget over the conventional and junctionless devices, with no need of a standard high-temperature annealing to activate S/D and channel. Therefore, in this work, low-temperature complementary Schottky S/D FinFETs are processed at a temperature as low as 500 • C, and the electrical characteristics are investigated to evaluate the feasibility of being used as the top-tier logic devices in 3D sequential technology. To our knowledge, previous investigations on Schottky S/D devices have been mostly focused on short-channel effects, with the fabrication thermal budget never lower than 600 • C [19][20][21][22][23][24]. This is the first demonstration of complementary S/D FinFETs with all process steps below 500 • C toward 3D sequential integration.

Device Fabrication
The process flow of Schottky S/D FinFETs is summarized in Figure 1a. SOI wafers measuring 200 mm with top Si of 40 nm and BOX of 145 nm were used as the starting materials to mimic the bonded substrate of top-tier devices. The replacement metal gate (RMG) process was adopted, and all process steps were set below the typical thermal budget of 550 • C for compatibility with 3D sequential integration [3][4][5]. According to the principle of Schottky S/D MOSFETs [18], the electrical property is primarily determined by the Schottky junction barrier between S/D and channel. In order to realize high performance, a doped source/drain extension (SDE) to lower the Schottky junction barrier, illustrated in Figure 1b, was first explored for pFinFETs by two methods, i.e., SDE first (SDE 1st ) and SDE last (SDE last ). In the SDE 1st scheme, SDE implantation was performed before the spacer and followed by silicidation annealing, and SDE was formed by dopant segregation at the silicide/Si interface during silicidation. In contrast, SDE implantation was performed after silicide formation in the SDE last scheme, and an additional rapid thermal annealing (RTA), also named drive-in annealing, was used to drive the dopant to segregate at the silicide/Si interface, forming SDE. An amount of 3 nm Ni was deposited by sputtering, and B 1.5 keV 2 × 10 15 cm −2 was implemented for SDE implantation in both schemes. A split, shown in Table 1, was further performed to investigate the impact of the SDE process thermal budget on device performance. Afterwards, the process flow of complementary Schottky S/D FinFETs was developed with optimal SDE engineering. Gate stacks of HfO 2 /TiN/TaN and HfO 2 /TiAl/TiN were separately applied to pFinFETs and nFinFETs for V TH adjustment. The fabrication was completed with tungsten contact plug and Al metallization. Conventional pFinFETs, with and without silicide, were also fabricated with a standard high-temperature (≥1000 • C) process flow ( Figure 1c) for comparison. It is worth noting that 8-inch industrial equipment was used for the fabrication in our experiment, and the process uniformity of within wafer, wafer-to-wafer and lot-to-lot was controllable and reproducible. Current-voltage measurements (112 measurement sites for each wafer) were performed using a HP4156 parameter analyser.

SDE Engineering
To develop the optimal SDE process, SDE engineering, shown in Table 1, was performed on pFinFETs. The I DS -V GS characteristics of the Schottky S/D pFinFETs with three SDE processes are noted in Figure 2a [25]. The R S/D measurements at V GS = −0.8 V were about 6.31 kΩ/µm, 8.71 kΩ/µm and 2.46 kΩ/µm for the devices with 310 • C SDE 1st , 450 • C SDE last and 550 • C SDE last processes, respectively. Such high R S/D values are ascribed to the nano-fins scheme and to insufficiently silicided S/D, as uncovered in Figure 4. Due to the ultrathin Ni of 3 nm, about 16 nm of silicide was formed, and yet around 24 nm silicon remained unsilicided. Figure 5a further shows the I ON dependence on the SDE process thermal budget, which is involved with the annealing steps in Table 1. It should be noted that the heating-up and cooling-down periods of an annealing process are ignored when defining a thermal budget. It was revealed that lowering the SDE process thermal budget degraded I ON in the SDE last scheme; it seems that SDE 1st prevails over SDE last in driving capability at a lower thermal budget level.   Correlating the electrical results with SDE engineering, two main findings can be made. First, SDE 1st holds the advantage in I ON at a lower thermal budget level, which results from the larger gate-to-SDE overlap (L SDE, OL ), by performing SDE implantation before the spacer, as illustrated in Figure 5b. The reduced V TH of −0.13 V, larger I OFF of 0.39 nA/µm and lower R S/D of 6.31 kΩ/µm for 310 • C SDE 1st , with reference to 450 • C SDE last , justify this point, which was performed with the same silicidation annealing. Second, in the SDE last scheme, increasing the thermal budget will lower R S/D, and thus improve I ON . The lowered R S/D is probably attributable to the reductions in silicide resistance and injection resistance (Figure 5b). It is known that an Ni/Si solid state reaction forms high-resistance Ni 2 Si at 250-400 • C and low-resistance NiSi at 400-700 • C [26]. With the raising of silicidation annealing from 310 • C to 500 • C for 450 • C SDE last and 550 • C SDE last (Table 1), the sheet resistance of Ni silicide decreases from around 457 Ω to 123 Ω, measured with a four-point probe system. Additionally, it has been demonstrated that increasing drive-in annealing will boost dopant segregation at the silicide/Si interface, leading to an enhanced Schottky junction barrier lowering [27][28][29]. Since the injection resistance is proportional to the Schottky junction barrier, its reduction can be expected for 550 • C SDE last with respect to 450 • C SDE last , with drive-in annealing at 550 • C for the former and 450 • C for the later. One may argue that the mobility could differ with SDE process thermal budget, affecting device performance. Since no channel doping was performed for Schottky devices and all samples were tested at 300 K, it is supposed that the mobility was almost the same and the difference in I DS -V GS characteristics in Figure 2 was primarily caused by R S/D and V TH .

Low-Temperature Schottky S/D FinFETs vs. Conventional High-Temperature FinFETs
In accordance with the findings in Section 3.1, the fabrication of complementary Schottky S/D FinFETs with optimal SDE engineering was developed toward 3D sequential integration. The thickness of Ni was increased from 3 nm to 6 nm and 5% Pt. was added, and a two-step RTA (310 • C 60 s + selective etch + 500 • C 10 s) method was explored for silicide formation so as to avoid abnormal Ni diffusion [30,31]. Meanwhile, the drive-in annealing was further reduced from 550 • C 60 s to 500 • C 60 s for better compatibility with 3D sequential integration. Figure 6 shows the I DS -V GS characteristics of the complementary Schottky S/D FinFETs with L G = 500 nm. The I ON and I ON /I OFF ratios for pFinFETs were 76.07 µA/µm and 7 × 10 5 , and those for nFinFETs were 48.57 and 1 × 10 6 µA/µm, at V DS = ±0.8 V. The corresponding V TH values were around −0.16 V and 0.3 V. Clearly, with S/D fully silicided as confirmed by XTEM images (not shown), an improvement in I ON was achieved for pFinFETs due to the reduced R S/D . A comparison was made between low-temperature Schottky S/D pFinFETs and conventional pFinFETs fabricated with a standard high-temperature (≥ 1000 • C) process flow ( Figure 1c). As shown in Figure 7a, with silicide formation, the I ON of conventional pFin-FETs is significantly improved. Since no shift of V TH was evidenced with silicide (Figure 7c), the I ON improvement is primarily attributable to the decrease in R S/D from 29 kΩ/µm to 2 kΩ/µm (Figure 7b). The low-temperature Schottky S/D pFinFETs exhibited higher I ON than the conventional high-temperature devices, whether they were with (w/) or without (w/o) silicide, owing to the lower R S/D (Figure 7b) and V TH (Figure 7c). As compared to the conventional device, the Schottky S/D device using silicide as S/D holds an inherent advantage in R S/D, and its fabrication is fully compatible with current Si technology; competitive performance can be obtained with a 500 • C drive-in annealing to form SDE; moreover, no annealing at ≥1000 • C is needed to activate the channel with respect to a junctionless device [16,17]. Hence, it is indeed feasible to adopt Schottky S/D FinFETs as the top-tier devices in 3D sequential technology.

Inverter Characterization
The CMOS inverter voltage transfer characteristics (VTC) at V DD ranging from 0.3 V to 1 V by step of 0.1 V are presented in Figure 8a. The source of Schottky S/D NMOS was connected to the ground potential, while the source of Schottky S/D PMOS was attached to V DD . Both transistors shared the silicided drain contact forming the output terminal of inverter V OUT , as illustrated in Figure 1b. Well-behaved VTC was obtained, with a low-tohigh output dynamic that reached rail-to-rail supply voltage range. This indicates that the subthreshold leakage currents of both transistors were sufficiently low to not degrade high and low logic states. It is noted that the transition of the inverter VTC was not located at V DD /2, due to the uncompensated asymmetry of V TH between pFinFETs and nFinFETs ( Figure 6). The transition of the inverter VTC was shifted by the same amount of about 0.14 V. A gate metal work function adjustment could be applied to optimize V TH symmetry to further improve the inverter VTC. Almost a constant voltage gain (∆V OUT /∆V IN ) of 18 v/v was achieved at V DD in the range of 0.3 V~0.8 V (Figure 8b), suggesting a great potential of our inverter in low-power and high-performance 3D sequential integration. In order to estimate the noise margin (NM), a piecewise approximation of the VTC was used here to determine the boundary of the transition zone. As illustrated in Figure 9a

Conclusions
In conclusion, low-temperature complementary Schottky S/D FinFETs were proposed as the top-tier devices for 3D sequential integration and were experimentally demonstrated in this work. The thermal budget for fabrication was no more than 500 • C. and the entire process flow was fully compatible with current Si technology. With optimal SDE engineering and competitive I ON values of 76.07 µA/µm and 48.57 µA/µm, I ON /I OFF ratios of 7 × 10 5 and 1 × 10 6 at V DD = 0.8 V were obtained for pFinFETs and nFinFETs, respectively. Excellent CMOS inverter and functional CMOS RO are successfully explored, offering a new method of high-performance 3D VLSI CMOS integration.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author.