Synergy of Electrostatic and Chemical Doping to Improve the Performance of Junctionless Carbon Nanotube Tunneling Field-Effect Transistors: Ultrascaling, Energy-Efficiency, and High Switching Performance

The low on-current and direct source-to-drain tunneling (DSDT) issues are the main drawbacks in the ultrascaled tunneling field-effect transistors based on carbon nanotube and ribbons. In this article, the performance of nanoscale junctionless carbon nanotube tunneling field-effect transistors (JL CNTTFETs) is greatly improved by using the synergy of electrostatic and chemical doping engineering. The computational investigation is conducted via a quantum simulation approach, which solves self-consistently the Poisson equation and the non-equilibrium Green’s function (NEGF) formalism in the ballistic limit. The proposed high-performance JL CNTTFET is endowed with a particular doping approach in the aim of shrinking the band-to-band tunneling (BTBT) window and dilating the direct source-to-drain tunneling window, while keeping the junctionless paradigm. The obtained improvements include the on-current, off-current, ambipolar behavior, leakage current, I60 metric, subthreshold swing, current ratio, intrinsic delay, and power-delay product. The scaling capability of the proposed design was also assessed, where greatly improved switching performance and sub-thermionic subthreshold swing were recorded by using JL CNTTFET with 5 nm gate length. Moreover, a ferroelectric-based gating approach was employed for more enhancements, where further improvements in terms of switching performance were recorded. The obtained results and the conducted quantum transport analyses indicate that the proposed improvement approach can be followed to improve similar cutting-edge ultrascaled junctionless tunnel field-effect transistors based on emerging atomically thin nanomaterials.


Introduction
Sub-thermionic subthreshold swing provided by nanoscale-tunnel field-effect transistors (TFETs) enables a decrease in power supply voltage, which is a prerequisite in ultralow power applications, such as the internet of things (IoT) [1,2]. In the last decade, the great progress experienced in nanomaterials science have given an additional asset and new Figure 1a shows the three-dimensional (3D) structure of the junctionless-carbonnanotube-tunneling field-effect transistor (JL CNTTFET). The shape of the nanodevice follows the cylindricity of the carbon-nanotube channel, and, thus, coaxial gates are considered accordingly. Note that the gate-all-around (GAA) configuration is found to be more efficient in terms of controlling the carrier transport [21,22]. In addition, the GAA structure really supports the assumption of uniform electrostatics in radial direction, thus making the simulation less complex [22]. In this work, a small CNT diameter was used, due to its appropriateness in terms of device electrical performance. Figure 1b shows the lengthwise-cut view of the uniformly doped JL CNTTFET. As shown, the tunneling FET is endowed with an auxiliary gate (P-gate) to electrostatically p-type dope the source side in order to preserve the junctionless aspect on CNT channel while achieving the tunneling FET operating regime [9]. As we can see, the control-gate at the middle of the device governs the FET carrier transport, while the drain side is left undoped. The Hafnium oxide (HfO 2 ) is considered to be a gate dielectric surrounding the zigzag CNT (Z-CNT). Figure 1c shows the doping profile of the conventional JL CNTTFET, which is uniformly n-type doped from source to drain electrodes. Figure 1d shows the cross-sectional view of the proposed engineered doping (ED)-based design, EDJL CNTTFET. As shown, this latter design is similar to the baseline design shown in Figure 1b, with the exception of three differences. The first is a heavily n-type doped pocket (HDP), which is located between the two coaxial gates with α concentration [23], the second is a lightly n-type doped portion (LDP) near the drain with β concentration, and the third is an electrical p-type doping gate with a tunable applied bias that aims to match the synergy. Figure 1e shows the doping profile of the proposed JL CNTTFET, showing the heavily n-type doped pocket between the P-G and C-G gates and the LDP near the drain electrode. From a fabrication point of view, the proposed non-uniform doping profile can be reached by tuning the exposure time of the concerned CNT portions to the employed chemical dopant and thus varying the doping level as required [13,22]. All physical, electrical, and geometrical design parameters are shown in Table 1. Note that the physical backgrounds and reasons for the adopted chemical and electrical doping and their locations are discussed thoroughly in Section 4.

Simulation Approach
In the literature, the common quantum simulation method used to propose, investigate, and assess advanced nanoscale CNTFETs with full soundness and high accuracy is the selfconsistent computation between the non-equilibrium Green's function formalism and the Poisson equation [22][23][24][25]. The main assets of this quantum simulation method are its ability to consider most of electrostatic features and the main quantum transport phenomena, including the band-to-band and direct source-to-drain tunneling mechanisms [22][23][24][25][26]. For this reason, we adopted the NEGF simulation in the present computational work. The retarded Green's function is the main equation on which this quantum simulation is based, and it can be expressed in the following matrix form [26] where E, η + , H PZ , I, and Σ S(D) are the energy, infinitesimal positive value, Hamiltonian matrix based on the atomistic nearest neighbor p Z -orbital tight-binding approximation, identity matrix, and the source (drain) self-energy, respectively. In our computation, the mode space (MS) representation is employed to avoid the computational burden while considering only the relevant modes and the ballistic limit conditions [27]. Note that the source (drain) self-energy is analytically computed in accordance with the MS computational fashion [22,27]. The computation of the retarded Green's function and the S/D self-energies allows us to compute the source (drain) local density of states (LDOS), D S(D) , using the following expressions [22] D S(D) = GΓ S(D) G † with where Γ S(D) denotes the energy level broadening due to the S/D contact. Now, the channel charge density is within reach, using the following equation [22]: where q, sgn, E N , f, and E FS(FD) are the electron charge, sign function, charge neutrality level, Fermi function, and S/D Fermi level, respectively. In the self-consistent computation, computing the charge-density Equations (1)-(4) needs information on the on-site electrostatic potential, which is approximated by solving the Poisson equation for cylindrical nano-FET structure given by the following equation [22,27]: where U, ε, and ρ are the potential distribution, the dielectric constant, and the Z-CNT charge density, including the chemical doping concentration, respectively. The Poisson equation is solved by using the finite difference method, while assuming that the potential is invariant in the coaxial direction. The Dirichlet boundary conditions are imposed on the gates' nodes, considering the relevant biases, while the Neumann boundary conditions are considered for the remaining external interfaces, including the source and drain electrodes [22,27]. After attaining the self-consistency between the Poisson solver and the MS NEGF solver, the drain current is within reach by using the following equation [22]: whereh is the Planck's constant, and T(E) is the transmission coefficient, which can be computed as follows [22]: where Tr denotes the trace operator. All NEGF simulations were performed by using MATLAB software. For more information and details regarding the NEGF-based quantum mechanical simulation of nanoscale carbon-nanotube FETs, we refer to our previous relevant works [24,25,28,29], where the validation of the used NEGF simulation against some experimental and theoretical data was reported.

Results and Discussion
The nanoscale tunneling FETs are promising nanodevices, due to their assets, namely sub-thermionic subthreshold swing, low-off current, and intriguing scaling capability. However, the low on-current is considered the main disadvantage in these promising nano-FETs. Thereafter, we show interesting improvements in on-current, off-current, and subthreshold swing, using the synergy of both chemical and electrical-doping techniques, while keeping the junctionless paradigm. Figure 2a shows how the increase in doping concentration of the heavily n-type doped pocket boosts the on-current of the JL CNTTFET. When inspecting the same figure, we can observe that the off-current is also slightly improved with the N HDP increase. The recorded off-current (on-current) improvement is principally attributed to the dilation (shrinking) in the DSDT (BTBT) window induced by the heavily doped pocket. Figure 2b shows that the recorded improvement in on-current, using the heavily doped pocket, can be further enhanced by increasing negatively the applied voltage of the auxiliary p-gate that ensures the source p-type doping electrostatically. We can also see that a slight increase in off-current is recorded, while the ambipolar behavior is still the same. The recorded additional improvement in on-current is logically attributed to an additional shrinking in the BTBT window that is induced by the negatively high p-gate voltage. Therefore, in order to increasingly boost the on-current, it is appropriate to combine the HDP technique with that of the negatively high p-gate voltage. In order to decrease the off-current (increased with increasing the negative p-gate voltage as shown in Figure 2b) and improve the subthreshold swing, we adopted, in addition, a lightly doped portion to dilate the direct source-to-drain tunneling window, while keeping the junctionless paradigm. As expected, Figure 3a explicitly shows significant improvements in terms of on-current, off-current, subthreshold swing, and ambipolar behavior, in comparison to the conventional JL CNTTFET. We can clearly see the steep switching of the transfer characteristic, which is a highly desired feature in cutting-edge high-performance digital applications. Figure 3b shows the subthreshold swing in function with the drain current for the conventional and proposed nanoscale TFETs. This indicates that the drawn curves are important and informative, because they reveal the minimum SS on the one hand and the values of SS over the transfer characteristics on the other hand. The same figure also highlights the I 60 factor, which denotes the highest drain current at which SS = 60 mV/dec is recorded. Note that the ideal region of the I 60 metric in the plot is on the lower right corner, with a steep SS and high drain currents [30]. As shown, the performance of the proposed design is closest to the aforementioned region of interest, with a higher I 60 factor in comparison to the baseline TFET. In addition, the proposed JL-CNTTFET exhibits a steeper SS than the conventional TFET over the considered I DS range, and, thus, the average SS of the proposed JL-CNTTFET is smaller than that of the conventional one. It is worth noting that the proposed (conventional) design provides a minimum SS value of~19 mV/dec (~33 mV/dec), as indicated in Figure 3a.  Figure 4 shows the potential distribution drawn from the converged Poisson's solutions at the lengthwise-cut region. The electrostatic gating of the p-gate and the main gate is clearly seen. More important, we can see in Figure 4a that the longitudinal potential variation between the two aforementioned electrostatic-gating examples (at the level of the ungated region, framed by a discontinued line) is somewhat wide, while reflecting the long BTBT window responsible for the low on-current. However, by using the V PG adjustment and heavily n-type doped pocket, we can observe a steep longitudinal potential variation at the BTBT region, as shown in Figure 4b. In this latter example, it is also clearly seen the dilation in the DSDT window that is induced by the lightly n-type doped portion near the drain, making the nano-TFET more immune to the DSDT leakage, contrary to the conventional case.  Figure 5 shows how the band diagrams are tuned by using the chemical-and electricaldoping techniques in order to improve the low on-current, which is among the main drawbacks in nanoscale TFETs. In Figure 5, the top (bottom) solid line is the edge of conduction (valence) band edge, E C (E V ). We can clearly see in all figures that the edge of the conduction band underneath the gate is below the edge of the source valence band, while allowing a band-to-band tunneling mechanism that results in the on-current in tunneling FETs. This indicates that the direct source-to-drain tunneling can also contribute to the BTBT on-current, especially in TFET with ultra-scaled gate lengths, where the DSDT leakage becomes a concern. In Figure 5a, we can clearly see that the BTBT window indicated by two arrows is somewhat long, leading to low TFET on-currents. In Figure 5b, we can see the HDP-induced band lowering, which shrinks the BTBT window while increasing the BTBT components and making the on-current higher, as shown in Figure 2a. It is worth noting that the shorter (longer) BTBT window provides a higher (lower) on-current [18]. The inspection of Figure 5b also reveals a slight dilation in the DSDT window, due to the HDP-induced band lowering, while also explaining the recorded decrease in off-current shown in Figure 2a. Figure 5c shows that the BTBT window becomes somewhat shorter by increasing the p-gate voltage, and, thus, the BTBT on-current is boosted accordingly. Note that the negative increase in p-gate voltage also decreases the DSDT window, leading to the increase in off-current, as recorded in Figure 2b. For more clarification, Figure 5d is plotted to graphically show how the synergy of the HDP-based technique and the P-G voltage adjustment increasingly shrinks the BTBT window responsible for the on-current increase. In fact, the negative increase in P-gate voltage induces a band elevation at the level of source region, as shown in the same figure. Therefore, geometrically, the V PG adjustmentinduced band elevation, together with the HDP-induced band lowering, shrinks the BTBT window more and more, making it shorter, while clearly explaining the additional increase in on-current recorded in Figure 2b.  Figure 6 shows the energy-position-resolved current spectrum drawn from the NEGF quantities for the JL CNTTFETs under investigation. We can see in Figure 6a the bandto-band tunneling from source valence band to the drain conduction band through the BTBT window. In Figure 6b, we can clearly see that the BTBT on-current spectrum becomes higher than that of conventional JL CNTTFET, due to the HDP-induced band lowering that shrinks the BTBT window. Figure 6c obviously shows that the synergy of the p-gate voltage adjustment and heavily doped pocket approaches causes an additional increase in BTBT on-current spectrum (in comparison to other cases), due to the recorded additional shortening in BTBT window, as previously explained and shown in Figure 5.  Figure 7 shows the role of the lightly n-type doped ZCNT region near the drain in dilating the direct source-to-drain tunneling window responsible for the tunneling leakage current in ultrascaled TFETs. As shown in Figure 7a, the DSDT window of the JL CNTTFET without the lightly n-type doped pocket is somewhat short (~14 nm), leading to a higher leakage current or, equivalently, a higher DSDT current; thus, a high off-state is recorded, as shown previously in Figure 2. Figure 7b clearly shows the LDP-induced dilation in the DSDT window by elevating the concerned bands via the lightly doped pocket. Please note that this LDP-induced dilation in the DSDT window explains the recorded improvement well in the off-current, I 60 factor, and sub-thermionic subthreshold swing, as shown above in Figure 3.  Figure 8a shows the electron-density distribution throughout the JL CNTTFET, without considering the lightly n-type doped pocket near the drain electrode. We can see that the direct source-to-drain tunneling window is somewhat short; equivalently, the source and drain reservoir are close, thus leading to a significant DSDT mechanism and a high leakage current spectrum, as shown in Figure 8b. Figure 8c shows the electron density per unit energy versus the longitudinal position at off-state for the JL CNTTFET, considering the LDP near the drain electrode. As shown, the source and drain reservoirs diverge, making the DSDT window longer, and, thus, a decrease in DSDT off-current spectrum is recorded, as shown in Figure 8d.  Figure 9a shows how the decrease in doping concentration of the lightly n-type doped pocket near the drain improves the subthreshold swing and off-current and suppresses the ambipolar behavior. It is worth noting that we have not considered very low doping concentrations in order to keep the junctionless paradigm and avoid the n-type dopingintrinsic abrupt junction. The recorded improvements are attributed to the light dopinginduced band elevation that dilates the DSDT window. In Figure 9b, the same improvement behavior is recorded when increasing the length of the LDP, where enhancements in terms of sub-thermionic subthreshold swing, off-current, and ambipolar behavior are recorded, while optimized on-current is within reach by the chemical and electrical-doping techniques near the source, as shown above. Therefore, wide lightly n-type doped ZCNT portions with a low concentration are suitable for improved subthreshold performance; however, there are some considerations regarding the junctionless aspect, the scaling capability, and the ohmic drain contact.  It is to indicate that the intrinsic delay presents how fast the JL CNTTFET can switch, while the power-delay product shows the energy required for a switching event. Note that the curves in Figure 10 are drawn from the concerned transfer characteristics by shifting a switching window with a width of power-supply voltage (V DD ) equal to 0.4 V, while extracting the on-state total charge (Q ON ) and its current (I ON ) at each given V GS-ON , and the corresponding off-state total charge (Q OFF ) and its current (I OFF ) at V GS-OFF = V GS-ON − V DD [31][32][33].  Figure 10a shows that the proposed JL CNTTFET can provides higher (lower) oncurrent (off-current) for a shared off-current (on-current) in comparison with the conventional nanodevice. Our inspection of the same figure reveals that the proposed JL CNTTFET, which is endowed with electrical-and chemical-doping engineering, can provide a particular performance (highlighted by a solid circle), where both higher on-current and lower off-current were simultaneously recorded in comparison with the currents of the conventional JL CNTTFET. Figure 10b is drawn from the concerned transfer characteristics, showing that the proposed JL CNTTFET can exhibit a higher maximum reachable current ratio (MRCR) with higher on-current, as indicated by arrows. Note that the MRCR of the proposed device is higher than that of the conventional device by about three orders of magnitude. In addition, we can clearly see that the proposed device exhibits a higher I ON /I OFF current ratio than the conventional device over the shared range of on-currents. Figure 10c shows and compares the power-delay product (PDP) in function of I ON /I OFF current ratio for the proposed and conventional JL CNTTFET. It is clearly seen that the proposed nanodevice exhibits lower PDP (higher I ON /I OFF ) than its conventional counterpart over the shared range of current ratio (PDP). In addition, we can observe that the proposed device exhibits a higher MRCR with a lower PDP than that of the CJL CNTTFET. The recorded improvements in terms of PDP empower the proposed design to be an intriguing energy-efficient nano-TFET for high switching applications. Figure 10d shows that the proposed device provides faster (higher) intrinsic delay (current ratio) than its conventional counterpart over the shared range of current ratio (intrinsic delay). In addition, we can also see that the proposed design provides higher MRCR with faster delay than that of the CJL CNTTFET. The substantial decrease in terms of intrinsic delay, together with the recorded current ratios, makes the proposed JL CNTTFET an interesting nanoscale junctionless tunnel FET for high-speed applications.
In order to assess the benefits of the proposed design in the ultrascaled regime, we have performed a quantum-simulation-based comparison between the conventional and the proposed nanodevices, considering the main parameters of switching performance. Table 2 summarizes the main switching figures of merit of the proposed JLCNTTFET with 5 nm gate length. As very interesting results, the current ratio is improved by about 3 orders of magnitude and sub-thermionic SS (43 mV/dec) is well recorded in ultra-scaled regime. In addition, the on-current is boosted, and the off-current, minimum leakage current (I MIN ), I 60 factor, PDP, and intrinsic delay are all decreased, which is very important for high-speed, low-power, and high-performance switching applications. Basing on the recorded results in terms of the on-current improvement, which is attributed to the doping-induced shrinking in BTBT window, the ferroelectric-based gating can be adopted as additional improvement approach in order to further improve the EDJL-CNTTFET performance via the feature of the FE-induced amplified gate voltage [34], and thus well exploiting the boosted BTBT on-current. In fact, the adoption of ferroelectric (FE) material can take two different designs. The first configuration is based on the metalferroelectric-insulator-semiconductor (MFIS) design, while the second arrangement is the metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure [35]. We adopt in our case the MFMIS configuration due to its benefits in terms of elaboration [35][36][37], the possibility of separate integration [38], and the simulation simplicity [39][40][41]. Figure 11a shows an EDJL-CNTTFET design with a MFMIS structure. Note that the MFMIS can be integrated as a coaxial gate [42] or used as separate gating system ideally connected by a wire [25,38,41,43]. From simulation point of view, the ferroelectric field-effect transistors endowed with a MFMIS system can be treated as a baseline field-effect transistor in series with a ferroelectric capacitor [25,[40][41][42][43][44]. Therefore, conceptually, the numerical modeling of the negative capacitance (MFMIS) nanodevices is divided into two parts [45]. The first step of simulation deals with the baseline device as mentioned above in the Section 3. After the self-consistency, the gate charge (Q G ) is numerically extracted and used to compute the voltage across the FE material (V FE ), using the 1-D steady-state Landau-Khalatnikov equation, which is given as follows [34]: where t FE is the FE thickness; and (α, β, and γ) are the FE Landau coefficients, which are chosen to be as those of the Al-doped HfO 2 FE parameters [25,[44][45][46]. After computing V FE , the external gate voltage (V GS ) of the EDJL-CNTTFET is normally computed by using the following equation [25,[39][40][41][42][43][44][45]: where V INT is the internal metal-gate voltage considered in the baseline self-consistent quantum simulation. For more computational information regarding the quantum simulation of ultrascaled MFMIS FE-FETs, we refer the reader to our previous works [19,25,45].  Figure 11b shows that the proposed electrical-and chemical-doping approach can significantly improve the I DS -V GS transfer characteristics of an ultrascaled JL CNTTFET with 5 nm gate length. We can clearly see the substantial improvements in terms of I ON , I OFF , current ratio, and leakage current. In addition, we can observe that the nanodevice with the MFMIS structure additionally improves the on-current, off-current, and subthreshold swing, due to the FE-induced amplified gate voltage. Note that the recorded sub-thermionic subthreshold swing recorded in EDJL-CNTTFET was decreased from 43 to 35 mV/dec via the FE-based improvement approach. This indicates that the adoption of more appropriate FE nanomaterial with particular coercive field and remnant polarization can increasingly boost the nanodevice performance via enhancing the FE-induced amplified internal gate voltage [45]. In order to find the best device and ferroelectric parameters that can lead to the ultimate best performance, a parametric investigation [47] based on metaheuristic techniques (e.g., ant colony optimization, practical swarm optimization, genetic algorithms [48], etc.) in conjunction with the used NEGF simulation approach can be followed, while solving an advanced optimization problem, which can be a matter for future investigations.

Conclusions
In this article, a new approach based on the synergy of the electrostatic and chemicaldoping engineering is proposed to boost the performance of nanoscale JL CNTTFETs. The hybrid doping approach was found to be efficient at shrinking the BTBT window and dilating the DSDT spacing, while also boosting the JL CNTTFET performance. The profound quantum transport investigations have included the band diagrams, the potential distributions, and the energy-position-resolved electron density and current spectra. As a result, the subthreshold and switching performance is significantly improved, where subthermionic subthreshold swing, mitigated ambipolar behavior, boosted on-current, higher current ratio, reduced off-and leakage-current, faster switching speed, lower switching power, and improved scaling capability were obtained. Moreover, the metal-ferroelectricmetal-based gating approach was employed in order to exploit the recorded improvement in carrier transport, while boosting the JL TFET switching performance. The proposed design based on the synergy of electrostatic and chemical-doping engineering solved the main problems in ultrascaled JL CNTTFETs, and this is promising for the future CNT-based nanoelectronics.