On-Chip Reconfigurable and Ultracompact Silicon Waveguide Mode Converters Based on Nonvolatile Optical Phase Change Materials

Reconfigurable mode converters are essential components in efficient higher-order mode sources for on-chip multimode applications. We propose an on-chip reconfigurable silicon waveguide mode conversion scheme based on the nonvolatile and low-loss optical phase change material antimony triselenide (Sb2Se3). The key mode conversion region is formed by embedding a tapered Sb2Se3 layer into the silicon waveguide along the propagation direction and further cladding with graphene and aluminum oxide layers as the microheater. The proposed device can achieve the TE0-to-TE1 mode conversion and reconfigurable conversion (no mode conversion) depending on the phase state of embedded Sb2Se3 layer, whereas such function could not be realized according to previous reports. The proposed device length is only 2.3 μm with conversion efficiency (CE) = 97.5%, insertion loss (IL) = 0.2 dB, and mode crosstalk (CT) = −20.5 dB. Furthermore, the proposed device scheme can be extended to achieve other reconfigurable higher-order mode conversions. We believe the proposed reconfigurable mode conversion scheme and related devices could serve as the fundamental building blocks to provide higher-order mode sources for on-chip multimode photonics.


Introduction
Silicon-on-insulator (SOI), a vital and mature material platform for silicon photonics, has pushed the development of photonic integrated circuits (PICs) based on its high refractive index contrast and CMOS compatible processing [1,2]. On-chip optical interconnects, data centers, and optical communications have been benefited greatly from the compact size, higher performance, and lower power-consumption of PICs [3][4][5]. Most of the current PICs operate in the single-mode state to avoid mode crosstalk and simplify the device design. However, the intrinsic mode degree of freedom of light is lost because of the single-mode operation. To satisfy the rapidly increasing demand on capacity, various on-chip multiplexing technologies have been developed, such as wavelengthdivision-multiplexing (WDM) [6,7], polarization-division-multiplexing (PDM) [8,9], and mode-division-multiplexing (MDM) [10,11], where the underlying mechanisms are based on the intrinsic properties of light (wavelength, polarization, and mode, respectively). Among these multiplexing technologies, WDM requires expensive multi-wavelength lasers and PDM has only two polarization states to be multiplexed [10][11][12]. In comparison, MDM is best suited for the on-chip multiplexing transmission since higher-order modes could provide new multiplexing channels for the on-chip MDM transmission and reveal unique the output. Therefore, reconfigurable mode conversions between TE 0 and TE 1 mode can be achieved by controlling the operating state of the material Sb 2 Se 3 , while previous reports nearly do not have such reconfigurable function [15][16][17][18][19][20][21][24][25][26]. Our calculations show that the required mode conversion length is only 2.3 µm, which is quite shorter than most previous reports [15][16][17][19][20][21]24,25]. The mode conversion efficiency (CE), mode crosstalk (CT), and insertion loss (IL) are 97.5%, −20.5 dB, and 0.2 dB, respectively, at wavelength λ = 1550 nm for the TE 0 -to-TE 1 mode conversion, where the achieved low IL is benefited from the quite low optical loss of material Sb 2 Se 3 compared with other PCMs [33,34]. The performance for the reconfigurable function, i.e., TE 0 -to-TE 0 mode, is better than that of TE 0 -to-TE 1 mode conversion. Moreover, we can achieve reconfigurable TE 0 -to-TE 2 mode conversion by changing the embedded tapering structures. Other reconfigurable mode conversions (TE 0 -to-TE n , n ≥ 3) can also be obtained in theory. Therefore, with the obvious advantages of reconfigurability, small size, high performance, and functional extensibility, the proposed mode conversion scheme can form the building blocks for on-chip multimode photonics in future reconfigurable and programmable PICs [35][36][37]. Figure 1 shows the schematic of the proposed reconfigurable silicon waveguide mode converter. The insets show the enlarged cross-sectional view of the mode conversion region and side view of the embedded PCM layer. To create an efficient refractive index change on the silicon waveguide, we embedded a PCM taper into the silicon waveguide by using waveguide etching and magnetron sputtering [38,39], where the end widths and length of the PCM taper are W 1 , W 2 , and L, respectively, and the PCM thickness is T. The position of the embedded PCM taper should be located asymmetrically to one side relative to the centerline of the silicon waveguide, to allow accumulation of the required π phase difference for the TE 0 -to-TE 1 mode conversion [18,19]. For the PCM, here we use a new Sb 2 Se 3 material rather than the conventionally used VO 2 , Ge 2 Sb 2 Te 5 , and Ge 2 Sb 2 Se 4 Te 1 [33,34,[40][41][42]. The reason is that Sb 2 Se 3 has quite low optical loss compared with other PCMs. Furthermore, the phase transition temperature and melting temperature of Sb 2 Se 3 are lower than that of silicon, thus the silicon waveguide will not be damaged during the phase transition process. The material Sb 2 Se 3 is nonvolatile which means the proposed device will not require static power consumption, because the phase state (crystalline or amorphous state) of the material Sb 2 Se 3 can sustain a long time without any power being supplied. Furthermore, Sb 2 Se 3 can be switched between the crystalline and amorphous state over 4000 cycles without obvious aging symptoms [33,34]. Therefore, the material Sb 2 Se 3 enables the proposed reconfigurable mode converter to work at low loss and low power consumption.

The Device Structure Design and Materials
Further, we add graphene and Al 2 O 3 layers atop the Sb 2 Se 3 . The thicknesses of the Al 2 O 3 and graphene layers are H 1 (=20 nm) and H 3 (=0.35 nm), respectively. The graphene layer works as an efficient microheater because of its high thermal conductivity and low heat capacity [43,44]. The optical absorption loss of graphene could be quite low as the chemical potential of graphene is larger than 0.4 eV owing to the Pauli blocking mechanism [45,46]. The Al 2 O 3 layer is used to prevent the graphene from oxidation. The thickness of the metal electrodes on both sides of the proposed device is chosen as H 2 (=100 nm), and we also introduce a silicon slab layer with a thickness of H 4 (=50 nm) to facilitate rapid heat dissipation when the Sb 2 Se 3 layer changes from the crystalline state to amorphous state. The width and thickness of the input and output silicon waveguide are W (=1.1 µm) and H (=220 nm), respectively.

The Device Working Principle and Calculation Method
The device working principles are analyzed as follows. First when the Sb2Se3 layer at the crystalline state, its optical refractive index is 4.05 at λ = 1.55 μm (imaginary p <10 −5 ) which is larger than that of silicon (~3.4) [33]. The asymmetrically placed Sb2Se3 lay relative to the centerline of the silicon waveguide creates two regions with different fractive index. One region is pure silicon with uniform refractive index distribution a the other region is silicon embedded with the Sb2Se3 layer with nonuniform refractive dex distribution. The two regions are located on either side of the central axis along t waveguide transmission direction, as shown in Figure 2a. When the input TE0 mode e ters the mode conversion region, it will be separated into two beams because of the d ferent refractive indices at the end face of the mode conversion region. These two bea will then propagate along the two regions separately, i.e., the region with pure silic waveguide and the other region which has a Sb2Se3 layer embedded in the silicon wav guide. Owing to different refractive index distribution between these two regions, the tw transmitted beams will have different propagation constants and the phase difference b tween them will accumulate through the light propagation. When the accumulated pha difference between the beams in the two regions equals to π, we combine these two bea and connect to the output waveguide. The output is TE1 mode because the two bea have a π phase difference. The length of the mode conversion region is <3 μm and t conversion loss is <0.3 dB, because of the relatively large refractive index and low opti loss of Sb2Se3 material at the crystalline state.
When the Sb2Se3 layer switches from crystalline sate to amorphous state, its opti refractive index is 3.28 at λ = 1.55 μm (the imaginary part negligible) which is close to t refractive index of silicon (~3.4) [33]. Such a small refractive index difference in a sh propagation length (<3 μm) has negligible effect on the mode field transmission. As a sult, the input TE0 mode will be transmitted through the mode conversion region witho any mode conversion, as shown in Figure 2b. In summary, by switching between t phase states of the embedded Sb2Se3 layer, one can obtain either TE1 or TE0 mode at t device output for the same input TE0 mode, thus achieving reconfigurable mode conv sion.

The Device Working Principle and Calculation Method
The device working principles are analyzed as follows. First when the Sb 2 Se 3 layer is at the crystalline state, its optical refractive index is 4.05 at λ = 1.55 µm (imaginary part < 10 −5 ) which is larger than that of silicon (~3.4) [33]. The asymmetrically placed Sb 2 Se 3 layer relative to the centerline of the silicon waveguide creates two regions with different refractive index. One region is pure silicon with uniform refractive index distribution and the other region is silicon embedded with the Sb 2 Se 3 layer with nonuniform refractive index distribution. The two regions are located on either side of the central axis along the waveguide transmission direction, as shown in Figure 2a. When the input TE 0 mode enters the mode conversion region, it will be separated into two beams because of the different refractive indices at the end face of the mode conversion region. These two beams will then propagate along the two regions separately, i.e., the region with pure silicon waveguide and the other region which has a Sb 2 Se 3 layer embedded in the silicon waveguide. Owing to different refractive index distribution between these two regions, the two transmitted beams will have different propagation constants and the phase difference between them will accumulate through the light propagation. When the accumulated phase difference between the beams in the two regions equals to π, we combine these two beams and connect to the output waveguide. The output is TE 1 mode because the two beams have a π phase difference. The length of the mode conversion region is <3 µm and the conversion loss is <0.3 dB, because of the relatively large refractive index and low optical loss of Sb 2 Se 3 material at the crystalline state.
When the Sb 2 Se 3 layer switches from crystalline sate to amorphous state, its optical refractive index is 3.28 at λ = 1.55 µm (the imaginary part negligible) which is close to the refractive index of silicon (~3.4) [33]. Such a small refractive index difference in a short propagation length (<3 µm) has negligible effect on the mode field transmission. As a result, the input TE 0 mode will be transmitted through the mode conversion region without any mode conversion, as shown in Figure 2b. In summary, by switching between the phase states of the embedded Sb 2 Se 3 layer, one can obtain either TE 1 or TE 0 mode at the device output for the same input TE 0 mode, thus achieving reconfigurable mode conversion.
To analyze the device performance and optimize the device parameters, threedimensional finite-difference time-domain (3D-FDTD) method was employed [47,48], which could well calculate the mode transmission and conversion performance of the proposed device. In the following sections, we will use the 3D-FDTD method to find the optimum structural parameters based on the above-mentioned device working principle. proposed device. In the following sections, we will use the 3D-FDTD method to find the optimum structural parameters based on the above-mentioned device working principle.

Results and Discussion
Before we conduct the calculation and optimization of the device performance, the key device performance indictors should be defined at first. Here, we use the device performance indicators of mode CE, CT, and IL to characterize the device performance. For the TE0-to-TE1 mode conversion, the mode CE is defined as [19,20] where PTE1 and Pout stand for the receiving power of TE1 mode and total output power at the device output port, respectively. Mode CT is defined as [19,20] 1 OT 10 TE CT= max 10log P P where POT represents the output power of the other interfering mode rather than TE1 at the device output port and we choose the maximum value as the mode CT for the proposed device. IL is defined as [19,20] 1 TE 10 in where Pin represents the power of the input TE0 mode at the device input port. If not otherwise specified, the working wavelength is set as 1.55 μm in the following discussion. We then carried out extensive numerical simulation to determine the structural parameters of the embedded Sb2Se3 layer for optimal device performance. The optimized values of embedded Sb2Se3 layer are as follows: the embedded taper end widths W1 = 340 nm and W2 = 100 nm, the layer thickness T = 340 nm, the lateral shift relative to the waveguide center S = 360 nm, and the taper length L = 2.3 μm. Figure 3 shows the calculated mode CE, CT, and IL of the proposed device as a function of the PCM (Sb2Se3) taper length L, where the end widths and thickness of the Sb2Se3 layer are chosen at the respective optimal values W1 = 340 nm, W2 = 100 nm and T = 340 nm. For the TE0-to-TE1 mode conversion, the Sb2Se3 layer is in the crystalline state. From

Results and Discussion
Before we conduct the calculation and optimization of the device performance, the key device performance indictors should be defined at first. Here, we use the device performance indicators of mode CE, CT, and IL to characterize the device performance. For the TE 0 -to-TE 1 mode conversion, the mode CE is defined as [19,20] where P TE 1 and P out stand for the receiving power of TE 1 mode and total output power at the device output port, respectively. Mode CT is defined as [19,20] CT = max 10 log 10 P OT P TE 1 , where P OT represents the output power of the other interfering mode rather than TE 1 at the device output port and we choose the maximum value as the mode CT for the proposed device. IL is defined as [19,20] where P in represents the power of the input TE 0 mode at the device input port. If not otherwise specified, the working wavelength is set as 1.55 µm in the following discussion. We then carried out extensive numerical simulation to determine the structural parameters of the embedded Sb 2 Se 3 layer for optimal device performance. The optimized values of embedded Sb 2 Se 3 layer are as follows: the embedded taper end widths W 1 = 340 nm and W 2 = 100 nm, the layer thickness T = 340 nm, the lateral shift relative to the waveguide center S = 360 nm, and the taper length L = 2.3 µm. Figure 3 shows the calculated mode CE, CT, and IL of the proposed device as a function of the PCM (Sb 2 Se 3 ) taper length L, where the end widths and thickness of the Sb 2 Se 3 layer are chosen at the respective optimal values W 1 = 340 nm, W 2 = 100 nm and T = 340 nm. For the TE 0 -to-TE 1 mode conversion, the Sb 2 Se 3 layer is in the crystalline state. From Figure 3, the mode conversion performance is closely related to the PCM taper length within the calculation range from L = 1.5 to 3.0 µm. The optimum performance is obtained at L = 2.3 µm with the highest CE = 97.5%, lowest CT = −20.5 dB, and lowest IL = 0.2 dB. For a fabrication error of ±0.2 µm, i.e., L varies from 2.1 to 2.5 µm, the device performance is still acceptable with CE > 95%, CT < −15 dB, and IL < 0.3 dB. The taper length L is chosen at 2.3 µm in the following discussion, where such conversion length is clearly shorter than most previous reports [15][16][17][19][20][21]24,25].
within the calculation range from L = 1.5 to 3.0 μm. The optimum performance is obtained at L = 2.3 μm with the highest CE = 97.5%, lowest CT = −20.5 dB, and lowest IL = 0.2 dB. For a fabrication error of ±0.2 μm, i.e., L varies from 2.1 to 2.5 μm, the device performance is still acceptable with CE > 95%, CT < −15 dB, and IL < 0.3 dB. The taper length L is chosen at 2.3 μm in the following discussion, where such conversion length is clearly shorter than most previous reports [15][16][17][19][20][21]24,25].  Figure 4 shows the effect of the end widths (W1, W2) of the embedded Sb2Se3 layer on the device performance. For W1, the Sb2Se3 layer will reach the waveguide boundary if W1 is larger than 380 nm. So, we set W1 ≤ 380 nm in the calculations. For W2, the achievable width depends on the state of fabrication technology. We choose W2 ≥ 80 nm, which could be achieved using current E-beam lithography and etching processes [49,50]. The Sb2Se3 layer thickness T and lateral shift S are set at the optimal values of 340 nm and 360 nm, respectively. Figure 4 shows that the input end width W1 has stronger effect on the device performance when compared with the output end width W2. The widths for the best device performance are at W1 = 340 nm and W2 = 100 nm, corresponding to CE = 97.5%, CT = −20.5 dB, and IL = 0.2 dB. Assuming a device performance of CE > 95%, CT < −15 dB, IL < 0.3 dB, W1 and W2 should be within the ranges of [310,370] nm and [80,130] nm, respectively. More detailed comparisons of the mode conversion performance (CE, CT, IL) with other reports can be found in the following Table 1.    Figure 4 shows the effect of the end widths (W 1 , W 2 ) of the embedded Sb 2 Se 3 layer on the device performance. For W 1 , the Sb 2 Se 3 layer will reach the waveguide boundary if W 1 is larger than 380 nm. So, we set W 1 ≤ 380 nm in the calculations. For W 2 , the achievable width depends on the state of fabrication technology. We choose W 2 ≥ 80 nm, which could be achieved using current E-beam lithography and etching processes [49,50]. The Sb 2 Se 3 layer thickness T and lateral shift S are set at the optimal values of 340 nm and 360 nm, respectively. Figure 4 shows that the input end width W 1 has stronger effect on the device performance when compared with the output end width W 2 . The widths for the best device performance are at W 1 = 340 nm and W 2 = 100 nm, corresponding to CE = 97.5%, CT = −20.5 dB, and IL = 0.2 dB. Assuming a device performance of CE > 95%, CT < −15 dB, IL < 0.3 dB, W 1 and W 2 should be within the ranges of [310, 370] nm and [80, 130] nm, respectively. More detailed comparisons of the mode conversion performance (CE, CT, IL) with other reports can be found in the following Table 1.  Figure 5a shows the definition of the Sb2Se3 layer thickness T. For the same device performance criteria mentioned above, i.e., CE > 95%, CT < −15 dB, IL < 0.3 dB, the thickness T can vary from 300 to 400 nm. The large tolerance in thickness T relaxes the constrains on device fabrication. Figure 5b shows that the lateral shift S of the embedded Sb2Se3 layer relative to the centerline of the waveguide has a strong effect on the device performance when compared with other parameters. The reason is that the lateral shift S determines the refractive index distribution in the mode conversion region. When the lateral shift changes, the corresponding refractive index distribution will change, strongly affecting the mode conversion performance [19,20]. The optimum lateral shift is found to be 360 nm relative to the centerline of the waveguide. Note that the embedded Sb2Se3 layer will be outside the silicon waveguide boundary for S > 380 nm. Thus, the calculation range of S should be less than 380 nm. In summary, the input end width W1 and lateral shift S should be carefully controlled during the fabrication process since their fabrication tolerances are relatively small.    Figure 5 plots the device performance versus the Sb 2 Se 3 layer thickness T and lateral shift S of the embedded Sb 2 Se 3 layer relative to the waveguide center. The taper widths W 1 and W 2 are set as 340 nm and 100 nm, respectively. The insets of Figure 5a,b show the definition of T and S, respectively. From Figure 5a, we find that the device performance would be very poor if the thickness of the Sb 2 Se 3 layer T is the same as that of the silicon waveguide (H = 220 nm). So, it is necessary to choose different thicknesses which would require extra fabrication steps during device fabrication. The optimum thickness of Sb 2 Se 3 layer is 340 nm, corresponding to the performance CE = 97.5%, CT = −20.5 dB, and IL = 0.2 dB. The inset in Figure 5a shows the definition of the Sb 2 Se 3 layer thickness T. For the same device performance criteria mentioned above, i.e., CE > 95%, CT < −15 dB, IL < 0.3 dB, the thickness T can vary from 300 to 400 nm. The large tolerance in thickness T relaxes the constrains on device fabrication. Figure 5b shows that the lateral shift S of the embedded Sb 2 Se 3 layer relative to the centerline of the waveguide has a strong effect on the device performance when compared with other parameters. The reason is that the lateral shift S determines the refractive index distribution in the mode conversion region. When the lateral shift changes, the corresponding refractive index distribution will change, strongly affecting the mode conversion performance [19,20]. The optimum lateral shift is found to be 360 nm relative to the centerline of the waveguide. Note that the embedded Sb 2 Se 3 layer will be outside the silicon waveguide boundary for S > 380 nm. Thus, the calculation range of S should be less than 380 nm. In summary, the input end width W 1 and lateral shift S should be carefully controlled during the fabrication process since their fabrication tolerances are relatively small.  Figure 5a shows the definition of the Sb2Se3 layer thickness T. For the sam device performance criteria mentioned above, i.e., CE > 95%, CT < −15 dB, IL < 0.3 dB, th thickness T can vary from 300 to 400 nm. The large tolerance in thickness T relaxes th constrains on device fabrication. Figure 5b shows that the lateral shift S of the embedded Sb2Se3 layer relative to the centerline of the waveguide has a strong effect on the devic performance when compared with other parameters. The reason is that the lateral shift S determines the refractive index distribution in the mode conversion region. When the lat eral shift changes, the corresponding refractive index distribution will change, strongly affecting the mode conversion performance [19,20]. The optimum lateral shift is found to be 360 nm relative to the centerline of the waveguide. Note that the embedded Sb2Se3 laye will be outside the silicon waveguide boundary for S > 380 nm. Thus, the calculation rang of S should be less than 380 nm. In summary, the input end width W1 and lateral shift S should be carefully controlled during the fabrication process since their fabrication toler ances are relatively small.  Figure 6a depicts mode CE, CT, and IL as a function of wavelength for the proposed TE0-to-TE1 mode converter, when material dispersions are considered [33,51]. Figure 6b shows the reconfigurable function, i.e., no mode conversion when the embedded Sb2Se layer is at the amorphous state. Figure 6a shows a strong wavelength dependence in th range from 1.4 to 1.7 μm for the mode conversion from TE0 to TE1 mode. By contrast   shows the reconfigurable function, i.e., no mode conversion when the embedded Sb 2 Se 3 layer is at the amorphous state. Figure 6a shows a strong wavelength dependence in the range from 1.4 to 1.7 µm for the mode conversion from TE 0 to TE 1 mode. By contrast, Figure 6b shows that when no mode conversion takes place, the device performance exhibits only a small wavelength dependence. Again, for the same device performance criteria (CE > 95%, CT < −15 dB, IL < 0.3 dB), the allowable working wavelength range is from 1507 nm to 1616 nm (bandwidth = 109 nm) for the TE 0 -to-TE 1 mode conversion. As for the reconfigurable function, the corresponding CE, CT, and IL are >98.5%, <−24 dB, and <0.23 dB, respectively, in the wavelength range from 1.4 to 1.7 µm. Thus, the proposed mode converter has a good reconfigurable function, and the allowable working bandwidth covers the main optical communication bands, which is larger than the working bandwidths of some reported mode converters [16,18,24,25]. exhibits only a small wavelength dependence. Again, for the same device performance criteria (CE > 95%, CT < −15 dB, IL < 0.3 dB), the allowable working wavelength range is from 1507 nm to 1616 nm (bandwidth = 109 nm) for the TE0-to-TE1 mode conversion. As for the reconfigurable function, the corresponding CE, CT, and IL are >98.5%, <−24 dB, and <0.23 dB, respectively, in the wavelength range from 1.4 to 1.7 μm. Thus, the proposed mode converter has a good reconfigurable function, and the allowable working bandwidth covers the main optical communication bands, which is larger than the working bandwidths of some reported mode converters [16,18,24,25]. The main process to fabricate the proposed reconfigurable mode converter can be divided into three sections: fabricating the silicon waveguide, embedding the Sb2Se3 layer into the silicon waveguide, and depositing the graphene and Al2O3 layers atop the device including the metal contacts. We can start from a standard SOI wafer with a top silicon layer thickness of 220 nm and a buried oxide layer thickness of 2 μm. First, the silicon waveguide with a width of 1.1 μm and a slab layer thickness of 50 nm, including a taper slot, is fabricated on the SOI wafer using E-beam lithography and reactive ion etching processes [49,50]. Second, a Sb2Se3 layer with a thickness of 340 nm is deposited on the mode conversion region using magnetron sputtering [33,34], and then the Sb2Se3 material is removed except in the taper slot region such that the Sb2Se3 material will fill the etched slot region. More details about the film preparation and deposition of the Sb2Se3 material can refer to the work reported in [52]. Third, a graphene layer grown by the chemical vapor deposition is transferred onto the device surface. The metal contacts are added on both sides of the conversion region. Then, using atom layer deposition, a 20-nm-thick Al2O3 layer is deposited atop the graphene layer to prevent the graphene from oxidation [45]. Using these methods, we can realize the proposed reconfigurable silicon waveguide mode converter. Within these fabrication processes, if a small number of voids are introduced into the Sb2Se3 layer due to the sputtering error, the IL of the device might be slightly increased, but the mode CE and CT could be still guaranteed through further structural optimizations.
To study the deterioration of the device performance caused by fabrication errors in practice, we analyze the effect of the variations of the size of the embedded Sb2Se3 layer (ΔC) and silicon waveguide (ΔW) along the width direction (y-direction in Figure 1b) on the device performance. Figure 7 shows the device performance deteriorates as ΔC or ΔW deviates from their optimum values. Insets in Figure 7a,b show the definition of ΔC and ΔW, respectively. For the same device performance criteria of CE > 95%, CT < −15 dB, and IL < 0.3 dB, ΔC and ΔW should be controlled within the ranges of −22 to 14 nm, and −50 to 150 nm, respectively. These tolerance requirements can be achieved using current fabrication facilities [49,50]. Figure 8 shows the wavelength spectra of the proposed device when the structural parameters (L, W1, W2, S, T, W) change. For the analysis of every structural parameter, other structural parameters are fixed at their optimal values. From Figure  8, the optimum working wavelength will shift as these calculated structural parameters The main process to fabricate the proposed reconfigurable mode converter can be divided into three sections: fabricating the silicon waveguide, embedding the Sb 2 Se 3 layer into the silicon waveguide, and depositing the graphene and Al 2 O 3 layers atop the device including the metal contacts. We can start from a standard SOI wafer with a top silicon layer thickness of 220 nm and a buried oxide layer thickness of 2 µm. First, the silicon waveguide with a width of 1.1 µm and a slab layer thickness of 50 nm, including a taper slot, is fabricated on the SOI wafer using E-beam lithography and reactive ion etching processes [49,50]. Second, a Sb 2 Se 3 layer with a thickness of 340 nm is deposited on the mode conversion region using magnetron sputtering [33,34], and then the Sb 2 Se 3 material is removed except in the taper slot region such that the Sb 2 Se 3 material will fill the etched slot region. More details about the film preparation and deposition of the Sb 2 Se 3 material can refer to the work reported in [52]. Third, a graphene layer grown by the chemical vapor deposition is transferred onto the device surface. The metal contacts are added on both sides of the conversion region. Then, using atom layer deposition, a 20-nm-thick Al 2 O 3 layer is deposited atop the graphene layer to prevent the graphene from oxidation [45]. Using these methods, we can realize the proposed reconfigurable silicon waveguide mode converter. Within these fabrication processes, if a small number of voids are introduced into the Sb 2 Se 3 layer due to the sputtering error, the IL of the device might be slightly increased, but the mode CE and CT could be still guaranteed through further structural optimizations.
To study the deterioration of the device performance caused by fabrication errors in practice, we analyze the effect of the variations of the size of the embedded Sb 2 Se 3 layer (∆C) and silicon waveguide (∆W) along the width direction (y-direction in Figure 1b) on the device performance. Figure 7 shows the device performance deteriorates as ∆C or ∆W deviates from their optimum values. Insets in Figure 7a,b show the definition of ∆C and ∆W, respectively. For the same device performance criteria of CE > 95%, CT < −15 dB, and IL < 0.3 dB, ∆C and ∆W should be controlled within the ranges of −22 to 14 nm, and −50 to 150 nm, respectively. These tolerance requirements can be achieved using current fabrication facilities [49,50]. Figure 8 shows the wavelength spectra of the proposed Nanomaterials 2022, 12, 4225 9 of 15 device when the structural parameters (L, W 1 , W 2 , S, T, W) change. For the analysis of every structural parameter, other structural parameters are fixed at their optimal values. From Figure 8, the optimum working wavelength will shift as these calculated structural parameters vary from their optimal values, and the corresponding device performance will also deteriorate. For optimum device performance, one should target the determined structural parameters when fabricating the device. Nanomaterials 2022, 12, x FOR PEER REVIEW 9 of 15 vary from their optimal values, and the corresponding device performance will also deteriorate. For optimum device performance, one should target the determined structural parameters when fabricating the device.   Figure 9 plots the evolution of the electric field along the propagation direction through the proposed reconfigurable mode converter. The mode conversion length is 2.3 μm and the 3D-FDTD method is used to perform the calculations. From Figure 9, either the TE1 or TE0 mode can be obtained at the device output port by switching the phase state of the embedded Sb2Se3 layer in the device. Because of the nonvolatile property of the Sb2Se3 material, either output (TE1 or TE0 mode) of the proposed device can be kept for a long time without consuming any energy, i.e., zero static power consumption [33,34,38,39]. When the Sb2Se3 layer is at the crystalline state, the input TE0 mode will be split into two beams when it enters the mode conversion region. The two beams transmit along the two channels. One channel is a pure silicon waveguide and the other channel is a silicon waveguide embedded with a Sb2Se3 layer. Because of the different mode vary from their optimal values, and the corresponding device performance will also deteriorate. For optimum device performance, one should target the determined structural parameters when fabricating the device.   Figure 9 plots the evolution of the electric field along the propagation direction through the proposed reconfigurable mode converter. The mode conversion length is 2.3 μm and the 3D-FDTD method is used to perform the calculations. From Figure 9, either the TE1 or TE0 mode can be obtained at the device output port by switching the phase state of the embedded Sb2Se3 layer in the device. Because of the nonvolatile property of the Sb2Se3 material, either output (TE1 or TE0 mode) of the proposed device can be kept for a long time without consuming any energy, i.e., zero static power consumption [33,34,38,39]. When the Sb2Se3 layer is at the crystalline state, the input TE0 mode will be split into two beams when it enters the mode conversion region. The two beams transmit along the two channels. One channel is a pure silicon waveguide and the other channel is a silicon waveguide embedded with a Sb2Se3 layer. Because of the different mode  Figure 9 plots the evolution of the electric field along the propagation direction through the proposed reconfigurable mode converter. The mode conversion length is 2.3 µm and the 3D-FDTD method is used to perform the calculations. From Figure 9, either the TE 1 or TE 0 mode can be obtained at the device output port by switching the phase state of the embedded Sb 2 Se 3 layer in the device. Because of the nonvolatile property of the Sb 2 Se 3 material, either output (TE 1 or TE 0 mode) of the proposed device can be kept for a long time without consuming any energy, i.e., zero static power consumption [33,34,38,39]. When the Sb 2 Se 3 layer is at the crystalline state, the input TE 0 mode will be split into two beams when it enters the mode conversion region. The two beams transmit along the two channels. One channel is a pure silicon waveguide and the other channel is a silicon waveguide embedded with a Sb 2 Se 3 layer. Because of the different mode propagation constants in these two channels, the split modes will accumulate phase difference between them during mode propagation. When the phase difference equals to π, the two beams are in opposite phase resulting in the TE 1 mode, as shown in Figure 9a. When the Sb 2 Se 3 layer is at the amorphous state, no mode conversion is observed and the input TE 0 mode propagates through the device with little distortion as shown in Figure 9b. We obtain the TE 0 mode at the output port of the device. Figure 9 shows that reconfigurable mode conversion can be achieved within a device length of only 2.3 µm. To the best of our knowledge, such reconfigurable function and conversion length have not been realized before [15][16][17][18][19][20][21][24][25][26].
Nanomaterials 2022, 12, x FOR PEER REVIEW propagation constants in these two channels, the split modes will accumulate ph ference between them during mode propagation. When the phase difference equa the two beams are in opposite phase resulting in the TE1 mode, as shown in Fig  When the Sb2Se3 layer is at the amorphous state, no mode conversion is observed input TE0 mode propagates through the device with little distortion as shown in 9b. We obtain the TE0 mode at the output port of the device. Figure 9 shows that re urable mode conversion can be achieved within a device length of only 2.3 μm. best of our knowledge, such reconfigurable function and conversion length have n realized before [15][16][17][18][19][20][21][24][25][26]. Next, we analyze the phase change process between the crystalline state and phous state of the embedded Sb2Se3 layer. The electric-thermal phase transition me employed based on the graphene micro-heater and the electric-thermal simulation ried out using COMSOL Multiphysics [53]. Figure 10 shows the results of the e thermal simulation when the Sb2Se3 material undergoes the crystallization and phization process. The phase transition temperature of Sb2Se3 is 473 K and the temperature of Sb2Se3 is 893 K [33,34], where the upper temperature limit of the pr device is 1100 K. From Figure 10, the required temperatures for the phase change o material can be achieved using the proposed graphene microheater. The graphene heater is more efficient than other metal heaters because of the high thermal cond and low heat capacity of graphene [43,44]. In addition, the phase transition and temperatures of Sb2Se3 are clearly lower than the melting temperatures of silicon graphene, and Al2O3, thus the phase transition process will not damage the propo vice. For the switching time of the material Sb2Se3 based on the electric-therma transition method, the commonly required pulse width is ~100 μs (120 μs for the edge) from the amorphous state to crystalline state, while the pulse width is only (10 ns for the trailing edge) from the crystalline state to the amorphous state [44]. Next, we analyze the phase change process between the crystalline state and amorphous state of the embedded Sb 2 Se 3 layer. The electric-thermal phase transition method is employed based on the graphene micro-heater and the electric-thermal simulation is carried out using COMSOL Multiphysics [53]. Figure 10 shows the results of the electric-thermal simulation when the Sb 2 Se 3 material undergoes the crystallization and amorphization process. The phase transition temperature of Sb 2 Se 3 is 473 K and the melting temperature of Sb 2 Se 3 is 893 K [33,34], where the upper temperature limit of the proposed device is 1100 K. From Figure 10, the required temperatures for the phase change of Sb 2 Se 3 material can be achieved using the proposed graphene microheater. The graphene microheater is more efficient than other metal heaters because of the high thermal conductivity and low heat capacity of graphene [43,44]. In addition, the phase transition and melting temperatures of Sb 2 Se 3 are clearly lower than the melting temperatures of silicon, silica, graphene, and Al 2 O 3 , thus the phase transition process will not damage the proposed device. For the switching time of the material Sb 2 Se 3 based on the electric-thermal phase transition method, the commonly required pulse width is~100 µs (120 µs for the trailing edge) from the amorphous state to crystalline state, while the pulse width is only~400 ns (10 ns for the trailing edge) from the crystalline state to the amorphous state [44]. So, one switching cycle is <250 µs, including the trailing edge of the pulse. So, the proposed mode converter can therefore utilize the phase change property of Sb 2 Se 3 to perform the reconfigurable mode conversion functions. We then apply the principle of the proposed reconfigurable mode conversion scheme for TE0-to-TE1 to realize reconfigurable higher-order mode converters. We design a reconfigurable TE0-to-TE2 mode converter, in which two Sb2Se3 tapers are embedded into the silicon waveguide symmetrically with respect to the centerline of the silicon waveguide, as shown in Figure 11. The mode conversion length is still 2.3 μm. From the simulation results, the conversion performance from TE0 to TE2 mode is quite good with CE = 99.4%, CT < −25.2 dB, and IL = 0.11 dB at λ = 1.55 μm. When the Sb2Se3 layer switches from crystalline to amorphous state, the reconfigurable function can be obtained with no mode conversion. Thus, the reconfigurable function of the TE0-to-TE2 mode converter is achieved. Moreover, we also study the backward transmission processes of the proposed TE0-to-TE1 and TE0-to-TE2 reconfigurable mode converters, where the higher-order modes (TE1 mode and TE2 mode) are injected from the right port under two types of the phase state conditions, as illustrated in Figure 12. From Figure 12, we can clearly find that both TE1 and TE2 modes can be well converted to the fundamental TE0 mode when the Sb2Se3 layer works at the crystalline state. Meanwhile, no mode conversion can happen when the Sb2Se3 layer works at the amorphous state and the output modes are still TE1 mode and TE2 mode, respectively. In principle, other reconfigurable higher-order mode converters can also be designed by using our previously reported extension rule [54]. For the reconfigurable function of the present device, it is just like a mode switch, which can be switched between the output TE0 mode and TE1 (or TE2) mode. While some previously reported mode converters normally have only one function for a device [15][16][17][18][19][20][21][24][25][26] with quite low functional flexibility. When these devices are designed and fabricated, their functions are determined which cannot be further changed. If we program signals on these two outputting modes based on the proposed reconfigurable mode converter and combine with other components on the same chip, the whole chip could have a programmable function. Further, if we add more reconfigurable mode converters in the PIC, more functions will be obtained for the same PIC, which could support more applications (e.g., optical computing [31], optical neural network [32], optical imaging [55]). We then apply the principle of the proposed reconfigurable mode conversion scheme for TE 0 -to-TE 1 to realize reconfigurable higher-order mode converters. We design a reconfigurable TE 0 -to-TE 2 mode converter, in which two Sb 2 Se 3 tapers are embedded into the silicon waveguide symmetrically with respect to the centerline of the silicon waveguide, as shown in Figure 11. The mode conversion length is still 2.3 µm. From the simulation results, the conversion performance from TE 0 to TE 2 mode is quite good with CE = 99.4%, CT < −25.2 dB, and IL = 0.11 dB at λ = 1.55 µm. When the Sb 2 Se 3 layer switches from crystalline to amorphous state, the reconfigurable function can be obtained with no mode conversion. Thus, the reconfigurable function of the TE 0 -to-TE 2 mode converter is achieved. Moreover, we also study the backward transmission processes of the proposed TE 0 -to-TE 1 and TE 0 -to-TE 2 reconfigurable mode converters, where the higher-order modes (TE 1 mode and TE 2 mode) are injected from the right port under two types of the phase state conditions, as illustrated in Figure 12. From Figure 12, we can clearly find that both TE 1 and TE 2 modes can be well converted to the fundamental TE 0 mode when the Sb 2 Se 3 layer works at the crystalline state. Meanwhile, no mode conversion can happen when the Sb 2 Se 3 layer works at the amorphous state and the output modes are still TE 1 mode and TE 2 mode, respectively. In principle, other reconfigurable higher-order mode converters can also be designed by using our previously reported extension rule [54]. For the reconfigurable function of the present device, it is just like a mode switch, which can be switched between the output TE 0 mode and TE 1 (or TE 2 ) mode. While some previously reported mode converters normally have only one function for a device [15][16][17][18][19][20][21][24][25][26] with quite low functional flexibility. When these devices are designed and fabricated, their functions are determined which cannot be further changed. If we program signals on these two outputting modes based on the proposed reconfigurable mode converter and combine with other components on the same chip, the whole chip could have a programmable function. Further, if we add more reconfigurable mode converters in the PIC, more functions will be obtained for the same PIC, which could support more applications (e.g., optical computing [31], optical neural network [32], optical imaging [55]).  Table 1 compares the proposed mode converters with typical mode converters reported recently in the literature. We consider the device structure, function, size, performance, and reconfigurability. From Table 1, the proposed devices have obvious advantages in conversion length, device performance, and reconfigurable functions. By comparison, we can also easily find the superiority of the proposed reconfigurable mode converters, which could well support the development of on-chip multimode photonics.
Finally, with the features of short conversion length (2.3 μm), high conversion performance (CE > 97%, CT < −20 dB, IL~0.2 dB), reconfigurable mode conversion, and functional extensibility, we believe the proposed reconfigurable silicon waveguide mode conversion scheme and related devices could find important applications in on-chip multimode photonics and be one of the fundamental building blocks for the reconfigurable multimode PICs [13,14].    Table 1 compares the proposed mode converters with typical mode converters reported recently in the literature. We consider the device structure, function, size, performance, and reconfigurability. From Table 1, the proposed devices have obvious advantages in conversion length, device performance, and reconfigurable functions. By comparison, we can also easily find the superiority of the proposed reconfigurable mode converters, which could well support the development of on-chip multimode photonics.
Finally, with the features of short conversion length (2.3 μm), high conversion performance (CE > 97%, CT < −20 dB, IL~0.2 dB), reconfigurable mode conversion, and functional extensibility, we believe the proposed reconfigurable silicon waveguide mode conversion scheme and related devices could find important applications in on-chip multimode photonics and be one of the fundamental building blocks for the reconfigurable multimode PICs [13,14].   Table 1 compares the proposed mode converters with typical mode converters reported recently in the literature. We consider the device structure, function, size, performance, and reconfigurability. From Table 1, the proposed devices have obvious advantages in conversion length, device performance, and reconfigurable functions. By comparison, we can also easily find the superiority of the proposed reconfigurable mode converters, which could well support the development of on-chip multimode photonics.
Finally, with the features of short conversion length (2.3 µm), high conversion performance (CE > 97%, CT < −20 dB, IL~0.2 dB), reconfigurable mode conversion, and functional extensibility, we believe the proposed reconfigurable silicon waveguide mode conversion scheme and related devices could find important applications in on-chip mul-timode photonics and be one of the fundamental building blocks for the reconfigurable multimode PICs [13,14].

Conclusions
In conclusion, we proposed a reconfigurable silicon waveguide mode conversion scheme, in which the reconfigurable function is achieved by using nonvolatile and low-loss optical phase change material Sb 2 Se 3 . A hybrid Sb 2 Se 3 -silicon waveguide is obtained by embedding a tapered Sb 2 Se 3 layer into the silicon waveguide. To achieve the mode conversion from input TE 0 to output TE 1 mode, the embedded Sb 2 Se 3 layer should be located on one side of the centerline of the silicon waveguide. When the Sb 2 Se 3 layer works at the crystalline state, the input TE 0 mode can be efficiently converted to TE 1 mode at the output in a device length of only 2.3 µm, which is much shorter than most reports. When the Sb 2 Se 3 layer works at the amorphous state, no mode conversion occurs, which corresponds to the reconfigurable mode conversion. Note that the reconfigurable function cannot be achieved using previous mode converters. From the simulation results, the device performance for the TE 0 -to-TE 1 mode conversion is CE = 97.5%, CT < −20.5 dB, and IL = 0.2 dB, where the quite low IL is benefited from the low-loss feature of the employed material Sb 2 Se 3 . We also analyze the device working bandwidth and fabrication tolerance of key structural parameters, as well as carry out the electric-thermal simulation for the phase change process. In addition, the present device scheme can be extended to realize other reconfigurable higher-order mode conversions (e.g., TE 0 -to-TE 2 mode conversion, CE = 99.4%, CT < −25.2 dB, and IL = 0.11 dB at λ = 1.55 µm), demonstrating the extensibility of the proposed scheme. With these advantages, the proposed device scheme can provide reconfigurable higher-order mode sources for on-chip multimode photonics.