Hyper-FET’s Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by −16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.


Introduction
Silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are being scaled down to sub-5 nm, and a multi-nanosheet FET (mNS-FET) is expected to be used in the 3 nm technical node. Although successful scaling down technology is being developed, increase in power density has become an issue due to difficulty in reducing supply voltage (V DD ). Recently, research on overcoming these limitations by achieving a sub-threshold swing (SS) ≤60 mV/dec through devices such as negative capacitance FET (NC-FET) [1] and tunneling FET (T-FET) [2] using nanomaterials is being actively conducted. In addition, a Hybrid-Phase Transition Field-Effects-Transistor (hyper-FET) [3] device utilizing the steep switching characteristic of nano-scale Phase-Transition Materials (PTM) [4,5] has been proposed, and various material and process prospective studies are actively being conducted. Recently, a study analyzed for the first time in terms of the operation characteristics of a hyper-FET device and circuit using a fin-FET of a 14 nm technology node as a baseline FET was published by Aziz, A. et al. in [6,7]. However, there are insufficient studies on the electrical characteristics of a hyper-FET upon scaling down to the latest node, such as a 3 nm technology node, and targeting of the PTM characteristics for hyper-FET device design.
In this work, following the approach of Aziz, A. et al., we focused on PTM device design for hyper-FET implementation, based on a 3 nm technology node using a mNS-FET with various threshold voltage (V th ) characteristics. We propose an optimization method in consideration of device and circuit operation for optimizing the key electrical characteristics In this work, following the approach of Aziz, A. et. al., we focused on PTM device design for hyper-FET implementation, based on a 3 nm technology node using a mNS-FET with various threshold voltage (Vth) characteristics. We propose an optimization method in consideration of device and circuit operation for optimizing the key electrical characteristics of baseline-FET and PTM constituting hyper-FET. This is a proposed flow based on a systematic analysis of previously published research results [6,7]. Hyper-FET characteristics were secured according to IOFF of baseline-FET and variation of the PTM's transition time (TT) through the systematic optimization process, and benchmarks were performed in logic INV RO and SRAM circuits with conventional CMOS devices. Since an INV RO is a circuit that represents the power and speed characteristics of numerous logic standard cell circuits, such as NAND, NOR, and XOR, the benchmark through an INV RO can be considered to have the characteristics of the entire logic circuit. Also, hyper-FET design guidelines for further circuit characteristic optimization at the 3 nm tech. node are presented Chapter 2 of this paper describes the device and circuit simulation environment used in this work, Chapter 3 presents the hyper-FET optimization process and the logic circuit level (INV RO, SRAM) results of benchmark performance with conventional CMOS devices, and Chapter 4 presents the conclusion of this paper.

Simulation Environment for Hyper-FET Device and Circuit Co-Analysis
In this work, a lateral multi-nanosheet field-effect transistor (LmNS-FET) using multiple multi-nanosheet channels placed in the lateral direction in the 3 nm technology node dimension, was used as an FEOL device. The number of nanosheet channels used is three, and the main device dimensions of the 3 nm technology node, such as contact-poly-pitch (CPP) and gate length (Lg), were set concerning IRDS 2020 [8] as shown in Figure 1. Table  1 summarizes the results.    The electrical characteristics of the mNS-FET were simulated using Synopsys' Sentarurus TM ver. S-2021.06-SP1, a three-dimensional TCAD software, and the model used in this case was used by adding the following models to the drift-diffusion carrier Nanomaterials 2022, 12, 4096 3 of 12 transport model. The density gradient quantization model (eQuantum Potential) was included to describe the quantum confinement effect, and the mobility model (phumob/high field saturation/Enormal) was utilized to consider the quantum effect, Coulomb scattering, and interfacial surface roughness scattering. The Lombardi mobility model was included to calculate the mobility degradation by remote phonon and Coulomb scatterings at the channel and insulator interface. A thin-layer mobility model was included to account for the thin channel thickness. The measured electrical characteristics of the mNS-FET manufactured by hardware in the 7 nm dimension and the TCAD model parameters were calibrated to increase the accuracy of the model. A model library that accurately describes the current-voltage (I-V) and capacitance-voltage (C-V) characteristics extracted through TCAD simulation were then created using the industry-standard model BSIM-CMG. Next, to have the industry's standard 3 nm model circuit characteristics, the generated model library was centered to satisfy the target speed and power of the INV RO with fan-out 3 (FO3), a benchmark circuit, to produce the final model library as summarized in Figure 2.
S/D doping 3 × 10 2 cm −3 PTS doping (upper of substrate 1) 1 × 10 19 cm −3 Substrate 2 doping 10 17 cm −3 The electrical characteristics of the mNS-FET were simulated using Synopsys' Sentarurus TM ver. S-2021.06-SP1, a three-dimensional TCAD software, and the model used in this case was used by adding the following models to the drift-diffusion carrier transport model. The density gradient quantization model (eQuantum Potential) was included to describe the quantum confinement effect, and the mobility model (phumob/high field saturation/Enormal) was utilized to consider the quantum effect, Coulomb scattering, and interfacial surface roughness scattering. The Lombardi mobility model was included to calculate the mobility degradation by remote phonon and Coulomb scatterings at the channel and insulator interface. A thin-layer mobility model was included to account for the thin channel thickness. The measured electrical characteristics of the mNS-FET manufactured by hardware in the 7 nm dimension and the TCAD model parameters were calibrated to increase the accuracy of the model. A model library that accurately describes the current-voltage (I-V) and capacitance-voltage (C-V) characteristics extracted through TCAD simulation were then created using the industry-standard model BSIM-CMG. Next, to have the industry's standard 3 nm model circuit characteristics, the generated model library was centered to satisfy the target speed and power of the INV RO with fanout 3 (FO3), a benchmark circuit, to produce the final model library as summarized in Figure 2. Next, the PTM compact model was developed using Verilog-A to describe the I-V characteristics according to the voltage applied to the PTM as shown in Figure 3a. The developed PTM have a low resistivity ρMET in the metal phase and a large resistivity ρINS in the insulator phase, and the current determined by the voltage applied across the PTM device is compared with the critical current density (JC) at which the phase transition occurs. Such an operation in which either an insulator-metal transition (IMT) or a metalinsulator transition (MIT) occurs through the circuit simulator can be implemented. This Next, the PTM compact model was developed using Verilog-A to describe the I-V characteristics according to the voltage applied to the PTM as shown in Figure 3a. The developed PTM have a low resistivity ρ MET in the metal phase and a large resistivity ρ INS in the insulator phase, and the current determined by the voltage applied across the PTM device is compared with the critical current density (J C ) at which the phase transition occurs. Such an operation in which either an insulator-metal transition (IMT) or a metal-insulator transition (MIT) occurs through the circuit simulator can be implemented. This model reflects the characteristics of PTMs such as single crystalline VO 2 [9], NbO 2 [10], Te-based OTS [11] and HfO 2 [12], such as in Figure 3b, and the key parameters are summarized in Table 2. In addition, an RC-delay circuit is implemented inside Verilog-A to describe transition time (TT) [13], which has a very important effect on the circuit's dynamic operation characteristics. The dimension of the PTM, the PTM area (A PTM ) and the PTM length (L PTM ) are 30 nm × 15 nm (metal pitch × source/drain contact length) and 20 nm, respectively, considering the process design rule of the 3 nm tech. node. model reflects the characteristics of PTMs such as single crystalline VO2 [9], NbO2 [10], Te based OTS [11] and HfO2 [12], such as in Figure 3b, and the key parameters are summa rized in Table 2. In addition, an RC-delay circuit is implemented inside Verilog-A to de scribe transition time (TT) [13], which has a very important effect on the circuit's dynam operation characteristics. The dimension of the PTM, the PTM area (APTM) and the PTM length (LPTM) are 30 nm × 15 nm (metal pitch x source/drain contact length) and 20 nm respectively, considering the process design rule of the 3 nm tech. node. As shown in Figure 3c, the compact model of the hyper-FET with the PTM connecte in series to the source terminal of the baseline-FET has the transfer characteristics a shown in Figure 3d. Gate voltage conditions in which an IMT and MIT occur are name VGS_IMT and VGS_MIT, respectively. Assuming that the Vth-shift of the baseline FET is possibl through a process such as work-function engineering, the hyper-FET is expected to im prove on-current compared to the conventional mNS-FET under the iso-IOFF condition.

Hyper-FET Simulation Results and Discussions
For hyper-FET optimization, it is necessary to determine the electrical characteristic of each device under systematical analysis since there is a very close relationship betwee the composing baseline-FET and the electrical characteristics of the PTM. In this work, th key parameters of the PTM (ρINS, ρMET, JC_IMT, JC_MIT) were determined through the circu characteristics according to the switching time characteristics of the PTM and the variatio in baseline-FET IOFF characteristics, which were not considered in previous studie Through this, hyper-FET design optimization was performed, and circuit-level bench marks were performed with conventional 3 nm tech. mNS-FET.

Hyper-FET Design Optimization Flow
For optimal design of hyper-FET devices, device level DC (DD), circuit level DC (CD and circuit level transient (CT) analysis are essential, as shown in Figure 4. In this sub chapter, the systematic optimization process used in this work is described.  As shown in Figure 3c, the compact model of the hyper-FET with the PTM connected in series to the source terminal of the baseline-FET has the transfer characteristics as shown in Figure 3d. Gate voltage conditions in which an IMT and MIT occur are named V GS_IMT and V GS_MIT , respectively. Assuming that the V th -shift of the baseline FET is possible through a process such as work-function engineering, the hyper-FET is expected to improve on-current compared to the conventional mNS-FET under the iso-I OFF condition.

Hyper-FET Simulation Results and Discussions
For hyper-FET optimization, it is necessary to determine the electrical characteristics of each device under systematical analysis since there is a very close relationship between the composing baseline-FET and the electrical characteristics of the PTM. In this work, the key parameters of the PTM (ρ INS , ρ MET , J C_IMT , J C_MIT ) were determined through the circuit characteristics according to the switching time characteristics of the PTM and the variation in baseline-FET I OFF characteristics, which were not considered in previous studies. Through this, hyper-FET design optimization was performed, and circuit-level benchmarks were performed with conventional 3 nm tech. mNS-FET.

Hyper-FET Design Optimization Flow
For optimal design of hyper-FET devices, device level DC (DD), circuit level DC (CD), and circuit level transient (CT) analysis are essential, as shown in Figure 4. In this subchapter, the systematic optimization process used in this work is described. Nanomaterials 2022, 12, x FOR PEER REVIEW 5 of 12

Device Level DC Analysis
As he initial setting of the hyper-FET's VDD is used as the supply voltage of the baseline-FET, the conditions under which the resistance of the PTM (RPTM) for the hyper-FET have steep slope characteristics are discussed. In order to prevent the PTM's resistance of the metal state (RMET) from inhibiting the on-current of the hyper-FET, the ρMET is determined to be at least 100 times smaller than the resistance of the transistor in the on state (RON,TR at VGS = VDD, VDS = VDD). Then, the resistance of the insulator state of the PTM (RINS) is determined through Figure 5a, a graph where Hyper-FET ION/IOFF is mapped according to ρINS and ρMET made with reference to [6]. The gain increases in proportion to ρINS, but circuit operation may become difficult if too large, as shown in CD-3. Therefore, the ρINS is set so that RINS is less than the resistance of the transistor in the off state (ROFF,TR at VGS = 0 V, VDS = VDD), and ION/IOFF gain is checked compared to the baseline-FET. Then, JC_IMT&JC_MIT was designed to include IC_IMT&IC_MIT in the yellow box of Figure 5d,e, made with reference to [6], so that hyper-FET, as shown in Figure 5b, transitions within the given supply voltage range.
Furthermore, it is necessary to satisfy the condition of VGS_IMT> VGS_MIT to avoid negative hysteresis [14] in which the current of the hyper-FET oscillates, as shown in Figure  6a. This phenomenon can be understood through Figure 6b, which is a graph of voltage biased to the PTM (VPTM) and the current graph according to VGS. As VGS increases, VPTM increases, and when VPTM reaches critical voltage for an IMT (VC_IMT), negative differential resistance (NDR) occurs, in which VPTM decreases and current increases due to the lowered resistance. If the resistance of the transistor during transition (RTR) is less than or equal to a critical resistance (RC), the PTMs make hysteretic switching. On the other hand, because of the large RTR, the relatively lower VPTM is not sufficient to keep the PTM in a metal state, so MIT occurs again, and it repeats and oscillates like a green line, which is called negative hysteresis. If RTR > RC, VGS decreases from VDD and VPTM satisfies critical voltage for MIT(VC_MIT), the VPTM is too large to keep the PTMs in the resistance state, so they transition back to the metal state and oscillate in the same way. The critical resistance RC is as follows [14]:

Device Level DC Analysis
As he initial setting of the hyper-FET's V DD is used as the supply voltage of the baseline-FET, the conditions under which the resistance of the PTM (R PTM ) for the hyper-FET have steep slope characteristics are discussed. In order to prevent the PTM's resistance of the metal state (R MET ) from inhibiting the on-current of the hyper-FET, the ρ MET is determined to be at least 100 times smaller than the resistance of the transistor in the on state (R ON,TR at V GS = V DD , V DS = V DD ). Then, the resistance of the insulator state of the PTM (R INS ) is determined through Figure 5a, a graph where Hyper-FET I ON /I OFF is mapped according to ρ INS and ρ MET made with reference to [6]. The gain increases in proportion to ρ INS , but circuit operation may become difficult if too large, as shown in CD-3. Therefore, the ρ INS is set so that R INS is less than the resistance of the transistor in the off state (R OFF,TR at V GS = 0 V, V DS = V DD ), and I ON /I OFF gain is checked compared to the baseline-FET. Then, J C_IMT &J C_MIT was designed to include I C_IMT &I C_MIT in the yellow box of Figure 5d,e, made with reference to [6], so that hyper-FET, as shown in Figure 5b, transitions within the given supply voltage range.

Circuit Level DC Analysis
For functional operation of the logic circuit, the effect of hysteresis, which is not in the existing FET, on the VTC (Voltage-Transfer-Curve) is checked. First, as revealed in previous study [7], if an IMT does not occur before VM (logic threshold voltage) regardless of forwarding sweep or reverse sweep at the VTC in Figure 7a, the inverter current in Figure 7b does not satisfy the IMT condition and switching does not occur within the voltage range. Therefore, design JC_IMT and JC_MIT so that IC_IMT and IC_MIT are included in the orange box in Figure 5d,e are obtained with the inverter in Figure 5c since VGS_IMT & VGS_MIT < VDD/2 must be satisfied. In general, the characteristics are improved in proportion to ρINS, so ρINS,MAX as large as possible is required. However, when this maximum value is exceeded, the high-level output voltage's minimum (VOH, MIN) comes into contact with VM, and the VTC collapses, as shown by the green line in Figure 7c. In this case, it is necessary to either reduce JC_IMT with the first option, or reduce ρINS with the second option. Additionally, if ρMET is too large, it adversely affects VOUT, as shown in Figure 7d. To prevent this, the initial value of ρMET is set small enough.  Furthermore, it is necessary to satisfy the condition of V GS_IMT > V GS_MIT to avoid negative hysteresis [14] in which the current of the hyper-FET oscillates, as shown in Figure 6a. This phenomenon can be understood through Figure 6b, which is a graph of voltage biased to the PTM (V PTM ) and the current graph according to V GS . As V GS increases, V PTM increases, and when V PTM reaches critical voltage for an IMT (V C_IMT ), negative differential resistance (NDR) occurs, in which V PTM decreases and current increases due to the lowered resistance. If the resistance of the transistor during transition (R TR ) is less than or equal to a critical resistance (R C ), the PTMs make hysteretic switching. On the other hand, because of the large R TR , the relatively lower V PTM is not sufficient to keep the PTM in a metal state, so MIT occurs again, and it repeats and oscillates like a green line, which is called negative hysteresis. If R TR > R C , V GS decreases from V DD and V PTM satisfies critical voltage for MIT(V C_MIT ), the V PTM is too large to keep the PTMs in the resistance state, so they transition back to the metal state and oscillate in the same way. The critical resistance R C is as follows [14]: ceeded, the high-level output voltage's minimum (VOH, MIN) comes into contact w and the VTC collapses, as shown by the green line in Figure 7c. In this case, it is n to either reduce JC_IMT with the first option, or reduce ρINS with the second optio tionally, if ρMET is too large, it adversely affects VOUT, as shown in Figure 7d. To this, the initial value of ρMET is set small enough.    Lastly, I ON gain is obtained by matching the I OFF of hyper-FET with that of the baseline-FET, as shown in Figure 3d (of course, J C_IMT & J C_MIT adjustment is necessary afterwards).

Circuit Level DC Analysis
For functional operation of the logic circuit, the effect of hysteresis, which is not in the existing FET, on the VTC (Voltage-Transfer-Curve) is checked. First, as revealed in previous study [7], if an IMT does not occur before V M (logic threshold voltage) regardless of forwarding sweep or reverse sweep at the VTC in Figure 7a, the inverter current in Figure 7b does not satisfy the IMT condition and switching does not occur within the voltage range. Therefore, design J C_IMT and J C_MIT so that I C_IMT and I C_MIT are included in the orange box in Figure 5d,e are obtained with the inverter in Figure 5c since V GS_IMT & V GS_MIT < V DD /2 must be satisfied. In general, the characteristics are improved in proportion to ρ INS , so ρ INS,MAX as large as possible is required. However, when this maximum value is exceeded, the high-level output voltage's minimum (V OH, MIN ) comes into contact with V M , and the VTC collapses, as shown by the green line in Figure 7c. In this case, it is necessary to either reduce J C_IMT with the first option, or reduce ρ INS with the second option. Additionally, if ρ MET is too large, it adversely affects V OUT , as shown in Figure 7d. To prevent this, the initial value of ρ MET is set small enough.

Circuit Level Transient Analysis
In DC analysis, V OUT varies as much as ∆V OUT , as shown in Figure 7a, and it was revealed in the previous paper [7] that this phenomenon is prevented when the V DS_MIT (V DS at which an MIT occurs) of a hyper-FET is lower than 1 mV. If not, either J C_MIT or ρ MET should be reduced. After verifying that the given values have proper VTC, the performance is evaluated using an INV RO with a fan-out of 3 (FO3) with a hyper-FET. Evaluate various performances by adjusting J C_IMT and J C_MIT under the given ρ INS and ρ MET conditions. V DD scaling down is necessary if the target performance is not obtained because of the TT of the PTM, and has a large influence on speed limiting, which will be dealt with later in Section III-B. In this case, you must start over from DD-1. If the expected performance is satisfied, measure the power and performance and extract the parameters of the PTMs. Table 2 summarizes the key parameters of the PTMs obtained through the above flow when a 3 nm mNS-FET is used as a baseline-FET.

Benchmark with Conventional MOSFET Using INV RO
First, we discuss the results of studying the optimal characteristics of a hyper-FET for 3 nm tech. mNS-FET according to the TT of the PTM. Figure 8a shows the transient analysis of an INV RO according to the TT. The intrinsic transistor delay (τ transistor ) required for transition from V DD to GND (or vice versa) is measured as 66 ps. In the case of hyper-FET, the delay is longer than τ transistor due to the TT required for the PTM to change phase. This can be understood through the internal graph of Figure 8b showing the current flowing in the hyper-FET-based INV RO, because the higher the TT of the PTM, the lower the current level. According to Figure 8b, a graph in which the average current of the internal graph is normalized to the average current of the baseline-FET, When the TT is less than 10 ps, the current level is higher than the baseline-FET over all V DD ranges. However, when the TT ≥ 30 ps, a high current level was observed only in the ultra-low power region with a low τ transistor of 0.3 V or less. This indicates that the TT of the PTM suppresses the Hyper-FET from having a higher I ON compared to the baseline-FET at the device level. As the TT of the PTM increases, the circuit performance of the hyper-FET will deteriorate due to the increase in delay and the decrease in the current level. Therefore, in order to use it as a logic device of the hyper-FET, PTM having a TT much smaller than at least τ transistor should be used. Figure 8c shows the circuit characteristics according to the TT of the PTM. As the TT is higher, the current level is lowered and the delay is increased, so the performance and power of the circuit are both reduced. However, this tendency is reduced in the low V DD region, which is relatively smaller than the TT of the PTM due to the increased τ transistor of the transistor.
logic device of the hyper-FET, PTM having a TT much smaller than at least τtransistor should be used. Figure 8c shows the circuit characteristics according to the TT of the PTM. As the TT is higher, the current level is lowered and the delay is increased, so the performance and power of the circuit are both reduced. However, this tendency is reduced in the low VDD region, which is relatively smaller than the TT of the PTM due to the increased τtransistor of the transistor.   Figure 8d shows the circuit characteristics with a TT lower than τ transistor in the ultralow power region (V DD ≤ 0.25 V). The baseline-FET used was I OFF = 5 nA at V DD = 0.7 V, and the value of PTM-3 nm illustrated in Table 2 was used. Table 3 summarizes the operation frequency, active power gain, and supply voltage of the hyper-FET compared to the baseline-FET with V DD = 0.2 V. In all cases of Table 3, the circuit performance was improved even if the supply voltage of the hyper-FET was lower than that of the baseline-FET (V DD = 0.2 V), which is an I ON gain obtained with a steep slope, and the speed was high and the power was decreased due to the low voltage. In case of a TT = 50 ps, compared to a baseline-FET with V DD = 0.2 V, frequency shows a +8.96% and power −16.68% improvement, and their improvement increases as the TT decreases. This shows that at least the TT of the PTMs should be less than 50 ps for the logic device of hyper-FET based on 3 nm tech mNS-FETs. The following is the result of studying the optimal characteristics of hyper-FET according to V th of the baseline-FET. Figure 9a shows the transfer characteristic of 3 nm tech. mNS-FET according to various threshold voltages, and the RVT (Regular Voltage Threshold), the LVT (Low Voltage Threshold) and the SLVT (Super Low Voltage Threshold) are named for the case where I OFF is 0.2 nA, 2 nA, and 5 nA at V DD = 0.7 V of the baseline-FET, respectively. In addition, Figure 9b-d shows the optimized circuit characteristics in each case of V DD ≤ 0.25 V at TT = 50 ps. Table 4 summarizes the characteristics of the hyper-FET compared to the baseline FET with V DD = 0.2 V. As discussed earlier, the relationship between τ and the TT is significant. The overall current level, which is determined by the V th of the transistor, determines the τ transistor , and the higher the V th , the freer from the disturbance of the TT. In the case of the RVT device, the hyper-FET shows improvement in frequency by +18.40% and power by −31.45% compared to the baseline-FET. However, as shown in Figure 9c,d, it is observed that as V th decreases, τ transistor approaches the TT, and the amount of performance improvement decreases. In other words, if the designer knows the TT of the PTM, the higher the V th , the wider the device's versatility, and the range of V th that can be optimized is suggested.    Figure 10 shows the optimal PTM's key parameter obtained through the previous flow-based circuit simulation, and shows the tendency according to IOFF by normalizing the parameter of Single Crystalline (SC) VO2 [9], one of the most promising candidate PTMs. First, as can be seen from the circuit DC analysis above, the optimal value of ρINS decreases proportionally as the transistor resistance decreases. Therefore, as the off-current increases, the optimal ρINS decreases and becomes similar to that of SC VO2. On the other hand, the on-current does not change much, so ρMET set small enough is almost constant. In the case of the critical current density, it shows a tendency to increase as the offcurrent increases to switch within the current level. In this condition, when IOFF = 5 nA, JC_IMT is 28% larger and JC_MIT is 57% smaller than SC VO2. Through this work, if SC VO2 is used for hyper-FET utilization of 3 nm tech. mNS-FET, an SLVT device with IOFF = 5 nA is appropriate, and an adjustment of around 60% to the PTM parameter is required

Benchmark with Conventional MOSFET Using 6T SRAM
In a previous study [15], SRAM topology based on hyper-FET was reported, and a schematic is shown in Figure 11a. The device has a high-density structure with a transistor channel width ratio    Figure 10 shows the optimal PTM's key parameter obtained through the previous flow-based circuit simulation, and shows the tendency according to I OFF by normalizing the parameter of Single Crystalline (SC) VO 2 [9], one of the most promising candidate PTMs. First, as can be seen from the circuit DC analysis above, the optimal value of ρ INS decreases proportionally as the transistor resistance decreases. Therefore, as the off-current increases, the optimal ρ INS decreases and becomes similar to that of SC VO 2 . On the other hand, the on-current does not change much, so ρ MET set small enough is almost constant. In the case of the critical current density, it shows a tendency to increase as the off-current increases to switch within the current level. In this condition, when I OFF = 5 nA, J C_IMT is 28% larger and J C_MIT is 57% smaller than SC VO 2 . Through this work, if SC VO 2 is used for hyper-FET utilization of 3 nm tech. mNS-FET, an SLVT device with IOFF = 5 nA is appropriate, and an adjustment of around 60% to the PTM parameter is required.    Figure 10 shows the optimal PTM's key parameter obtained through the previous flow-based circuit simulation, and shows the tendency according to IOFF by normalizing the parameter of Single Crystalline (SC) VO2 [9], one of the most promising candidate PTMs. First, as can be seen from the circuit DC analysis above, the optimal value of ρINS decreases proportionally as the transistor resistance decreases. Therefore, as the off-current increases, the optimal ρINS decreases and becomes similar to that of SC VO2. On the other hand, the on-current does not change much, so ρMET set small enough is almost constant. In the case of the critical current density, it shows a tendency to increase as the offcurrent increases to switch within the current level. In this condition, when IOFF = 5 nA, JC_IMT is 28% larger and JC_MIT is 57% smaller than SC VO2. Through this work, if SC VO2 is used for hyper-FET utilization of 3 nm tech. mNS-FET, an SLVT device with IOFF = 5 nA is appropriate, and an adjustment of around 60% to the PTM parameter is required

Benchmark with Conventional MOSFET Using 6T SRAM
In a previous study [15], SRAM topology based on hyper-FET was reported, and a schematic is shown in Figure 11a. The device has a high-density structure with a transistor channel width ratio

Benchmark with Conventional MOSFET Using 6T SRAM
In a previous study [15], SRAM topology based on hyper-FET was reported, and a schematic is shown in Figure 11a. The device has a high-density structure with a transistor channel width ratio of pull up: pass gate: pull down = 1:1:1, and the PTM is added to only two pull-down (PD) transistor source terminals out of a total of six transistors, two each. Figure 11b-d shows the results of I read related to read time [16], Read Static Noise Margin RSNM, and Bit-line Write Margin BWRM [17], respectively, compared to mNS-FET 6T SRAM. It is assumed that '0' is stored in Q node and '1' is stored in QB node. In the proposed topology, the PTM in the insulator state of the source of PD1 decreases the strength of PD1 in the read operation and increases the read ability by maintaining the insulator state against noise in Q (or QB). In the write operation, V Q increases due to the PTM in the insulator state connected to PD2, and at the same time, the V QB increases by the PTM in the metal state of PD1 to increase the write ability. Also, the high resistance of the insulator state reduces standby power. As a result of the analysis, the RSNM improved by 43.9%, the BWRM improved by 9.4%, and the static power was reduced by 58.6%. In this case, I read is reduced by 41.4%. Table 5 summarizes the above SRAM index results. Nanomaterials 2022, 12, x FOR PEER REVIEW 10 of 12 of pull up: pass gate: pull down = 1:1:1, and the PTM is added to only two pull-down (PD) transistor source terminals out of a total of six transistors, two each. Figure 11b-d shows the results of Iread related to read time [16], Read Static Noise Margin RSNM, and Bit-line Write Margin BWRM [17], respectively, compared to mNS-FET 6T SRAM. It is assumed that '0' is stored in Q node and '1' is stored in QB node. In the proposed topology, the PTM in the insulator state of the source of PD1 decreases the strength of PD1 in the read operation and increases the read ability by maintaining the insulator state against noise in Q (or QB). In the write operation, VQ increases due to the PTM in the insulator state connected to PD2, and at the same time, the VQB increases by the PTM in the metal state of PD1 to increase the write ability. Also, the high resistance of the insulator state reduces standby power. As a result of the analysis, the RSNM improved by 43.9%, the BWRM improved by 9.4%, and the static power was reduced by 58.6%. In this case, Iread is reduced by 41.4%. Table 5 summarizes the above SRAM index results.

Conclusions
In this work, we present a systematic design guideline for optimal use of a hyper-FET according to the electrical characteristics of a baseline-FET and the PTM, and, using this, the INV RO and SRAM characteristics according to the PTM's TT and various characteristics of 3 nm-tech. mNS-FET was evaluated. The presented hyper-FET optimization flow chart allows other researchers to evaluate the optimized logic circuit characteristics of any baseline-FET. Through this, it was confirmed that the circuit characteristics were further improved as the transition time of the PTM was shorter than the intrinsic delay of the transistor. Analysis results show that in the case of 3 nm tech. mNS-FETs, the PTM's TT should be less than 50 ps in the ultra-low power region (VDD < 0.3 V). In addition, hyper-FET circuit characteristics according to various threshold voltage options of 3 nm tech. mNS-FET related to intrinsic delay were evaluated and the PTM parameter trends were analyzed accordingly. As a result, at the TT = 50 ps of the PTM, the SLVT device with IOFF = 5 nA showed a +8.96% improvement in speed and a −16.68% improvement in power at VDD = 0.15 V. The PTM-3 nm key parameters used in this work are similar to those of Single Crystalline VO2 [9]. Also, the 3 nm tech. mNS-FET based 6T SRAM structure with

Conclusions
In this work, we present a systematic design guideline for optimal use of a hyper-FET according to the electrical characteristics of a baseline-FET and the PTM, and, using this, the INV RO and SRAM characteristics according to the PTM's TT and various characteristics of 3 nm-tech. mNS-FET was evaluated. The presented hyper-FET optimization flow chart allows other researchers to evaluate the optimized logic circuit characteristics of any baseline-FET. Through this, it was confirmed that the circuit characteristics were further improved as the transition time of the PTM was shorter than the intrinsic delay of the transistor. Analysis results show that in the case of 3 nm tech. mNS-FETs, the PTM's TT should be less than 50 ps in the ultra-low power region (V DD < 0.3 V). In addition, hyper-FET circuit characteristics according to various threshold voltage options of 3 nm tech. mNS-FET related to intrinsic delay were evaluated and the PTM parameter trends were analyzed accordingly. As a result, at the TT = 50 ps of the PTM, the SLVT device with I OFF = 5 nA showed a +8.96% improvement in speed and a −16.68% improvement in power at V DD = 0.15 V. The PTM-3 nm key parameters used in this work are similar to those of Single Crystalline VO 2 [9]. Also, the 3 nm tech. mNS-FET based 6T SRAM structure with the PTM connected to the pull-down source terminal shows the RSNM improved by 43.9%, the BWRM improved by 9.4%, and the static power was reduced by 58.6%. In this case, I read is reduced by 41.4%. Our systematic optimization flow and the results of logic and memory circuit characteristics not only show the potential for ultra-low power applications of 3 nm technology, but also suggest a direction for PTM optimization of transistors with various characteristics.