Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

Two-dimensional (2D) semiconductors have been considered as promising candidates to fabricate ultimately scaled field-effect transistors (FETs), due to the atomically thin thickness and high carrier mobility. However, the performance of FETs based on 2D semiconductors has been limited by extrinsic factors, including high contact resistance, strong interfacial scattering, and unintentional doping. Among these challenges, contact resistance is a dominant issue, and important progress has been made in recent years. In this review, the Schottky–Mott model is introduced to show the ideal Schottky barrier, and we further discuss the contribution of the Fermi-level pinning effect to the high contact resistance in 2D semiconductor devices. In 2D FETs, Fermi-level pinning is attributed to the high-energy metal deposition process, which would damage the lattice of atomically thin 2D semiconductors and induce the pinning of the metal Fermi level. Then, two contact structures and the strategies to fabricate low-contact-resistance short-channel 2D FETs are introduced. Finally, our review provides practical guidelines for the realization of high-performance 2D-semiconductors-based FETs with low contact resistance and discusses the outlook of this field.


Introduction
The development of silicon complementary metal-oxide semiconductor (CMOS) integrated circuits has followed Moore's law for several decades. With the downscaling of the transistor dimensions into sub−20 nanometer nodes, two main challenges emerge, including drain-induced barrier lowering and degradation of the carrier mobility of Si. The former effect makes the transistor hard to turn off and results in a high off-current, which will cause high static power consumption. Emerging technologies such as FinFETs and Gate-All-Around (GAA) FETs have been employed to decrease the off-current. The mobility degradation is caused by the strong interfacial scattering, especially when the semiconductor thickness (t b ) is in the sub−3−nm regime [1]. Since the discovery of graphene, two-dimensional (2D) materials with atomic thickness exhibit high carrier mobility, even at t b < 3 nm [1], and show high immunity to the short-channel effect. These unique properties contribute to making 2D materials promising candidates to fabricate ultimately scaled transistors.
Although 2D materials present a unique pathway to build next-generation electronic devices, the construction of 2D-materials-based transistors (2D FETs) faces several technical challenges, including the growth of high-quality wafer-scale 2D materials [2], wafer-scale transfer methods [3], low contact resistance [4], and the high-quality dielectric interface [5]. These technical issues lead to large device-to-device variation [6] and the apparent discrepancy between the theoretical prediction and actual device performance, limiting the industrial applications of 2D materials in logic devices. Among these challenges, the contact problems are of vital important because the working mechanism of 2D FETs is based on the control of charge injection at the metal/2D junction, which is quite different from silicon CMOS transistors [4]. Recent studies show tremendous advances in the achievement of the ideal Mott-Schottky contact and the lowering of the contact resistance in 2D FETs [7][8][9]. The value of the contact resistance in 2D-materials-based transistors is approaching the requirement of the International Roadmap for Devices and Systems (IRDS) 2024 targets of logic transistors [10]. It is believed that a summary of emerging strategies to realize contact engineering in 2D FETs is urgently needed.
In this review, we present a comprehensive analysis of contact challenges in 2D FETs and discuss the recent research progress. We start with the origins of high contact resistance in 2D FETs. Then, two contact structures are presented, including top contact and edge contact, followed by several strategies to decrease the contact resistance. Finally, an outlook is provided to present the possible roadmap for the contact engineering of 2D FETs.

Fermi-Level Pinning and Pinning Factor
The Schottky barrier height (Φ SB ) and the contact resistance (R c ) are important quantitative parameters to examine the quality of the metal-2D material junction. In an ideal metal-semiconductor junction, Φ SB is determined by the Schottky-Mott rule based on the energy-level band alignment [11,12]: where Φ SB,n and Φ SB,p are the Schottky barrier heights for electrons and holes transport, Φ M represents the metal work function, χ s represents the electron affinity and I s represents the ionization potential of the semiconductor. The Φ SB is linearly dependent on the metal work function in the Schottky-Mott model, as shown in Figure 1a. However, the metal work function in FETs is always derived from the theoretical value, and it is pinned on a specific position within the bandgap of the semiconductor regardless of the selection of different metals, as shown in Figure 1b. This effect is called Fermi-level pinning, which makes the metal-semiconductor junction insensitive to the modulation of the metal work function. The pinning factor S represents the strength of Fermi-level pinning: The value of S in an ideal device is nearly equal to 1, but S is usually far away from 1 in 2D FETs. Liu [13,14]. The Fermi-level pinning effect strongly limits the performance of 2D semiconductor FETs.

Origins of Fermi-Level Pinning
Tersoff et al. successfully established a parameter-free metal-induced gap states (MIGS) model in bulk semiconductors to explain the Fermi-level pinning effect. The MIGS model can quantitatively explain the almost unchanged Schottky barrier height, which is independent of the metal work function in experiments [15]. Guo et al. employed the density functional theory (DFT) calculation to calculate the Schottky barrier height of 2D transition metal dichalcogenides (TMDs) by using different metal contacts. The calculated pinning factor is around 0.3, demonstrating a strong Fermi-level pinning effect. They found that direct bonding existed between the contact metal atoms and the chalcogen atoms of TMDs, leading to the MIGS [16]. The charge neutrality level serves as a quantitative characteristic of the electronic states of the defective semiconductor surface. Dominik et al. employed the primary theoretical model to calculate the charge neutrality level (CNL) of the monolayer TMDs, and they found that CNL is mostly placed near the mid-point of the semiconducting band gaps [17]. Although they use different theoretical calculation methods, both studies demonstrate that the MIGS can well-explain the Fermi-level pinning effect in 2D TMDs. Fermi-level pinning in 2D FETs mainly originates from the interfacial states. In the early stage of the study, Au, Ni and Pt with a high melting temperature are selected as the metal contact of 2D FETs, and they are deposited by evaporation or sputtering techniques, as shown in Figure 1a,b. This leads to the compact stacking of metal atoms on the surface of 2D layers, the wavefunction interaction between the metal and 2D semiconductor, and the rehybridizations of the semiconductor's original wavefunctions, resulting in the strong orbital overlap and MIGS. Photolithography and electron-beam lithography are common techniques to pattern the electrodes on 2D materials. Compared with bulk semiconductors, atomically thin 2D materials are sensitive to laser [18], electronbeam [19,20] and chemical solution [21]. Matsunage et al. reported that a relatively low electron-beam dose (280 µC/cm 2 ) used in conventional electron-beam lithography will induce strain in MoS 2 , leading to the local widening of the MoS 2 bandgap [22]. Preeti et al. systemically reported the doping effect of the conventional lithography process and the used chemical solvent. For example, acetone shows n-type doping and chloroform displays p-type doping on MoS 2 [23]. Meanwhile, the high-energy deposition process generates atomic defects at the interface of metal and 2D layers, facilitates the formation of covalent bonds [24,25], and gives rise to MIGS. Liu et al. experimentally showed that the typical metal deposition process induced defects at the contact region, which were observed by transmission electron microscope [13]. In 2D FETs with deposited metal contact, the injected charges are accumulated at the interfacial gap states regardless of the modulation of the metal work function, as shown in Figure 1c. The Fermi level is pinned around these gap states and a Schottky barrier is unavoidable, as shown in Figure 1d. Furthermore, heavy doping via ion implantation is employed in Si CMOS FETs to realize Fermi-level depinning and successfully achieve low contact resistance. However, the ion implantation cannot be well implemented on 2D materials. The implantation process will generate a large number of defects in atomically thin 2D materials and degrade the carrier transport.
Overall, the interface defects of the 2D semiconductor can induce the MIGS and greatly affect the contact quality. Furthermore, the conventional Fermi-level depinning methods in Si CMOS FETs are not suitable for 2D FETs. Therefore, the specific contact strategies should be tailored to meet the requirement of 2D FETs.

Contact Engineering of 2D FETs
FETs based on 2D materials can realize the ultimate downscaling of transistor dimensions. Along with the scaling of channel length, the scaling of contact region will produce new challenges. The most straightforward effect is the increase in contact resistance in the scaled contact region. The transfer length is the effective length with which carriers are transferred from the contact metal to channels. According to the current crowding model [28], carriers prefer to be transferred inside the more conductive metal and enter the semiconductor only near the end of metal-semiconductor contact regions, leading to a much smaller transfer length in comparison with the contact length. In this condition, the contact resistance is dependent on the transfer length, rather than the contact length, and its value can be calculated by the distributed resistor network model [29]. When the contact length is equal to or smaller than the transfer length, the charge injection is limited by the contact length. Therefore, a high-quality metal-semiconductor contact becomes more important in 2D FETs for ultra-scaled integrated circuits.
In order to overcome the strong Fermi-level pinning effect in 2D FETs, great progress has been made in the optimized metal-deposition process and the efficient carrier-modulation methods. In this section, state-of-the-art contact engineering strategies are systematically discussed.

Top Contact Engineering
Top contact refers to the deposition of metal contact on the surface of 2D layers. Due to the large surface-to-edge ratio, top contact is widely used in 2D FETs, and the fabrication process is simple and efficient. In this part, we introduce the use of bulk metals, bulk semimetals and 2D metals as top contact to optimize the contact of 2D FETs.

Bulk Metals
Defects in 2D materials, including intrinsic defects and the generated defect during the fabrication process, are the main origins of the Fermi-level pinning effect. Defects contribute to the interfacial trap states, which is directly related to the Fermi-level pinning effect. In early studies, bulk metals with low work function were used to achieve highperformance n-type 2D FETs. Kwon [26] due to the low work function of Sc (3.5 eV). An average Schottky barrier of 0.03 eV was achieved, which represents a very low contact barrier at that time. However, from the Schottky-Mott rule, the ideal Schottky barrier between Sc and MoS 2 should be negative because the work function of Sc is much lower than the CBM of MoS 2 . The positive Schottky barrier experimentally demonstrates Fermi-level pinning. In order to avoid the generation of defects during the metal-deposition process, transferred metal methods have been developed to preserve a sharp and clean interface between metal and 2D layers. Liu et al. reported realization of the van der Waals (vdW) contact through mechanically transferring metals to avoid chemical bonding and defect-induced gap states, as shown in Figure 2a,b. Owing to the atomically clean interface between metal and semiconductor, the majority carrier type and corresponding Schottky barrier height are strongly dependent on the metal work function (S = 0.96) [13]. Wang et al. further reported that the transferred metal can achieve low contact resistance in p-type WSe 2 FETs [31]. Due to the successful Fermi-level depinning, the work function of the transferred metal plays an important role in determining the charge injection and the device performance. Han et al. reported the use of molecular functionalization to change the work function of gold electrodes. Then, they fabricated top-contact FETs via the transfer of these pre-modified electrodes to tune the charge injection in MoS 2 FETs [32], demonstrating the modulation of the Schottky barrier. This method has also been used in 2D-materials-based resistive random-access memory, leading to a stable resistive switching performance [33]. Therefore, the transferred metal method represents a reliable way to create vdW contact [34], but wafer-scale metal transfer technology is still lacking. Moreover, the metal transfer process is mostly operated under the optical microscope and the alignment error is still huge, which is another big challenge.
The conventional metal-deposition process can be optimized to realize low contact resistance. Chris et al. reported that Au deposited in ultra-high vacuum (~10 −9 Torr) yields three times lower contact resistance than that in normal conditions, as shown in Figure 2c [35]. Wang et al. reported high performance p-type FETs based on single− and few−layer MoS 2 and WSe 2 by the electron-beam evaporation of high-work-function metals such as Pd and Pt, as shown in Figure 2d [8]. They conducted the metal evaporation at a high vacuum (<10 −8 torr) and low temperature (18 • C to 36 • C) to avoid high temperature damage to 2D semiconductors and to form vdW contact between the metal and semiconductor interface. Wang et al. reported the employment of In metal to build van der Waals contact with 2D semiconductors [36]. Due to the low melting point of In, the temperature of the 2D sample can be greatly decreased and a high-quality vdW interface can form, resulting in the Fermi-level depinning. Furthermore, In metal can be used to form stable alloys with other metals to modulate the work function. The use of In alloy as contact shows the advantages in the preservation of a high-quality contact interface and the effective tunability of the Schottky barrier. Kumar et al. employed In/Au alloy and Sn/Au alloy as contact electrodes in monolayer MoS 2 FETs, and they achieved an ultra-low contact resistance of 190 Ω·µm for In/Au alloy and 270 Ω·µm for Sn/Au alloy [37]. The use of metal alloys increases the thermal stability of low-melting-point metals and results in~450 • C temperature tolerance that is compatible with back-end-of-line (BEOL). Reprinted/adapted with permission from Ref. [8]. Copyright 2022, Springer Nature.

Bulk Semimetals
Recently, a powerful strategy was demonstrated by adopting semi-metals as contact electrodes to suppress MIGS and the Fermi-level pinning effect [7,38]. Shen et al. used semimetal Bi as the n-type contact metal in monolayer MoS 2 FETs [7]. Bi as a semi-metal has a negligible density of state at the Fermi level, and this induces the suppression of MIGS, as shown in Figure 3a,b. Furthermore, the use of Bi contact results in the degenerately doped MoS 2 with a high electron density of 1.5 × 10 13 cm −2 , and the Fermi level shifts from inside the bandgap to above the conduction band minimum. They achieved an ultralow contact resistance of 123 Ω·µm and a high current density of 1135 µA µm −1 in a 35−nm channel length MoS 2 FETs, as shown in Figure 3c,d. Owing to the highly efficient carrier injection between Bi and MoS 2 , the drain current density increased by lowering the temperature from room temperature to 77 K, as shown in Figure 3e. The values of Bi−MoS 2 contact resistance are comparable to those Si transistors and approach the quantum limit, as shown in Figure 3f. However, it has been observed that the MoS 2 FETs with Bi electrodes degraded severely after annealing at 300 and 400 • C [39]. Chou et al. reported semimetal antimony (Sb) as a novel contact metal to enable 2D materials towards advanced electronic device applications. They obtained a near-zero Schottky barrier height and a low contact resistance of 0.66 kΩ·µm [39]. Compared with Bi contact electrodes, the melting point of Sb (630 • C) is much larger than that of Bi (271 • C), although Sb has a higher work function than Bi. The transfer curves of MoS 2 FETs with Sb electrodes show a better electrical performance after high-temperature annealing. Overall, the use of semi-metal as a contact can greatly reduce MIGS and realize Fermi-level depinning in 2D FETs. Reprinted/adapted with permission from Ref. [7]. Copyright 2021, Springer Nature.

Two-Dimensional Metals/Semimetals
The MIGS are commonly found at the interface between 3D metal and 2D semiconductors. Liu et al. theoretically found that the interface states in the metal-semiconductor junction mainly derive from the 3D metal rather than the 2D semiconductor [40]. Therefore, they suggested replacing the 3D bulk metal with 2D metals. In their works, they predict that the Fermi-level pinning effect can be greatly suppressed when the 2D metal-2D semiconductor interface is well formed. The existence of a van der Waals distance between the 2D metal and the 2D semiconductor (3 to 4 Å) leads to the weak interlayer interaction, mild orbital overlap and the creation of interface dipole, contributing to Fermi-level depinning. Two-dimensional layered materials with metallic properties, such as graphene, 1T−MoS 2 and PtSe 2 , can be used to form vdW contacts on 2D semiconductors. Majumdar et al. employed 2H−TaSe 2 , graphene and degenerately-doped semiconducting SnSe 2 as contact metals [41]. They demonstrated that vdW contacts exhibited a universal Fermi-level depinning phenomenon, as shown in Figure 4a.
We present the theoretical band alignment of MoS 2 and WSe 2 with different 2D metals/semimetals, as shown in Figure 4b [9]. In a 20 nm−long and 1.3 nm−thick bi-layer WSe 2 transistor, an on-state current density of 1.72 mA µm −1 and a contact resistance of 0.25-0.54 kΩ·µm are achieved. PtSe 2 has been demonstrated to have a higher electron mobility than MoS 2 based on DFT calculations and experimentally extracted field-effect mobility [46]. Furthermore, PtSe 2 shows a layer-dependent semiconductor to semimetal transition. When a PtSe 2 transistor is built, few-layer PtSe 2 can serve as a semiconducting channel and bulk PtSe 2 can serve as the semimetallic contact [47][48][49]. Das et al. vertically integrated a thick PtSe 2 layer as source/drain contact on the surface of an ultrathin PtSe 2 channel, achieving a high performance of all PtSe 2 FETs, as shown in Figure 4e [50]. Zhang et al. reported barrier-free p-type WSe 2 FETs with a layered 1T'−WS 2 semimetal contact, as shown [51]. Owing to the high-quality interface between WSe 2 and 1T'−WS 2 , the WSe 2 FETs achieve a 50 meV Schottky barrier height and a high field-effect mobility of 97 cm 2 V −1 s −1 .
The growth of a graphene/MoS 2 heterostructure and the use of graphene as contact have shown the potential to lower the contact resistance of MoS 2 FETs [39]. In Mootheri et al.'s work, they further explored the function of 3D metal in the metal/graphene/MoS 2 contact structure. They proved that Ru-graphene contact show the lowest contact resistance of 9.34 kΩ·µm compared with Pd-graphene and Ni-graphene contact [52].
The use of 2D metallic materials is a simple and effective way to achieve high-quality vdW contact on a 2D semiconductor. However, the stacking of 2D vdW heterostructures needs a complex transfer process during the device fabrication, which is inefficient for the fabrication of large-scale devices. Reliable transfer methods that are suitable for waferscale fabrication with a high alignment accuracy need to be explored. Furthermore, it is quite challenging to use the mechanical transfer method to fabricate short-channel devices. The etching of 2D layers with sub−1−micron precision is essential to realize the contact engineering of 2D FETs.

Edge Contact Engineering
Wang et al. first showed the structure of edge contact in 2D FETs by encapsulating a 2D channel with hexagonal boron nitride (h−BN) and exposing the edge of the channel to the metal contact. The edge contact shows several advantages, including being free of Fermi-level pinning induced by interfacial states and having a lower tunnel barrier, strong orbital overlaps, the absence of a Schottky barrier, and high carrier injection efficiency [53]. As the thickness of the 2D layer is very small, effective orbital overlap or hybridization is required between the metal and the edge of the 2D layers, which is the prerequisite to building high-quality edge contact. In monolayer TMDs such as MoS 2 and WSe 2 , the CBM arises mainly from the d−orbitals of transition-metal atoms [54]. When a carrier is injected from metal to the conduction bands of MoS 2 , the edge contact exhibits strong orbital hybridization with transition-metal atoms [55] and leads to efficient carrier injection. In comparison, the top contact is formed on the surface of chalcogen atoms in monolayer MoS 2 with little influence on the CBM. The realization of edge contact on 2D materials is mainly through plasma etching, metallization and phase engineering. We discuss these methods in this section.  (Figure 5b) [55]. Figure 5c shows the high-resolution transmission electron microscopy (HR−TEM) cross-sectional image of the edge contact area. The use of high-work-function palladium (Pd) or gold (Au) enables a high-quality p-type dominant contact to MoS 2 layers without extrinsic doping, as shown in Figure 5d,e. Moreover, the h−BN encapsulation can suppress the interfacial scattering in 2D FETs and improve the long-term ambient stability, demonstrating the advantages of edge contact structure. Some 2D materials undergo gradual oxidation in air, especially MoTe 2 , black phosphorus and InSe, which can adopt the edge contact structure [57][58][59]. Except h−BN encapsulation, other insulating materials such as Al 2 O 3 [60] and PMMA [61] have also been used to form edge contacts on 2D semiconductors.

Phase Engineering and Degenerate Doping of 2D Layers
Two-dimensional TMDs have been reported with different polymorphs, including hexagonal (2H) and monoclinic or octahedral (1T, 1T') structures [62][63][64]. The 2H−phases MoS 2 and WSe 2 show semiconducting properties, while the 1T (1T') phase displays metallic transport behavior. Therefore, phase engineering between 2H and 1T (1T') can dramatically change the electronic properties of group−6 TMDs. The transition of group−6 TMDs from 2H to 1T (1T') phase at the contact region can be used to achieve high-quality edge contact in 2D FETs, which is similar to the degenerate doping at the source/drain region [65][66][67]. Kappera et al. first demonstrated the phase transition of MoS 2 from 2H to 1T through n-butyllithium treatment, as shown in Figure 6a [68]. The 1T/2H interface dominates the carrier injection, and the device exhibits an ultra-low contact resistance of 200-300 Ω·µm at zero gate bias. However, this 1T−phase MoS 2 is metastable, and the stability is a challenge. This method can be used not only in MoS 2 FETs [69], but also in other 2D-materials-based FETs. Cho et al. reported the laser-induced phase transition of MoTe 2 from 2H to 1T' phase, as shown in Figure 6b [70]. The 1T' phase region works as the edge contact of the 2H phase channel to improve the carrier injection, and the Schottky barrier height is decreased to 10 meV. They further reported the reversible phase transition of MoTe 2 between 2H and 1T' by controlling the annealing temperature and the cooling speed [71]. The 1T' MoTe 2 has a thermal stability of 300°C, which is higher than 1T phase MoS 2 [72]. Reversible phase transition of WSe 2 layers has been reported by Ma et al. The n-butyllithium treatment on 2H-phase WSe 2 induces the semiconducting to metallic phase transition, and the thermal annealing drives the metallic phase Wse 2 to be converted back to the semiconducting phase, as shown in Figure 6c [73].
The generation of defects by weak plasma treatment can also Induce phase transition. Zhu et al. reported a facile, clean, controllable and scalable phase-engineering technique for monolayer MoS 2 , as shown in Figure 6d [74]. Point defects (single S vacancies) result in the 2H to 1T phase transitions. Akinola et al. also reported a phase transformation in a region of a layered semiconductor PdSe 2 , as shown in Figure 6e [75]. This phase transition is driven by defects created by argon plasma, and this turns PdSe 2 into Pd 17 Se 15 . Recently, Cai et al. performed plasma treatment on patterned MoS 2 layer to induce a local bonding distortion. This distorted area works as a semi-metallic bridge between the metal and the pristine channel to facilitate the charge injection [76]. The TEM image shows that the distorted MoS 2 displays an octahedral structure, and the device exhibits an ultra-low contact resistance of 90 Ω·µm, approaching the quantum limit.
Another strategy is the introduction of degenerate doping during the growth process. Li et al. reported that unidirectionally aligned monolayer Fe−doped MoS 2 domains are prepared on two-inch commercial c-plane sapphire, suggesting the feasibility of synthesizing wafer-scale-doped 2D semiconductors with outstanding device performance, as shown in Figure 6f

Inserting Interlayer between Metal and 2D Materials
In previous sections, contact engineering has been realized by using 3D or 2D metallic materials, performing phase transition and introducing degenerate doping. Another strategy to suppress the Fermi-level pinning effect is introduced in this section. To decouple the orbital overlap, a thin insulating tunnel layer is inserted between the metal and semiconductor. The insulating buffer layer will increase the distance between the metal and semiconductor, which is an efficient way to suppress interface interaction, and the interlayer will inhibit high energy damage induced by the metal deposition process. The decrease in MIGS results in a reduced Schottky barrier height [82]. However, the thickness of the interlayer should be properly tuned because the electron tunneling through the insulating buffer layer is mandatory. Furthermore, the charges are injected by direct tunneling or Fowler-Nordheim tunneling dependent on the band alignment. Chen et al. first reported the insertion of a thin MgO film for Co−contacted monolayer MoS 2 FETs [83]. The Schottky barrier height was reduced from 60 to 9.7 meV with the increasing MgO thickness from 0.9 to 2 nm. Lee et al. showed a statistical study of Schottky barrier height by inserting a thin tunneling Ta 2 O 5 layer between MoS 2 and metal contacts, as shown in Figure 7a [84]. They pointed out that a thin tunnel layer with a sub−2 nm thickness could allow efficient tunneling, as shown in Figure 7b. The remarkably suppressed Fermi-level pinning has also been demonstrated with other dielectric layers, such as h−BN [82,85,86], ZnO [87] and TiO 2 [14]. Kwon et al. reported that defect-free vdW contacts were formed via a metal-deposition process with a selenium buffer layer on 2D layers, as shown in Figure 7c

Determination Methods of Contact Resistance
The determination method of contact resistance in 2D FETs should be consistent in different works for ease of comparison. There are three commonly used methods, including the transfer length method (TLM), Y−function method and four-point probe method.

Transfer Length Method
The transfer length method is widely used in 2D FETs to extract contact resistance [35]. The device should be fabricated with different channel lengths, as shown in Figure 8a. R total is the resistance between sourse and drain electrodes, R sh is the channel sheet resistance and W is the channel width. When R total /W is plotted versus the channel length, the y-axis intercept of the fitting line is equal to 2R c . The contact resistance value extracted by TLM can have large variation when the channel length is large and the sheet resistance is huge. To minimize the estimated error, short-channel devices should be used, and statistic results are preferred.

Y-Function Method
The Y-function method requires only one transfer curve I d − I g at the linear regime by applying a large gate voltage and a small source-drain voltage V d V g [90]. When the transconductance starts to decrease, the contact effect will dominate the µ attenuation and the contact resistance can be derived.
We assume that the contact resistance is comparable with the channel resistance. The source-drain voltage will drop at the contact region and I d can be expressed as the following equation where µ 0 , θ 0 and V th are the intrinsic mobility in the linear regime, first-order mobility attenuation coefficient, and the threshold voltage, respectively. When V g − V th 0.5V d , 0.5V d can be ignored. The effective mobility attenuation factor θ represents the contribution from both θ 0 and R c . Therefore, I d can be written as the following equation The Y-function was defined as where g m is transconductance g m = ∂I d /∂V g . The value s 1 can be extracted from the slope of the Y−function versus V g . The value s 2 can be extracted from the slope of 1 √ g m versus V g . The R c follows the equation:

Four-Point Probe Method
The four-point probe method to extract contact resistance requires the fabrication of a device with the desired structure, as shown in Figure 8b. The contact resistance is given by the following equation:

Conclusions and Outlook
This review focused on the contact engineering of 2D FETs and discussed the origins of high contact resistance, the structure of top contact and edge contact, and the contact engineering in both structures. We believe that Fermi-level pinning in 2D devices is dominantly induced by interfacial gap states, and the solution to this challenge is to make a sharp and clean vdW interface at the contact regions. The top contact is compatible with the conventional Si CMOS process, but it is very challenging to control the deposition condition to achieve a vdW interface. The edge contact can be used in both top-and bottom-gate 2D FETs, but the accurate etching of 2D materials with little damage should be developed by using the dry etching technologies, such as reactive ion etching, plasma etching and inductively coupled plasma etching. Realization of the edge contact requires a much more complex fabrication process than that of the top contact. Although the edge contact methods can often achieve ultra-low contact resistance, the small contact area still limits the electrical performance of 2D FETs, such as on-state current. The insertion of a buffer layer provides another pathway to reduce the Fermi-level pinning effect, which can be combined with other contact-engineering strategies. In 2D GAAFETs, it is necessary to vertically integrate 2D FETs into integrated circuits, which is more challenging to achieve a good metal contact.
Overall, it is important to develop a CMOS-compatible contact deposition process to achieve large-scale 2D FETs with high-performance transport properties. One promising method is to employ an alloy composed of low-melting-point metal and high-melting point-metal as contact to simultaneously achieve vdW contact and increase the temperature endurance for the BEOL process. Another promising method is to build a high-quality mixed contact by combining the advantages of edge contact and top contact to overcome the small contact areas and Fermi-level pinning.